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msm: ep_pcie: Avoid writing req_L1_exit during dstate change

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Avoid setting this bit to make sure device stays in L1SS when D-state is
changes to D3 Hot.

Because of device not staying in L1SS the PCIe link was going through
recovery all the time power consumption was higher than expected value.

Change-Id: Id06996745171e62d3a9dbc499c693f8a9870b2ea
Signed-off-by: Pallavi Singh <quic_pallsing@quicinc.com>
This commit is contained in:
Pallavi Singh 2024-06-17 23:16:56 +05:30
commit bbf350b175
1 changed files with 0 additions and 8 deletions
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8
drivers/platform/msm/ep_pcie/ep_pcie_core.c
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@ -2352,7 +2352,6 @@ static irqreturn_t ep_pcie_handle_dstate_change_irq(int irq, void *data)
EP_PCIE_DBG(dev,
"PCIe V%d: No. %ld change to D3 state\n",
dev->rev, dev->d3_counter);
ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, 0, BIT(1));
dev->pme_en_d3 = readl_relaxed(dev->dm_core +
PCIE20_CON_STATUS) & PCIE20_MASK_PME_EN;
@ -2370,13 +2369,6 @@ static irqreturn_t ep_pcie_handle_dstate_change_irq(int irq, void *data)
} else if (dstate == 0) {
dev->l23_ready = false;
dev->d0_counter++;
/*
* When device is trasistion back to D0 from D3hot
* (without D3cold), REQ_EXIT_L1 bit won't get cleared.
* And L1 would get blocked till next D3cold.
* So clear it explicitly during D0.
*/
ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(1), 0);
atomic_set(&dev->host_wake_pending, 0);
EP_PCIE_DBG(dev,