From bbf44eeba1967425a0915317e55a300ec5728d2c Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Mon, 20 Jan 2020 20:38:05 +0530 Subject: [PATCH] asoc: codecs: Update muxsel registers only when clock counts are not stale During SSR/PDR use cases, core clock count in different macros becomes stale and muxsel registers are accessed leading to NOC errors. Update muxsel registers only after clock counts are reset after SSR/PDR recovery. Change-Id: I656f8e7ddc8a92a325c2ba644f1a945cbafb08a0 Signed-off-by: Aditya Bavanari --- asoc/codecs/bolero/bolero-cdc.c | 4 ++++ asoc/codecs/bolero/bolero-cdc.h | 3 ++- asoc/codecs/bolero/bolero-clk-rsc.c | 30 +++++++++++++++++++---------- 3 files changed, 26 insertions(+), 11 deletions(-) diff --git a/asoc/codecs/bolero/bolero-cdc.c b/asoc/codecs/bolero/bolero-cdc.c index ec2a304034fa..0918652d3222 100644 --- a/asoc/codecs/bolero/bolero-cdc.c +++ b/asoc/codecs/bolero/bolero-cdc.c @@ -834,6 +834,10 @@ static int bolero_ssr_enable(struct device *dev, void *data) priv->component, BOLERO_MACRO_EVT_CLK_RESET, 0x0); } + + if (priv->rsc_clk_cb) + priv->rsc_clk_cb(priv->clk_dev, BOLERO_MACRO_EVT_SSR_GFMUX_UP); + trace_printk("%s: clk count reset\n", __func__); regcache_cache_only(priv->regmap, false); mutex_lock(&priv->clk_lock); diff --git a/asoc/codecs/bolero/bolero-cdc.h b/asoc/codecs/bolero/bolero-cdc.h index ca4324ac4a45..a1a2b7158637 100644 --- a/asoc/codecs/bolero/bolero-cdc.h +++ b/asoc/codecs/bolero/bolero-cdc.h @@ -52,7 +52,8 @@ enum { BOLERO_MACRO_EVT_CLK_RESET, BOLERO_MACRO_EVT_REG_WAKE_IRQ, BOLERO_MACRO_EVT_RX_COMPANDER_SOFT_RST, - BOLERO_MACRO_EVT_BCS_CLK_OFF + BOLERO_MACRO_EVT_BCS_CLK_OFF, + BOLERO_MACRO_EVT_SSR_GFMUX_UP, }; enum { diff --git a/asoc/codecs/bolero/bolero-clk-rsc.c b/asoc/codecs/bolero/bolero-clk-rsc.c index 7e28c5bfeb86..b134819e0c16 100644 --- a/asoc/codecs/bolero/bolero-clk-rsc.c +++ b/asoc/codecs/bolero/bolero-clk-rsc.c @@ -38,6 +38,7 @@ struct bolero_clk_rsc { int reg_seq_en_cnt; int va_tx_clk_cnt; bool dev_up; + bool dev_up_gfmux; u32 num_fs_reg; u32 *fs_gen_seq; int default_clk_id[MAX_CLK]; @@ -65,10 +66,14 @@ static int bolero_clk_rsc_cb(struct device *dev, u16 event) } mutex_lock(&priv->rsc_clk_lock); - if (event == BOLERO_MACRO_EVT_SSR_UP) + if (event == BOLERO_MACRO_EVT_SSR_UP) { priv->dev_up = true; - else if (event == BOLERO_MACRO_EVT_SSR_DOWN) + } else if (event == BOLERO_MACRO_EVT_SSR_DOWN) { priv->dev_up = false; + priv->dev_up_gfmux = false; + } else if (event == BOLERO_MACRO_EVT_SSR_GFMUX_UP) { + priv->dev_up_gfmux = true; + } mutex_unlock(&priv->rsc_clk_lock); return 0; @@ -282,10 +287,12 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, * care in DSP itself */ if (clk_id != VA_CORE_CLK) { - iowrite32(0x1, clk_muxsel); - muxsel = ioread32(clk_muxsel); - trace_printk("%s: muxsel value after enable: %d\n", - __func__, muxsel); + if (priv->dev_up_gfmux) { + iowrite32(0x1, clk_muxsel); + muxsel = ioread32(clk_muxsel); + trace_printk("%s: muxsel value after enable: %d\n", + __func__, muxsel); + } bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false); @@ -313,10 +320,12 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, * This configuration would be taken * care in DSP itself. */ - iowrite32(0x0, clk_muxsel); - muxsel = ioread32(clk_muxsel); - trace_printk("%s: muxsel value after disable: %d\n", - __func__, muxsel); + if (priv->dev_up_gfmux) { + iowrite32(0x0, clk_muxsel); + muxsel = ioread32(clk_muxsel); + trace_printk("%s: muxsel value after disable: %d\n", + __func__, muxsel); + } } } if (priv->clk[clk_id + NPL_CLK_OFFSET]) @@ -706,6 +715,7 @@ static int bolero_clk_rsc_probe(struct platform_device *pdev) } priv->dev = &pdev->dev; priv->dev_up = true; + priv->dev_up_gfmux = true; mutex_init(&priv->rsc_clk_lock); mutex_init(&priv->fs_gen_lock); dev_set_drvdata(&pdev->dev, priv);