From bc230a705e885acac11b63f71f161df51b3bf2c4 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 14:19:19 +0530 Subject: [PATCH] ARM: dts: msm: Add LLCC device nodes for Direwolf Add device nodes for Last level cache controller for Direwolf target. Change-Id: I7b207f8a63a9f466e5e3f1767b130137704fc73d --- bindings/arm/msm/qcom,llcc.txt | 1 + qcom/direwolf.dtsi | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index dc9c20cfec7b..2705ee9b1b5d 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -15,6 +15,7 @@ Properties: or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" or "qcom,yupik-llcc" or "qcom,sm8150-llcc" or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc" + or "qcom,direwolf-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index d2c3003d9a91..3eb5ba2ff0aa 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -1082,6 +1082,16 @@ #mbox-cells = <1>; }; + cache-controller@9200000 { + compatible = "qcom,direwolf-llcc", "qcom,llcc-v2"; + reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + interrupts = ; + clocks = <&aopcc QDSS_CLK>; + clock-names = "qdss_clk"; + }; + llcc_pmu: llcc-pmu@9095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x09095000 0x300>;