mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
Merge branch 'devel-stable' into for-next
This commit is contained in:
commit
bce5669be3
1043 changed files with 15846 additions and 8929 deletions
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@ -105,7 +105,7 @@ static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir)
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|||
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do {
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||||
/* flush any pending transfer */
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hw_write(ci, OP_ENDPTFLUSH, BIT(n), BIT(n));
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hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));
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||||
while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))
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cpu_relax();
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||||
} while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
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||||
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|
@ -205,7 +205,7 @@ static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl)
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if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
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return -EAGAIN;
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hw_write(ci, OP_ENDPTPRIME, BIT(n), BIT(n));
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hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));
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while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
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cpu_relax();
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|
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@ -63,8 +63,10 @@ ssize_t usb_store_new_id(struct usb_dynids *dynids,
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dynid->id.idProduct = idProduct;
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dynid->id.match_flags = USB_DEVICE_ID_MATCH_DEVICE;
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if (fields > 2 && bInterfaceClass) {
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if (bInterfaceClass > 255)
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return -EINVAL;
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if (bInterfaceClass > 255) {
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retval = -EINVAL;
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goto fail;
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}
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dynid->id.bInterfaceClass = (u8)bInterfaceClass;
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dynid->id.match_flags |= USB_DEVICE_ID_MATCH_INT_CLASS;
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@ -73,17 +75,21 @@ ssize_t usb_store_new_id(struct usb_dynids *dynids,
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if (fields > 4) {
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const struct usb_device_id *id = id_table;
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if (!id)
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return -ENODEV;
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if (!id) {
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retval = -ENODEV;
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goto fail;
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}
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for (; id->match_flags; id++)
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if (id->idVendor == refVendor && id->idProduct == refProduct)
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break;
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if (id->match_flags)
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if (id->match_flags) {
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dynid->id.driver_info = id->driver_info;
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else
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return -ENODEV;
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} else {
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retval = -ENODEV;
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goto fail;
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}
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}
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spin_lock(&dynids->lock);
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@ -95,6 +101,10 @@ ssize_t usb_store_new_id(struct usb_dynids *dynids,
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if (retval)
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return retval;
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return count;
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fail:
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kfree(dynid);
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return retval;
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}
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EXPORT_SYMBOL_GPL(usb_store_new_id);
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@ -1032,7 +1032,6 @@ static int register_root_hub(struct usb_hcd *hcd)
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dev_name(&usb_dev->dev), retval);
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return retval;
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}
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usb_dev->lpm_capable = usb_device_supports_lpm(usb_dev);
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}
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retval = usb_new_device (usb_dev);
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@ -128,7 +128,7 @@ struct usb_hub *usb_hub_to_struct_hub(struct usb_device *hdev)
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return usb_get_intfdata(hdev->actconfig->interface[0]);
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}
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int usb_device_supports_lpm(struct usb_device *udev)
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static int usb_device_supports_lpm(struct usb_device *udev)
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{
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/* USB 2.1 (and greater) devices indicate LPM support through
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* their USB 2.0 Extended Capabilities BOS descriptor.
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@ -149,11 +149,6 @@ int usb_device_supports_lpm(struct usb_device *udev)
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"Power management will be impacted.\n");
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||||
return 0;
|
||||
}
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||||
|
||||
/* udev is root hub */
|
||||
if (!udev->parent)
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||||
return 1;
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||||
|
||||
if (udev->parent->lpm_capable)
|
||||
return 1;
|
||||
|
||||
|
|
|
|||
|
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@ -35,7 +35,6 @@ extern int usb_get_device_descriptor(struct usb_device *dev,
|
|||
unsigned int size);
|
||||
extern int usb_get_bos_descriptor(struct usb_device *dev);
|
||||
extern void usb_release_bos_descriptor(struct usb_device *dev);
|
||||
extern int usb_device_supports_lpm(struct usb_device *udev);
|
||||
extern char *usb_cache_string(struct usb_device *udev, int index);
|
||||
extern int usb_set_configuration(struct usb_device *dev, int configuration);
|
||||
extern int usb_choose_configuration(struct usb_device *udev);
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||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
|
|||
int retval = 0;
|
||||
|
||||
if (!select_phy)
|
||||
return -ENODEV;
|
||||
return 0;
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||||
|
||||
usbcfg = readl(hsotg->regs + GUSBCFG);
|
||||
|
||||
|
|
|
|||
|
|
@ -2565,25 +2565,14 @@ static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
|
|||
struct usb_host_endpoint *ep)
|
||||
{
|
||||
struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
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||||
int is_control = usb_endpoint_xfer_control(&ep->desc);
|
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int is_out = usb_endpoint_dir_out(&ep->desc);
|
||||
int epnum = usb_endpoint_num(&ep->desc);
|
||||
struct usb_device *udev;
|
||||
unsigned long flags;
|
||||
|
||||
dev_dbg(hsotg->dev,
|
||||
"DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
|
||||
ep->desc.bEndpointAddress);
|
||||
|
||||
udev = to_usb_device(hsotg->dev);
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|
||||
spin_lock_irqsave(&hsotg->lock, flags);
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||||
|
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usb_settoggle(udev, epnum, is_out, 0);
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if (is_control)
|
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usb_settoggle(udev, epnum, !is_out, 0);
|
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dwc2_hcd_endpoint_reset(hsotg, ep);
|
||||
|
||||
spin_unlock_irqrestore(&hsotg->lock, flags);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -124,6 +124,9 @@ static int dwc2_driver_probe(struct platform_device *dev)
|
|||
int retval;
|
||||
int irq;
|
||||
|
||||
if (usb_disabled())
|
||||
return -ENODEV;
|
||||
|
||||
match = of_match_device(dwc2_of_match_table, &dev->dev);
|
||||
if (match && match->data) {
|
||||
params = match->data;
|
||||
|
|
|
|||
|
|
@ -360,24 +360,30 @@ static inline void usb_dma_writel(struct bcm63xx_udc *udc, u32 val, u32 off)
|
|||
bcm_writel(val, udc->iudma_regs + off);
|
||||
}
|
||||
|
||||
static inline u32 usb_dmac_readl(struct bcm63xx_udc *udc, u32 off)
|
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static inline u32 usb_dmac_readl(struct bcm63xx_udc *udc, u32 off, int chan)
|
||||
{
|
||||
return bcm_readl(udc->iudma_regs + IUDMA_DMAC_OFFSET + off);
|
||||
return bcm_readl(udc->iudma_regs + IUDMA_DMAC_OFFSET + off +
|
||||
(ENETDMA_CHAN_WIDTH * chan));
|
||||
}
|
||||
|
||||
static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off)
|
||||
static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off,
|
||||
int chan)
|
||||
{
|
||||
bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off);
|
||||
bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off +
|
||||
(ENETDMA_CHAN_WIDTH * chan));
|
||||
}
|
||||
|
||||
static inline u32 usb_dmas_readl(struct bcm63xx_udc *udc, u32 off)
|
||||
static inline u32 usb_dmas_readl(struct bcm63xx_udc *udc, u32 off, int chan)
|
||||
{
|
||||
return bcm_readl(udc->iudma_regs + IUDMA_DMAS_OFFSET + off);
|
||||
return bcm_readl(udc->iudma_regs + IUDMA_DMAS_OFFSET + off +
|
||||
(ENETDMA_CHAN_WIDTH * chan));
|
||||
}
|
||||
|
||||
static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off)
|
||||
static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off,
|
||||
int chan)
|
||||
{
|
||||
bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off);
|
||||
bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off +
|
||||
(ENETDMA_CHAN_WIDTH * chan));
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||||
}
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||||
|
||||
static inline void set_clocks(struct bcm63xx_udc *udc, bool is_enabled)
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||||
|
|
@ -638,7 +644,7 @@ static void iudma_write(struct bcm63xx_udc *udc, struct iudma_ch *iudma,
|
|||
} while (!last_bd);
|
||||
|
||||
usb_dmac_writel(udc, ENETDMAC_CHANCFG_EN_MASK,
|
||||
ENETDMAC_CHANCFG_REG(iudma->ch_idx));
|
||||
ENETDMAC_CHANCFG_REG, iudma->ch_idx);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -694,9 +700,9 @@ static void iudma_reset_channel(struct bcm63xx_udc *udc, struct iudma_ch *iudma)
|
|||
bcm63xx_fifo_reset_ep(udc, max(0, iudma->ep_num));
|
||||
|
||||
/* stop DMA, then wait for the hardware to wrap up */
|
||||
usb_dmac_writel(udc, 0, ENETDMAC_CHANCFG_REG(ch_idx));
|
||||
usb_dmac_writel(udc, 0, ENETDMAC_CHANCFG_REG, ch_idx);
|
||||
|
||||
while (usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG(ch_idx)) &
|
||||
while (usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG, ch_idx) &
|
||||
ENETDMAC_CHANCFG_EN_MASK) {
|
||||
udelay(1);
|
||||
|
||||
|
|
@ -713,10 +719,10 @@ static void iudma_reset_channel(struct bcm63xx_udc *udc, struct iudma_ch *iudma)
|
|||
dev_warn(udc->dev, "forcibly halting IUDMA channel %d\n",
|
||||
ch_idx);
|
||||
usb_dmac_writel(udc, ENETDMAC_CHANCFG_BUFHALT_MASK,
|
||||
ENETDMAC_CHANCFG_REG(ch_idx));
|
||||
ENETDMAC_CHANCFG_REG, ch_idx);
|
||||
}
|
||||
}
|
||||
usb_dmac_writel(udc, ~0, ENETDMAC_IR_REG(ch_idx));
|
||||
usb_dmac_writel(udc, ~0, ENETDMAC_IR_REG, ch_idx);
|
||||
|
||||
/* don't leave "live" HW-owned entries for the next guy to step on */
|
||||
for (d = iudma->bd_ring; d <= iudma->end_bd; d++)
|
||||
|
|
@ -728,11 +734,11 @@ static void iudma_reset_channel(struct bcm63xx_udc *udc, struct iudma_ch *iudma)
|
|||
|
||||
/* set up IRQs, UBUS burst size, and BD base for this channel */
|
||||
usb_dmac_writel(udc, ENETDMAC_IR_BUFDONE_MASK,
|
||||
ENETDMAC_IRMASK_REG(ch_idx));
|
||||
usb_dmac_writel(udc, 8, ENETDMAC_MAXBURST_REG(ch_idx));
|
||||
ENETDMAC_IRMASK_REG, ch_idx);
|
||||
usb_dmac_writel(udc, 8, ENETDMAC_MAXBURST_REG, ch_idx);
|
||||
|
||||
usb_dmas_writel(udc, iudma->bd_ring_dma, ENETDMAS_RSTART_REG(ch_idx));
|
||||
usb_dmas_writel(udc, 0, ENETDMAS_SRAM2_REG(ch_idx));
|
||||
usb_dmas_writel(udc, iudma->bd_ring_dma, ENETDMAS_RSTART_REG, ch_idx);
|
||||
usb_dmas_writel(udc, 0, ENETDMAS_SRAM2_REG, ch_idx);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -2035,7 +2041,7 @@ static irqreturn_t bcm63xx_udc_data_isr(int irq, void *dev_id)
|
|||
spin_lock(&udc->lock);
|
||||
|
||||
usb_dmac_writel(udc, ENETDMAC_IR_BUFDONE_MASK,
|
||||
ENETDMAC_IR_REG(iudma->ch_idx));
|
||||
ENETDMAC_IR_REG, iudma->ch_idx);
|
||||
bep = iudma->bep;
|
||||
rc = iudma_read(udc, iudma);
|
||||
|
||||
|
|
@ -2175,18 +2181,18 @@ static int bcm63xx_iudma_dbg_show(struct seq_file *s, void *p)
|
|||
seq_printf(s, " [ep%d]:\n",
|
||||
max_t(int, iudma_defaults[ch_idx].ep_num, 0));
|
||||
seq_printf(s, " cfg: %08x; irqstat: %08x; irqmask: %08x; maxburst: %08x\n",
|
||||
usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG(ch_idx)),
|
||||
usb_dmac_readl(udc, ENETDMAC_IR_REG(ch_idx)),
|
||||
usb_dmac_readl(udc, ENETDMAC_IRMASK_REG(ch_idx)),
|
||||
usb_dmac_readl(udc, ENETDMAC_MAXBURST_REG(ch_idx)));
|
||||
usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG, ch_idx),
|
||||
usb_dmac_readl(udc, ENETDMAC_IR_REG, ch_idx),
|
||||
usb_dmac_readl(udc, ENETDMAC_IRMASK_REG, ch_idx),
|
||||
usb_dmac_readl(udc, ENETDMAC_MAXBURST_REG, ch_idx));
|
||||
|
||||
sram2 = usb_dmas_readl(udc, ENETDMAS_SRAM2_REG(ch_idx));
|
||||
sram3 = usb_dmas_readl(udc, ENETDMAS_SRAM3_REG(ch_idx));
|
||||
sram2 = usb_dmas_readl(udc, ENETDMAS_SRAM2_REG, ch_idx);
|
||||
sram3 = usb_dmas_readl(udc, ENETDMAS_SRAM3_REG, ch_idx);
|
||||
seq_printf(s, " base: %08x; index: %04x_%04x; desc: %04x_%04x %08x\n",
|
||||
usb_dmas_readl(udc, ENETDMAS_RSTART_REG(ch_idx)),
|
||||
usb_dmas_readl(udc, ENETDMAS_RSTART_REG, ch_idx),
|
||||
sram2 >> 16, sram2 & 0xffff,
|
||||
sram3 >> 16, sram3 & 0xffff,
|
||||
usb_dmas_readl(udc, ENETDMAS_SRAM4_REG(ch_idx)));
|
||||
usb_dmas_readl(udc, ENETDMAS_SRAM4_REG, ch_idx));
|
||||
seq_printf(s, " desc: %d/%d used", iudma->n_bds_used,
|
||||
iudma->n_bds);
|
||||
|
||||
|
|
|
|||
|
|
@ -585,7 +585,6 @@ static ssize_t ffs_epfile_io(struct file *file,
|
|||
char __user *buf, size_t len, int read)
|
||||
{
|
||||
struct ffs_epfile *epfile = file->private_data;
|
||||
struct usb_gadget *gadget = epfile->ffs->gadget;
|
||||
struct ffs_ep *ep;
|
||||
char *data = NULL;
|
||||
ssize_t ret, data_len;
|
||||
|
|
@ -621,6 +620,12 @@ static ssize_t ffs_epfile_io(struct file *file,
|
|||
|
||||
/* Allocate & copy */
|
||||
if (!halt) {
|
||||
/*
|
||||
* if we _do_ wait above, the epfile->ffs->gadget might be NULL
|
||||
* before the waiting completes, so do not assign to 'gadget' earlier
|
||||
*/
|
||||
struct usb_gadget *gadget = epfile->ffs->gadget;
|
||||
|
||||
/*
|
||||
* Controller may require buffer size to be aligned to
|
||||
* maxpacketsize of an out endpoint.
|
||||
|
|
|
|||
|
|
@ -1157,7 +1157,7 @@ static int __init printer_bind_config(struct usb_configuration *c)
|
|||
|
||||
usb_gadget_set_selfpowered(gadget);
|
||||
|
||||
if (gadget->is_otg) {
|
||||
if (gadget_is_otg(gadget)) {
|
||||
otg_descriptor.bmAttributes |= USB_OTG_HNP;
|
||||
printer_cfg_driver.descriptors = otg_desc;
|
||||
printer_cfg_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
|
||||
|
|
|
|||
|
|
@ -1629,7 +1629,7 @@ static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
|
|||
ep->ep.desc = NULL;
|
||||
ep->halted = 0;
|
||||
INIT_LIST_HEAD(&ep->queue);
|
||||
usb_ep_set_maxpacket_limit(&ep->ep, &ep->ep.maxpacket);
|
||||
usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -685,8 +685,15 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd)
|
|||
struct ehci_hcd *ehci = hcd_to_ehci (hcd);
|
||||
u32 status, masked_status, pcd_status = 0, cmd;
|
||||
int bh;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock (&ehci->lock);
|
||||
/*
|
||||
* For threadirqs option we use spin_lock_irqsave() variant to prevent
|
||||
* deadlock with ehci hrtimer callback, because hrtimer callbacks run
|
||||
* in interrupt context even when threadirqs is specified. We can go
|
||||
* back to spin_lock() variant when hrtimer callbacks become threaded.
|
||||
*/
|
||||
spin_lock_irqsave(&ehci->lock, flags);
|
||||
|
||||
status = ehci_readl(ehci, &ehci->regs->status);
|
||||
|
||||
|
|
@ -704,7 +711,7 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd)
|
|||
|
||||
/* Shared IRQ? */
|
||||
if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
|
||||
spin_unlock(&ehci->lock);
|
||||
spin_unlock_irqrestore(&ehci->lock, flags);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
|
|
@ -815,7 +822,7 @@ dead:
|
|||
|
||||
if (bh)
|
||||
ehci_work (ehci);
|
||||
spin_unlock (&ehci->lock);
|
||||
spin_unlock_irqrestore(&ehci->lock, flags);
|
||||
if (pcd_status)
|
||||
usb_hcd_poll_rh_status(hcd);
|
||||
return IRQ_HANDLED;
|
||||
|
|
|
|||
|
|
@ -238,6 +238,7 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
|
|||
int port;
|
||||
int mask;
|
||||
int changed;
|
||||
bool fs_idle_delay;
|
||||
|
||||
ehci_dbg(ehci, "suspend root hub\n");
|
||||
|
||||
|
|
@ -272,6 +273,7 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
|
|||
ehci->bus_suspended = 0;
|
||||
ehci->owned_ports = 0;
|
||||
changed = 0;
|
||||
fs_idle_delay = false;
|
||||
port = HCS_N_PORTS(ehci->hcs_params);
|
||||
while (port--) {
|
||||
u32 __iomem *reg = &ehci->regs->port_status [port];
|
||||
|
|
@ -300,16 +302,32 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
|
|||
}
|
||||
|
||||
if (t1 != t2) {
|
||||
/*
|
||||
* On some controllers, Wake-On-Disconnect will
|
||||
* generate false wakeup signals until the bus
|
||||
* switches over to full-speed idle. For their
|
||||
* sake, add a delay if we need one.
|
||||
*/
|
||||
if ((t2 & PORT_WKDISC_E) &&
|
||||
ehci_port_speed(ehci, t2) ==
|
||||
USB_PORT_STAT_HIGH_SPEED)
|
||||
fs_idle_delay = true;
|
||||
ehci_writel(ehci, t2, reg);
|
||||
changed = 1;
|
||||
}
|
||||
}
|
||||
spin_unlock_irq(&ehci->lock);
|
||||
|
||||
if ((changed && ehci->has_tdi_phy_lpm) || fs_idle_delay) {
|
||||
/*
|
||||
* Wait for HCD to enter low-power mode or for the bus
|
||||
* to switch to full-speed idle.
|
||||
*/
|
||||
usleep_range(5000, 5500);
|
||||
}
|
||||
|
||||
if (changed && ehci->has_tdi_phy_lpm) {
|
||||
spin_unlock_irq(&ehci->lock);
|
||||
msleep(5); /* 5 ms for HCD to enter low-power mode */
|
||||
spin_lock_irq(&ehci->lock);
|
||||
|
||||
port = HCS_N_PORTS(ehci->hcs_params);
|
||||
while (port--) {
|
||||
u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
|
||||
|
|
@ -322,8 +340,8 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
|
|||
port, (t3 & HOSTPC_PHCD) ?
|
||||
"succeeded" : "failed");
|
||||
}
|
||||
spin_unlock_irq(&ehci->lock);
|
||||
}
|
||||
spin_unlock_irq(&ehci->lock);
|
||||
|
||||
/* Apparently some devices need a >= 1-uframe delay here */
|
||||
if (ehci->bus_suspended)
|
||||
|
|
|
|||
|
|
@ -203,12 +203,12 @@ void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
|
|||
addr, (unsigned int)temp);
|
||||
|
||||
addr = &ir_set->erst_base;
|
||||
temp_64 = readq(addr);
|
||||
temp_64 = xhci_read_64(xhci, addr);
|
||||
xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
|
||||
addr, temp_64);
|
||||
|
||||
addr = &ir_set->erst_dequeue;
|
||||
temp_64 = readq(addr);
|
||||
temp_64 = xhci_read_64(xhci, addr);
|
||||
xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
|
||||
addr, temp_64);
|
||||
}
|
||||
|
|
@ -412,7 +412,7 @@ void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
|
|||
{
|
||||
u64 val;
|
||||
|
||||
val = readq(&xhci->op_regs->cmd_ring);
|
||||
val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
|
||||
xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
|
||||
lower_32_bits(val));
|
||||
xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
|
||||
|
|
|
|||
|
|
@ -1958,7 +1958,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
|
|||
xhci_warn(xhci, "WARN something wrong with SW event ring "
|
||||
"dequeue ptr.\n");
|
||||
/* Update HC event ring dequeue pointer */
|
||||
temp = readq(&xhci->ir_set->erst_dequeue);
|
||||
temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
|
||||
temp &= ERST_PTR_MASK;
|
||||
/* Don't clear the EHB bit (which is RW1C) because
|
||||
* there might be more events to service.
|
||||
|
|
@ -1967,7 +1967,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
|
|||
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
|
||||
"// Write event ring dequeue pointer, "
|
||||
"preserving EHB bit");
|
||||
writeq(((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
|
||||
xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
|
||||
&xhci->ir_set->erst_dequeue);
|
||||
}
|
||||
|
||||
|
|
@ -2269,7 +2269,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
|
|||
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
|
||||
"// Device context base array address = 0x%llx (DMA), %p (virt)",
|
||||
(unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
|
||||
writeq(dma, &xhci->op_regs->dcbaa_ptr);
|
||||
xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
|
||||
|
||||
/*
|
||||
* Initialize the ring segment pool. The ring must be a contiguous
|
||||
|
|
@ -2312,13 +2312,13 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
|
|||
(unsigned long long)xhci->cmd_ring->first_seg->dma);
|
||||
|
||||
/* Set the address in the Command Ring Control register */
|
||||
val_64 = readq(&xhci->op_regs->cmd_ring);
|
||||
val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
|
||||
val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
|
||||
(xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
|
||||
xhci->cmd_ring->cycle_state;
|
||||
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
|
||||
"// Setting command ring address to 0x%x", val);
|
||||
writeq(val_64, &xhci->op_regs->cmd_ring);
|
||||
xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
|
||||
xhci_dbg_cmd_ptrs(xhci);
|
||||
|
||||
xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
|
||||
|
|
@ -2396,10 +2396,10 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
|
|||
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
|
||||
"// Set ERST base address for ir_set 0 = 0x%llx",
|
||||
(unsigned long long)xhci->erst.erst_dma_addr);
|
||||
val_64 = readq(&xhci->ir_set->erst_base);
|
||||
val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
|
||||
val_64 &= ERST_PTR_MASK;
|
||||
val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
|
||||
writeq(val_64, &xhci->ir_set->erst_base);
|
||||
xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
|
||||
|
||||
/* Set the event ring dequeue address */
|
||||
xhci_set_hc_event_deq(xhci);
|
||||
|
|
|
|||
|
|
@ -142,6 +142,11 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
|
|||
"QUIRK: Resetting on resume");
|
||||
xhci->quirks |= XHCI_TRUST_TX_LENGTH;
|
||||
}
|
||||
if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
|
||||
pdev->device == 0x0015 &&
|
||||
pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
|
||||
pdev->subsystem_device == 0xc0cd)
|
||||
xhci->quirks |= XHCI_RESET_ON_RESUME;
|
||||
if (pdev->vendor == PCI_VENDOR_ID_VIA)
|
||||
xhci->quirks |= XHCI_RESET_ON_RESUME;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -307,13 +307,14 @@ static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
|
|||
return 0;
|
||||
}
|
||||
|
||||
temp_64 = readq(&xhci->op_regs->cmd_ring);
|
||||
temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
|
||||
if (!(temp_64 & CMD_RING_RUNNING)) {
|
||||
xhci_dbg(xhci, "Command ring had been stopped\n");
|
||||
return 0;
|
||||
}
|
||||
xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
|
||||
writeq(temp_64 | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
|
||||
xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
|
||||
&xhci->op_regs->cmd_ring);
|
||||
|
||||
/* Section 4.6.1.2 of xHCI 1.0 spec says software should
|
||||
* time the completion od all xHCI commands, including
|
||||
|
|
@ -2864,8 +2865,9 @@ hw_died:
|
|||
/* Clear the event handler busy flag (RW1C);
|
||||
* the event ring should be empty.
|
||||
*/
|
||||
temp_64 = readq(&xhci->ir_set->erst_dequeue);
|
||||
writeq(temp_64 | ERST_EHB, &xhci->ir_set->erst_dequeue);
|
||||
temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
|
||||
xhci_write_64(xhci, temp_64 | ERST_EHB,
|
||||
&xhci->ir_set->erst_dequeue);
|
||||
spin_unlock(&xhci->lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
|
@ -2877,7 +2879,7 @@ hw_died:
|
|||
*/
|
||||
while (xhci_handle_event(xhci) > 0) {}
|
||||
|
||||
temp_64 = readq(&xhci->ir_set->erst_dequeue);
|
||||
temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
|
||||
/* If necessary, update the HW's version of the event ring deq ptr. */
|
||||
if (event_ring_deq != xhci->event_ring->dequeue) {
|
||||
deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
|
||||
|
|
@ -2892,7 +2894,7 @@ hw_died:
|
|||
|
||||
/* Clear the event handler busy flag (RW1C); event ring is empty. */
|
||||
temp_64 |= ERST_EHB;
|
||||
writeq(temp_64, &xhci->ir_set->erst_dequeue);
|
||||
xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
|
||||
|
||||
spin_unlock(&xhci->lock);
|
||||
|
||||
|
|
@ -2965,58 +2967,8 @@ static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
|
|||
}
|
||||
|
||||
while (1) {
|
||||
if (room_on_ring(xhci, ep_ring, num_trbs)) {
|
||||
union xhci_trb *trb = ep_ring->enqueue;
|
||||
unsigned int usable = ep_ring->enq_seg->trbs +
|
||||
TRBS_PER_SEGMENT - 1 - trb;
|
||||
u32 nop_cmd;
|
||||
|
||||
/*
|
||||
* Section 4.11.7.1 TD Fragments states that a link
|
||||
* TRB must only occur at the boundary between
|
||||
* data bursts (eg 512 bytes for 480M).
|
||||
* While it is possible to split a large fragment
|
||||
* we don't know the size yet.
|
||||
* Simplest solution is to fill the trb before the
|
||||
* LINK with nop commands.
|
||||
*/
|
||||
if (num_trbs == 1 || num_trbs <= usable || usable == 0)
|
||||
break;
|
||||
|
||||
if (ep_ring->type != TYPE_BULK)
|
||||
/*
|
||||
* While isoc transfers might have a buffer that
|
||||
* crosses a 64k boundary it is unlikely.
|
||||
* Since we can't add NOPs without generating
|
||||
* gaps in the traffic just hope it never
|
||||
* happens at the end of the ring.
|
||||
* This could be fixed by writing a LINK TRB
|
||||
* instead of the first NOP - however the
|
||||
* TRB_TYPE_LINK_LE32() calls would all need
|
||||
* changing to check the ring length.
|
||||
*/
|
||||
break;
|
||||
|
||||
if (num_trbs >= TRBS_PER_SEGMENT) {
|
||||
xhci_err(xhci, "Too many fragments %d, max %d\n",
|
||||
num_trbs, TRBS_PER_SEGMENT - 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
nop_cmd = cpu_to_le32(TRB_TYPE(TRB_TR_NOOP) |
|
||||
ep_ring->cycle_state);
|
||||
ep_ring->num_trbs_free -= usable;
|
||||
do {
|
||||
trb->generic.field[0] = 0;
|
||||
trb->generic.field[1] = 0;
|
||||
trb->generic.field[2] = 0;
|
||||
trb->generic.field[3] = nop_cmd;
|
||||
trb++;
|
||||
} while (--usable);
|
||||
ep_ring->enqueue = trb;
|
||||
if (room_on_ring(xhci, ep_ring, num_trbs))
|
||||
break;
|
||||
}
|
||||
if (room_on_ring(xhci, ep_ring, num_trbs))
|
||||
break;
|
||||
|
||||
if (ep_ring == xhci->cmd_ring) {
|
||||
xhci_err(xhci, "Do not support expand command ring\n");
|
||||
|
|
|
|||
|
|
@ -611,7 +611,7 @@ int xhci_run(struct usb_hcd *hcd)
|
|||
xhci_dbg(xhci, "Event ring:\n");
|
||||
xhci_debug_ring(xhci, xhci->event_ring);
|
||||
xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
|
||||
temp_64 = readq(&xhci->ir_set->erst_dequeue);
|
||||
temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
|
||||
temp_64 &= ~ERST_PTR_MASK;
|
||||
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
|
||||
"ERST deq = 64'h%0lx", (long unsigned int) temp_64);
|
||||
|
|
@ -756,11 +756,11 @@ static void xhci_save_registers(struct xhci_hcd *xhci)
|
|||
{
|
||||
xhci->s3.command = readl(&xhci->op_regs->command);
|
||||
xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
|
||||
xhci->s3.dcbaa_ptr = readq(&xhci->op_regs->dcbaa_ptr);
|
||||
xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
|
||||
xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
|
||||
xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
|
||||
xhci->s3.erst_base = readq(&xhci->ir_set->erst_base);
|
||||
xhci->s3.erst_dequeue = readq(&xhci->ir_set->erst_dequeue);
|
||||
xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
|
||||
xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
|
||||
xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
|
||||
xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
|
||||
}
|
||||
|
|
@ -769,11 +769,11 @@ static void xhci_restore_registers(struct xhci_hcd *xhci)
|
|||
{
|
||||
writel(xhci->s3.command, &xhci->op_regs->command);
|
||||
writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
|
||||
writeq(xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
|
||||
xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
|
||||
writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
|
||||
writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
|
||||
writeq(xhci->s3.erst_base, &xhci->ir_set->erst_base);
|
||||
writeq(xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
|
||||
xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
|
||||
xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
|
||||
writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
|
||||
writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
|
||||
}
|
||||
|
|
@ -783,7 +783,7 @@ static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
|
|||
u64 val_64;
|
||||
|
||||
/* step 2: initialize command ring buffer */
|
||||
val_64 = readq(&xhci->op_regs->cmd_ring);
|
||||
val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
|
||||
val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
|
||||
(xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
|
||||
xhci->cmd_ring->dequeue) &
|
||||
|
|
@ -792,7 +792,7 @@ static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
|
|||
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
|
||||
"// Setting command ring address to 0x%llx",
|
||||
(long unsigned long) val_64);
|
||||
writeq(val_64, &xhci->op_regs->cmd_ring);
|
||||
xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -3842,7 +3842,7 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
|
|||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
temp_64 = readq(&xhci->op_regs->dcbaa_ptr);
|
||||
temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
|
||||
xhci_dbg_trace(xhci, trace_xhci_dbg_address,
|
||||
"Op regs DCBAA ptr = %#016llx", temp_64);
|
||||
xhci_dbg_trace(xhci, trace_xhci_dbg_address,
|
||||
|
|
@ -4730,11 +4730,8 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
|
|||
struct device *dev = hcd->self.controller;
|
||||
int retval;
|
||||
|
||||
/* Limit the block layer scatter-gather lists to half a segment. */
|
||||
hcd->self.sg_tablesize = TRBS_PER_SEGMENT / 2;
|
||||
|
||||
/* support to build packet from discontinuous buffers */
|
||||
hcd->self.no_sg_constraint = 1;
|
||||
/* Accept arbitrarily long scatter-gather lists */
|
||||
hcd->self.sg_tablesize = ~0;
|
||||
|
||||
/* XHCI controllers don't stop the ep queue on short packets :| */
|
||||
hcd->self.no_stop_on_short = 1;
|
||||
|
|
@ -4760,6 +4757,14 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
|
|||
/* xHCI private pointer was set in xhci_pci_probe for the second
|
||||
* registered roothub.
|
||||
*/
|
||||
xhci = hcd_to_xhci(hcd);
|
||||
/*
|
||||
* Support arbitrarily aligned sg-list entries on hosts without
|
||||
* TD fragment rules (which are currently unsupported).
|
||||
*/
|
||||
if (xhci->hci_version < 0x100)
|
||||
hcd->self.no_sg_constraint = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -4788,6 +4793,9 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
|
|||
if (xhci->hci_version > 0x96)
|
||||
xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
|
||||
|
||||
if (xhci->hci_version < 0x100)
|
||||
hcd->self.no_sg_constraint = 1;
|
||||
|
||||
/* Make sure the HC is halted. */
|
||||
retval = xhci_halt(xhci);
|
||||
if (retval)
|
||||
|
|
|
|||
|
|
@ -28,17 +28,6 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/usb/hcd.h>
|
||||
|
||||
/*
|
||||
* Registers should always be accessed with double word or quad word accesses.
|
||||
*
|
||||
* Some xHCI implementations may support 64-bit address pointers. Registers
|
||||
* with 64-bit address pointers should be written to with dword accesses by
|
||||
* writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
|
||||
* xHCI implementations that do not support 64-bit address pointers will ignore
|
||||
* the high dword, and write order is irrelevant.
|
||||
*/
|
||||
#include <asm-generic/io-64-nonatomic-lo-hi.h>
|
||||
|
||||
/* Code sharing between pci-quirks and xhci hcd */
|
||||
#include "xhci-ext-caps.h"
|
||||
#include "pci-quirks.h"
|
||||
|
|
@ -1279,7 +1268,7 @@ union xhci_trb {
|
|||
* since the command ring is 64-byte aligned.
|
||||
* It must also be greater than 16.
|
||||
*/
|
||||
#define TRBS_PER_SEGMENT 256
|
||||
#define TRBS_PER_SEGMENT 64
|
||||
/* Allow two commands + a link TRB, along with any reserved command TRBs */
|
||||
#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
|
||||
#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
|
||||
|
|
@ -1614,6 +1603,34 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
|
|||
#define xhci_warn_ratelimited(xhci, fmt, args...) \
|
||||
dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
|
||||
|
||||
/*
|
||||
* Registers should always be accessed with double word or quad word accesses.
|
||||
*
|
||||
* Some xHCI implementations may support 64-bit address pointers. Registers
|
||||
* with 64-bit address pointers should be written to with dword accesses by
|
||||
* writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
|
||||
* xHCI implementations that do not support 64-bit address pointers will ignore
|
||||
* the high dword, and write order is irrelevant.
|
||||
*/
|
||||
static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
|
||||
__le64 __iomem *regs)
|
||||
{
|
||||
__u32 __iomem *ptr = (__u32 __iomem *) regs;
|
||||
u64 val_lo = readl(ptr);
|
||||
u64 val_hi = readl(ptr + 1);
|
||||
return val_lo + (val_hi << 32);
|
||||
}
|
||||
static inline void xhci_write_64(struct xhci_hcd *xhci,
|
||||
const u64 val, __le64 __iomem *regs)
|
||||
{
|
||||
__u32 __iomem *ptr = (__u32 __iomem *) regs;
|
||||
u32 val_lo = lower_32_bits(val);
|
||||
u32 val_hi = upper_32_bits(val);
|
||||
|
||||
writel(val_lo, ptr);
|
||||
writel(val_hi, ptr + 1);
|
||||
}
|
||||
|
||||
static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
|
||||
{
|
||||
return xhci->quirks & XHCI_LINK_TRB_QUIRK;
|
||||
|
|
|
|||
|
|
@ -477,8 +477,11 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
|
|||
musb->port1_status |=
|
||||
(USB_PORT_STAT_C_SUSPEND << 16)
|
||||
| MUSB_PORT_STAT_RESUME;
|
||||
musb->rh_timer = jiffies
|
||||
+ msecs_to_jiffies(20);
|
||||
schedule_delayed_work(
|
||||
&musb->finish_resume_work, 20);
|
||||
&musb->finish_resume_work,
|
||||
msecs_to_jiffies(20));
|
||||
|
||||
musb->xceiv->state = OTG_STATE_A_HOST;
|
||||
musb->is_active = 1;
|
||||
|
|
@ -2157,11 +2160,19 @@ static void musb_restore_context(struct musb *musb)
|
|||
void __iomem *musb_base = musb->mregs;
|
||||
void __iomem *ep_target_regs;
|
||||
void __iomem *epio;
|
||||
u8 power;
|
||||
|
||||
musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
|
||||
musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
|
||||
musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
|
||||
musb_writeb(musb_base, MUSB_POWER, musb->context.power);
|
||||
|
||||
/* Don't affect SUSPENDM/RESUME bits in POWER reg */
|
||||
power = musb_readb(musb_base, MUSB_POWER);
|
||||
power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
|
||||
musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
|
||||
power |= musb->context.power;
|
||||
musb_writeb(musb_base, MUSB_POWER, power);
|
||||
|
||||
musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
|
||||
musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
|
||||
musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
|
||||
|
|
|
|||
|
|
@ -1183,6 +1183,9 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
|
|||
csr = MUSB_CSR0_H_STATUSPKT
|
||||
| MUSB_CSR0_TXPKTRDY;
|
||||
|
||||
/* disable ping token in status phase */
|
||||
csr |= MUSB_CSR0_H_DIS_PING;
|
||||
|
||||
/* flag status stage */
|
||||
musb->ep0_stage = MUSB_EP0_STATUS;
|
||||
|
||||
|
|
|
|||
|
|
@ -135,7 +135,8 @@ void musb_port_suspend(struct musb *musb, bool do_suspend)
|
|||
|
||||
/* later, GetPortStatus will stop RESUME signaling */
|
||||
musb->port1_status |= MUSB_PORT_STAT_RESUME;
|
||||
schedule_delayed_work(&musb->finish_resume_work, 20);
|
||||
schedule_delayed_work(&musb->finish_resume_work,
|
||||
msecs_to_jiffies(20));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -158,7 +159,6 @@ void musb_port_reset(struct musb *musb, bool do_reset)
|
|||
*/
|
||||
power = musb_readb(mbase, MUSB_POWER);
|
||||
if (do_reset) {
|
||||
|
||||
/*
|
||||
* If RESUME is set, we must make sure it stays minimum 20 ms.
|
||||
* Then we must clear RESUME and wait a bit to let musb start
|
||||
|
|
@ -167,11 +167,22 @@ void musb_port_reset(struct musb *musb, bool do_reset)
|
|||
* detected".
|
||||
*/
|
||||
if (power & MUSB_POWER_RESUME) {
|
||||
while (time_before(jiffies, musb->rh_timer))
|
||||
msleep(1);
|
||||
long remain = (unsigned long) musb->rh_timer - jiffies;
|
||||
|
||||
if (musb->rh_timer > 0 && remain > 0) {
|
||||
/* take into account the minimum delay after resume */
|
||||
schedule_delayed_work(
|
||||
&musb->deassert_reset_work, remain);
|
||||
return;
|
||||
}
|
||||
|
||||
musb_writeb(mbase, MUSB_POWER,
|
||||
power & ~MUSB_POWER_RESUME);
|
||||
msleep(1);
|
||||
power & ~MUSB_POWER_RESUME);
|
||||
|
||||
/* Give the core 1 ms to clear MUSB_POWER_RESUME */
|
||||
schedule_delayed_work(&musb->deassert_reset_work,
|
||||
msecs_to_jiffies(1));
|
||||
return;
|
||||
}
|
||||
|
||||
power &= 0xf0;
|
||||
|
|
@ -180,7 +191,8 @@ void musb_port_reset(struct musb *musb, bool do_reset)
|
|||
|
||||
musb->port1_status |= USB_PORT_STAT_RESET;
|
||||
musb->port1_status &= ~USB_PORT_STAT_ENABLE;
|
||||
schedule_delayed_work(&musb->deassert_reset_work, 50);
|
||||
schedule_delayed_work(&musb->deassert_reset_work,
|
||||
msecs_to_jiffies(50));
|
||||
} else {
|
||||
dev_dbg(musb->controller, "root port reset stopped\n");
|
||||
musb_writeb(mbase, MUSB_POWER,
|
||||
|
|
|
|||
|
|
@ -659,7 +659,6 @@ static int omap2430_runtime_suspend(struct device *dev)
|
|||
OTG_INTERFSEL);
|
||||
|
||||
omap2430_low_level_exit(musb);
|
||||
phy_power_off(musb->phy);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -674,7 +673,6 @@ static int omap2430_runtime_resume(struct device *dev)
|
|||
omap2430_low_level_init(musb);
|
||||
musb_writel(musb->mregs, OTG_INTERFSEL,
|
||||
musb->context.otg_interfsel);
|
||||
phy_power_on(musb->phy);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -159,32 +159,6 @@ put_3p3:
|
|||
return rc;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
#define USB_PHY_SUSP_DIG_VOL 500000
|
||||
static int msm_hsusb_config_vddcx(int high)
|
||||
{
|
||||
int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
|
||||
int min_vol;
|
||||
int ret;
|
||||
|
||||
if (high)
|
||||
min_vol = USB_PHY_VDD_DIG_VOL_MIN;
|
||||
else
|
||||
min_vol = USB_PHY_SUSP_DIG_VOL;
|
||||
|
||||
ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
|
||||
if (ret) {
|
||||
pr_err("%s: unable to set the voltage for regulator "
|
||||
"HSUSB_VDDCX\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int msm_hsusb_ldo_set_mode(int on)
|
||||
{
|
||||
int ret = 0;
|
||||
|
|
@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
|
|||
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
|
||||
#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
#define USB_PHY_SUSP_DIG_VOL 500000
|
||||
static int msm_hsusb_config_vddcx(int high)
|
||||
{
|
||||
int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
|
||||
int min_vol;
|
||||
int ret;
|
||||
|
||||
if (high)
|
||||
min_vol = USB_PHY_VDD_DIG_VOL_MIN;
|
||||
else
|
||||
min_vol = USB_PHY_SUSP_DIG_VOL;
|
||||
|
||||
ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
|
||||
if (ret) {
|
||||
pr_err("%s: unable to set the voltage for regulator "
|
||||
"HSUSB_VDDCX\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int msm_otg_suspend(struct msm_otg *motg)
|
||||
{
|
||||
struct usb_phy *phy = &motg->phy;
|
||||
|
|
@ -1733,22 +1732,18 @@ static int msm_otg_pm_resume(struct device *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static const struct dev_pm_ops msm_otg_dev_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
|
||||
SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
|
||||
msm_otg_runtime_idle)
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct platform_driver msm_otg_driver = {
|
||||
.remove = msm_otg_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &msm_otg_dev_pm_ops,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ struct usb_phy *usb_get_phy(enum usb_phy_type type)
|
|||
|
||||
phy = __usb_find_phy(&phy_list, type);
|
||||
if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) {
|
||||
pr_err("unable to find transceiver of type %s\n",
|
||||
pr_debug("PHY: unable to find transceiver of type %s\n",
|
||||
usb_phy_type_string(type));
|
||||
goto err0;
|
||||
}
|
||||
|
|
@ -228,7 +228,7 @@ struct usb_phy *usb_get_phy_dev(struct device *dev, u8 index)
|
|||
|
||||
phy = __usb_find_phy_dev(dev, &phy_bind_list, index);
|
||||
if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) {
|
||||
pr_err("unable to find transceiver\n");
|
||||
dev_dbg(dev, "unable to find transceiver\n");
|
||||
goto err0;
|
||||
}
|
||||
|
||||
|
|
@ -424,10 +424,8 @@ int usb_bind_phy(const char *dev_name, u8 index,
|
|||
unsigned long flags;
|
||||
|
||||
phy_bind = kzalloc(sizeof(*phy_bind), GFP_KERNEL);
|
||||
if (!phy_bind) {
|
||||
pr_err("phy_bind(): No memory for phy_bind");
|
||||
if (!phy_bind)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
phy_bind->dev_name = dev_name;
|
||||
phy_bind->phy_dev_name = phy_dev_name;
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ static const struct usb_device_id id_table_combined[] = {
|
|||
{ USB_DEVICE(FTDI_VID, FTDI_CANUSB_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_CANDAPTER_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_NXTCAM_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_EV3CON_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_0_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_1_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_2_PID) },
|
||||
|
|
@ -191,6 +192,8 @@ static const struct usb_device_id id_table_combined[] = {
|
|||
{ USB_DEVICE(INTERBIOMETRICS_VID, INTERBIOMETRICS_IOBOARD_PID) },
|
||||
{ USB_DEVICE(INTERBIOMETRICS_VID, INTERBIOMETRICS_MINI_IOBOARD_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_SPROG_II) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_TAGSYS_LP101_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_TAGSYS_P200X_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_LENZ_LIUSB_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_XF_632_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_XF_634_PID) },
|
||||
|
|
@ -904,6 +907,8 @@ static const struct usb_device_id id_table_combined[] = {
|
|||
/* Crucible Devices */
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_CT_COMET_PID) },
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_Z3X_PID) },
|
||||
/* Cressi Devices */
|
||||
{ USB_DEVICE(FTDI_VID, FTDI_CRESSI_PID) },
|
||||
{ } /* Terminating entry */
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@
|
|||
#define TI_XDS100V2_PID 0xa6d0
|
||||
|
||||
#define FTDI_NXTCAM_PID 0xABB8 /* NXTCam for Mindstorms NXT */
|
||||
#define FTDI_EV3CON_PID 0xABB9 /* Mindstorms EV3 Console Adapter */
|
||||
|
||||
/* US Interface Navigator (http://www.usinterface.com/) */
|
||||
#define FTDI_USINT_CAT_PID 0xb810 /* Navigator CAT and 2nd PTT lines */
|
||||
|
|
@ -363,6 +364,12 @@
|
|||
/* Sprog II (Andrew Crosland's SprogII DCC interface) */
|
||||
#define FTDI_SPROG_II 0xF0C8
|
||||
|
||||
/*
|
||||
* Two of the Tagsys RFID Readers
|
||||
*/
|
||||
#define FTDI_TAGSYS_LP101_PID 0xF0E9 /* Tagsys L-P101 RFID*/
|
||||
#define FTDI_TAGSYS_P200X_PID 0xF0EE /* Tagsys Medio P200x RFID*/
|
||||
|
||||
/* an infrared receiver for user access control with IR tags */
|
||||
#define FTDI_PIEGROUP_PID 0xF208 /* Product Id */
|
||||
|
||||
|
|
@ -1313,3 +1320,9 @@
|
|||
* Manufacturer: Smart GSM Team
|
||||
*/
|
||||
#define FTDI_Z3X_PID 0x0011
|
||||
|
||||
/*
|
||||
* Product: Cressi PC Interface
|
||||
* Manufacturer: Cressi
|
||||
*/
|
||||
#define FTDI_CRESSI_PID 0x87d0
|
||||
|
|
|
|||
|
|
@ -1362,7 +1362,8 @@ static const struct usb_device_id option_ids[] = {
|
|||
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1267, 0xff, 0xff, 0xff) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1268, 0xff, 0xff, 0xff) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1269, 0xff, 0xff, 0xff) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1270, 0xff, 0xff, 0xff) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1270, 0xff, 0xff, 0xff),
|
||||
.driver_info = (kernel_ulong_t)&net_intf5_blacklist },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1271, 0xff, 0xff, 0xff) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1272, 0xff, 0xff, 0xff) },
|
||||
{ USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x1273, 0xff, 0xff, 0xff) },
|
||||
|
|
@ -1525,7 +1526,8 @@ static const struct usb_device_id option_ids[] = {
|
|||
/* Cinterion */
|
||||
{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_EU3_E) },
|
||||
{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_EU3_P) },
|
||||
{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PH8) },
|
||||
{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PH8),
|
||||
.driver_info = (kernel_ulong_t)&net_intf4_blacklist },
|
||||
{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_AHXX) },
|
||||
{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PLXX),
|
||||
.driver_info = (kernel_ulong_t)&net_intf4_blacklist },
|
||||
|
|
|
|||
|
|
@ -139,6 +139,9 @@ static const struct usb_device_id id_table[] = {
|
|||
{USB_DEVICE_INTERFACE_NUMBER(0x1199, 0x901c, 0)}, /* Sierra Wireless EM7700 Device Management */
|
||||
{USB_DEVICE_INTERFACE_NUMBER(0x1199, 0x901c, 2)}, /* Sierra Wireless EM7700 NMEA */
|
||||
{USB_DEVICE_INTERFACE_NUMBER(0x1199, 0x901c, 3)}, /* Sierra Wireless EM7700 Modem */
|
||||
{USB_DEVICE_INTERFACE_NUMBER(0x1199, 0x9051, 0)}, /* Netgear AirCard 340U Device Management */
|
||||
{USB_DEVICE_INTERFACE_NUMBER(0x1199, 0x9051, 2)}, /* Netgear AirCard 340U NMEA */
|
||||
{USB_DEVICE_INTERFACE_NUMBER(0x1199, 0x9051, 3)}, /* Netgear AirCard 340U Modem */
|
||||
|
||||
{ } /* Terminating entry */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -71,7 +71,8 @@ DEVICE(hp4x, HP4X_IDS);
|
|||
|
||||
/* Suunto ANT+ USB Driver */
|
||||
#define SUUNTO_IDS() \
|
||||
{ USB_DEVICE(0x0fcf, 0x1008) }
|
||||
{ USB_DEVICE(0x0fcf, 0x1008) }, \
|
||||
{ USB_DEVICE(0x0fcf, 0x1009) } /* Dynastream ANT USB-m Stick */
|
||||
DEVICE(suunto, SUUNTO_IDS);
|
||||
|
||||
/* Siemens USB/MPI adapter */
|
||||
|
|
|
|||
|
|
@ -18,7 +18,9 @@ config USB_STORAGE
|
|||
|
||||
This option depends on 'SCSI' support being enabled, but you
|
||||
probably also need 'SCSI device support: SCSI disk support'
|
||||
(BLK_DEV_SD) for most USB storage devices.
|
||||
(BLK_DEV_SD) for most USB storage devices. Some devices also
|
||||
will require 'Probe all LUNs on each SCSI device'
|
||||
(SCSI_MULTI_LUN).
|
||||
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called usb-storage.
|
||||
|
|
|
|||
|
|
@ -78,6 +78,8 @@ static const char* host_info(struct Scsi_Host *host)
|
|||
|
||||
static int slave_alloc (struct scsi_device *sdev)
|
||||
{
|
||||
struct us_data *us = host_to_us(sdev->host);
|
||||
|
||||
/*
|
||||
* Set the INQUIRY transfer length to 36. We don't use any of
|
||||
* the extra data and many devices choke if asked for more or
|
||||
|
|
@ -102,6 +104,10 @@ static int slave_alloc (struct scsi_device *sdev)
|
|||
*/
|
||||
blk_queue_update_dma_alignment(sdev->request_queue, (512 - 1));
|
||||
|
||||
/* Tell the SCSI layer if we know there is more than one LUN */
|
||||
if (us->protocol == USB_PR_BULK && us->max_lun > 0)
|
||||
sdev->sdev_bflags |= BLIST_FORCELUN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ UNUSUAL_DEV( 0x04b4, 0x6831, 0x0000, 0x9999,
|
|||
"Cypress ISD-300LP",
|
||||
USB_SC_CYP_ATACB, USB_PR_DEVICE, NULL, 0),
|
||||
|
||||
UNUSUAL_DEV( 0x14cd, 0x6116, 0x0000, 0x0219,
|
||||
UNUSUAL_DEV( 0x14cd, 0x6116, 0x0160, 0x0160,
|
||||
"Super Top",
|
||||
"USB 2.0 SATA BRIDGE",
|
||||
USB_SC_CYP_ATACB, USB_PR_DEVICE, NULL, 0),
|
||||
|
|
|
|||
|
|
@ -1455,6 +1455,13 @@ UNUSUAL_DEV( 0x0f88, 0x042e, 0x0100, 0x0100,
|
|||
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
|
||||
US_FL_FIX_CAPACITY ),
|
||||
|
||||
/* Reported by Moritz Moeller-Herrmann <[email protected]> */
|
||||
UNUSUAL_DEV( 0x0fca, 0x8004, 0x0201, 0x0201,
|
||||
"Research In Motion",
|
||||
"BlackBerry Bold 9000",
|
||||
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
|
||||
US_FL_MAX_SECTORS_64 ),
|
||||
|
||||
/* Reported by Michael Stattmann <[email protected]> */
|
||||
UNUSUAL_DEV( 0x0fce, 0xd008, 0x0000, 0x0000,
|
||||
"Sony Ericsson",
|
||||
|
|
|
|||
Loading…
Reference in a new issue