From bd0b75950bd06471f8f0713844fbf754c226ee10 Mon Sep 17 00:00:00 2001 From: David Collins Date: Mon, 11 Feb 2019 17:06:53 -0800 Subject: [PATCH] clk: qcom: clk-alpha-pll: add support to reconfigure PLLs during prepare Under some circumstances, such as during subsystem restart, the registers for a clock controller may be reset to hardware default values. Add support to reconfigure a Lucid PLL during clk_prepare in the case that the CAL_L_VAL is found to be 0 before performing calibration. Change-Id: Idef3c42dfb32748ec40f89a9dab9f6ab86e293f6 Signed-off-by: David Collins --- drivers/clk/qcom/clk-alpha-pll.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 640a2663a975..3908e101d113 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1593,6 +1593,20 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) if (regval & LUCID_PCAL_DONE) return 0; + if (pll->config) { + /* + * Reconfigure the PLL if CAL_L_VAL is 0 (which implies that all + * clock controller registers have been reset). + */ + regmap_read(pll->clkr.regmap, PLL_CAL_L_VAL(pll), ®val); + if (!regval) { + pr_debug("reconfiguring %s after it was reset\n", + clk_hw_get_name(hw)); + clk_lucid_pll_configure(pll, pll->clkr.regmap, + pll->config); + } + } + p = clk_hw_get_parent(hw); if (!p) return -EINVAL;