From dea29f5b1ab07b98e2732c064c77bb51f7144f95 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Fri, 31 Jan 2020 11:47:23 +0530 Subject: [PATCH 01/98] dt-bindings: iommu: add support for qcom,iommu-geometry Add support for "qcom,iommu-geometry" property to specify iova geometry. Change-Id: I13c935f7265d3033b42559e574211dc5847fc181 --- bindings/iommu/arm,smmu.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index 43a93023c1f8..b5352f862cb3 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -156,6 +156,12 @@ conditions. clients who do not detach, it's not possible to keep regulator vote while smmu is attached. Type is . +- qcom,iommu-geometry: + Allow clients to set the available IOVA space for fastmap + clients. The new space created will be a superset of the IOVA + range which was created through the qcom,iommu-dma-addr-pool + DT property. + - (%s)-supply : Phandle of the regulator that should be powered on during SMMU register access. (%s) is a string from the qcom,regulator-names property. From 828c5e271e38dcbedf5eeeb098444b8d7b4090ac Mon Sep 17 00:00:00 2001 From: George Shen Date: Wed, 8 Jul 2020 16:23:40 -0700 Subject: [PATCH 02/98] ARM: dts: msm: Enable CVP SMMU fault tolerance Avoid system crash when CVP SMMU fault happens. CVP SSR can recover SMMU fault now. Change-Id: I9015f9f31bfca39a3d9b015b9a32436e28291721 --- qcom/lahaina-cvp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/lahaina-cvp.dtsi b/qcom/lahaina-cvp.dtsi index d1f48f3fc866..0edfe77d4e12 100644 --- a/qcom/lahaina-cvp.dtsi +++ b/qcom/lahaina-cvp.dtsi @@ -64,6 +64,7 @@ buffer-types = <0xfff>; dma-coherent-hint-cached; qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + qcom,iommu-faults = "non-fatal"; }; @@ -75,6 +76,7 @@ buffer-types = <0x741>; qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>; qcom,iommu-vmid = <0xB>; + qcom,iommu-faults = "non-fatal"; }; cvp_secure_pixel_cb { @@ -85,6 +87,7 @@ buffer-types = <0x106>; qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; qcom,iommu-vmid = <0xA>; + qcom,iommu-faults = "non-fatal"; }; /* Memory Heaps */ From 0be8cd45a90c0bf9a804be0d0ba3a2c9d0c5567b Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 9 Jun 2020 13:33:17 +0530 Subject: [PATCH 03/98] dt-bindings: mtd: Add Documentation for qpic nand Add documentation for qpic controller dtsi entries. Change-Id: Ib491545f3118ec50df26671981163e422806c047 --- bindings/mtd/msm_qpic_nand.txt | 77 ++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 bindings/mtd/msm_qpic_nand.txt diff --git a/bindings/mtd/msm_qpic_nand.txt b/bindings/mtd/msm_qpic_nand.txt new file mode 100644 index 000000000000..a98e4aef7add --- /dev/null +++ b/bindings/mtd/msm_qpic_nand.txt @@ -0,0 +1,77 @@ +Qualcomm Technologies, Inc. Parallel Interface controller (QPIC) for NAND devices + +Required properties: +- compatible : "qcom,msm-nand". +- reg : should specify QPIC NANDc and BAM physical address range. +- reg-names : should specify relevant names to each reg property defined. +- interrupts : should specify QPIC/BAM interrupt numbers. +- interrupt-names : should specify relevant names to each interrupts property + defined. +- qcom,reg-adjustment-offset : Specify the base adjustment offset value for the + version registers +- qcom,qpic-clk-rpmh: Indicates whether QPIC clock is RPMH controlled clock or + not. + +MTD flash partition layout for NAND devices - + +Each partition is represented as a sub-node of the qcom,mtd-partitions device. +Each node's name represents the name of the corresponding partition. + +This is now completely optional as the partition information is avaialble from +bootloader. + +Optional properties: +- reg : boot_cfg. This is needed only on the targets where both NAND and eMMC + devices are supported. On eMMC based builds, NAND cannot be enabled by + default due to the absence of some of its required resources. +- reg : The partition offset and size +- label : The label / name for this partition. +- read-only: This parameter, if present, indicates that this partition + should only be mounted read-only. +- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for +below optional properties: + - qcom,msm-bus,name + - qcom,msm-bus,num-cases + - qcom,msm-bus,active-only + - qcom,msm-bus,num-paths + - qcom,msm-bus,vectors-KBps + +Examples: + + qcom,nand@f9af0000 { + compatible = "qcom,msm-nand"; + reg = <0xf9af0000 0x1000>, + <0xf9ac4000 0x8000>, + <0x5e02c 0x4>; + reg-names = "nand_phys", + "bam_phys", + "boot_cfg"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = <0 279 0>; + interrupt-names = "bam_irq"; + + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <1>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <91 512 0 0>, + qcom,qpic-clk-rpmh; + }; + + qcom,mtd-partitions { + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "boot"; + reg = <0x0 0x1000>; + read-only; + }; + partition@20000 { + label = "userdata"; + reg = <0x20000 0x1000>; + }; + partition@40000 { + label = "system"; + reg = <0x40000 0x1000>; + }; + }; From f01216a727ea2afe514046ce2d1632bccbcd90da Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Wed, 26 Aug 2020 14:26:27 -0600 Subject: [PATCH 04/98] ARM: dts: msm: Move the GMU kernel IOMMU phandle to the platform device Move the GMU kernel IOMMU handle to the top level GMU platform device to let it work with devlink and remove the currently unneeded gmu_user. Change-Id: Ic0dedbad54de69a3c117461a83b59d2dda534c16 --- qcom/lahaina-gpu.dtsi | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index bfb36ae6e5ea..62318544dbd0 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -253,6 +253,9 @@ regulator-names = "vddcx", "vdd"; + iommus = <&kgsl_smmu 0x5 0x400>; + qcom,iommu-dma = "disabled"; + vddcx-supply = <&gpu_cc_cx_gdsc>; vdd-supply = <&gpu_cc_gx_gdsc>; @@ -268,18 +271,5 @@ mboxes = <&qmp_aop 0>; mbox-names = "aop"; - - gmu_user: gmu_user { - compatible = "qcom,smmu-gmu-user-cb"; - iommus = <&kgsl_smmu 0x4 0x400>; - qcom,iommu-dma = "disabled"; - }; - - gmu_kernel: gmu_kernel { - compatible = "qcom,smmu-gmu-kernel-cb"; - iommus = <&kgsl_smmu 0x5 0x400>; - qcom,iommu-dma = "disabled"; - }; - }; }; From 507e72c3545b62f57681aa42fcfbd3ae014b5906 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Fri, 28 Aug 2020 22:52:52 +0530 Subject: [PATCH 05/98] ARM: dts: msm: Update GPU patch ID for Shima Update GPU patch ID to 0x10 from 0x1 as per latest recommendation. Change-Id: I98cb63d4fac5ef38d8e4baa6af016246c73e9817 --- qcom/shima-gpu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 924fb43d6ad7..0c4cf567c401 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -42,7 +42,7 @@ "gpu_cc_hub_aon", "gpu_cc_hub_cx_int"; - qcom,chipid = <0x06060001>; + qcom,chipid = <0x06060010>; qcom,no-nap; From 861903a42eb02ac22323c8cfd802428d8512ff71 Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Mon, 31 Aug 2020 09:40:21 +0530 Subject: [PATCH 06/98] ARM: dts: msm: Add the offlineable memory sizes for holi Add the DT node for the mem-offline driver for sizes of the offlineable memory. Change-Id: I7423672726220d69e7768494e8b79226099b1aeb --- qcom/holi.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index af27b19b522b..7a91e2ee0289 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -24,6 +24,14 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ From 9eb61c78ed968b0a5a7372e02404efc1fac5af11 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Thu, 30 Jul 2020 15:57:19 +0530 Subject: [PATCH 07/98] ARM: dts: msm: aatc usb changes for holi Included fsa handle for aatc support. Change-Id: I3f0d57878585fc7931b3f3a2a4dffa45f5c9966c --- qcom/holi-mtp-usbc-overlay.dts | 37 ++++++++++++++++ qcom/holi-mtp-usbc.dtsi | 79 ++++++++++++++++++++++++++++++++-- 2 files changed, 113 insertions(+), 3 deletions(-) diff --git a/qcom/holi-mtp-usbc-overlay.dts b/qcom/holi-mtp-usbc-overlay.dts index 4b04d9d69c6e..730400e7c767 100644 --- a/qcom/holi-mtp-usbc-overlay.dts +++ b/qcom/holi-mtp-usbc-overlay.dts @@ -9,3 +9,40 @@ qcom,msm-id = <454 0x10000>, <472 0x10000>; qcom,board-id = <8 1>; }; + +&swr0 { + qcom,is_wcd937x = <0>; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&wcd938x_tx_slave { + status = "ok"; +}; + +&wcd938x_rx_slave { + status = "ok"; +}; + +&wcd938x_codec { + status = "ok"; +}; + +&holi_snd { + asoc-codec = <&stub_codec>, <&bolero>, + <&wcd938x_codec>, <&wsa881x_i2c_e>, + <&wsa881x_i2c_f>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "wcd938x_codec", "wsa-codec0", + "wsa-codec1"; +}; diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index bfb99171157a..d442733e92cd 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -2,6 +2,8 @@ #include #include #include "holi-pmic-overlay.dtsi" +#include "display/holi-sde-display-mtp.dtsi" +#include "holi-thermal-overlay.dtsi" #include &sdhc_1 { @@ -69,10 +71,45 @@ status = "ok"; }; +&qupv3_se0_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L11A>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + &holi_snd { qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>; + fsa4480-i2c-handle = <&fsa4480>; +}; + +&qupv3_se10_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x42>; + io-channels = <&pm7250b_charger PSY_IIO_TYPEC_ACCESSORY_MODE>; + io-channel-names = "typec_mode"; + qcom,use-power-supply = <1>; + }; }; &soc { @@ -102,6 +139,44 @@ }; }; +&pm6150a_amoled { + status = "ok"; +}; + +&qupv3_se8_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 21 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware.img"; + + panel = <&dsi_rm69299_visionox_amoled_video + &dsi_rm69299_visionox_amoled_cmd>; + }; +}; + &pm7250b_charger { status = "ok"; #io-channel-cells = <1>; @@ -196,9 +271,7 @@ qcom,use-cp-iin-sns; }; -&pm6150a_amoled { - status = "ok"; -}; +#include "camera/holi-camera-sensor-mtp.dtsi" &pm7250b_charger { dpdm-supply = <&qusb_phy0>; From e78ee7236b4fdf9c6ebb07a2b333b1ae317f21fe Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 7 Sep 2020 15:55:51 +0530 Subject: [PATCH 08/98] ARM: dts: msm: Remove vdd_parent-supply from GDSC's in SHIMA Remove vdd_parent-supply property from the GDSC's as it is no longer supported. Change-Id: Ic69203bba9a1a06e868e926a2520b332785f55e6 --- qcom/shima.dtsi | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4170db3da48b..1b194396307c 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3772,7 +3772,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3782,7 +3781,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3791,7 +3789,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3800,7 +3797,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3809,7 +3805,6 @@ clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3819,7 +3814,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3829,7 +3823,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3838,7 +3831,6 @@ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3847,7 +3839,6 @@ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_GFX_LEVEL>; - vdd_parent-supply = <&VDD_GFX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3857,7 +3848,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3866,7 +3856,6 @@ clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3876,7 +3865,6 @@ clock-names = "ahb_clk"; qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; @@ -3885,7 +3873,6 @@ clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - vdd_parent-supply = <&VDD_CX_LEVEL>; qcom,retain-regs; status = "ok"; }; From 7284a890cd93e2e94d6cd01307dbdaa3a8e2a170 Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Thu, 3 Sep 2020 11:48:26 +0530 Subject: [PATCH 09/98] ARM: dts: msm: Enable audio over display Enable external display audio for shima BU. Change-Id: I17b440f619a824bd393b8f523cfe183c307108a2 --- qcom/shima-audio-overlay.dtsi | 8 +++++--- qcom/shima-qrd.dtsi | 4 ++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index a3b3958d27a3..75c102046f6d 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -247,7 +247,7 @@ qcom,wcn-bt = <1>; qcom,tdm-max-slots = <8>; qcom,wcd-disabled = <0>; - qcom,ext-disp-audio-rx = <0>; + qcom,ext-disp-audio-rx = <1>; qcom,audio-routing = "AMIC1", "Analog Mic1", "Analog Mic1", "MIC BIAS3", @@ -310,10 +310,12 @@ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; asoc-codec = <&stub_codec>, <&bolero>, <&wcd938x_codec>, <&swr_haptics>, - <&wsa883x_0221>, <&wsa883x_0222>; + <&wsa883x_0221>, <&wsa883x_0222>, + <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "wcd938x_codec", "swr-haptics", - "wsa-codec1", "wsa-codec2"; + "wsa-codec1", "wsa-codec2", + "msm-ext-disp-audio-codec-rx"; qcom,wsa-max-devs = <2>; qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>; qcom,cps_wsa_vbatt_temp_reg_addr = <0x0000429 0x0000422>; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 341a61e82824..5c6c205945c6 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -292,10 +292,10 @@ asoc-codec = <&stub_codec>, <&bolero>, <&wcd938x_codec>, <&swr_haptics>, - <&wsa883x_0222>; + <&wsa883x_0222>, <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "wcd938x_codec", "swr-haptics", - "wsa-codec2"; + "wsa-codec2", "msm-ext-disp-audio-codec-rx"; qcom,wsa-max-devs = <1>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; From 00841dbe6db1fa35cdd6cb8f38e52458346e39ca Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 8 Sep 2020 15:39:49 -0700 Subject: [PATCH 10/98] ARM: dts: msm: Add CX SDPM configuration for lahaina Add CX SDPM configuration to monitor Camera, CPU and other misc clocks for lahaina. Change-Id: I936d4ecc6af78a30abad97e402fe6c1e6c0fcf5d --- qcom/lahaina-thermal.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 561b0db16801..ea3307042725 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -30,6 +30,17 @@ csr-id = <1 3 5>; }; + cx_sdpm@0x00634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "cam_cc_csi0phytiimer", "ufs_phy"; + clocks = <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_gcc GCC_UFS_PHY_AXI_CLK_SRC>; + cam_cc_csi0phytiimer-supply = <&cam_cc_ipe_0_gdsc>; + cpu = <&CPU7>; + csr-id = <5 7 4>; + }; + mx_pe: mx_rdpm_pe@0x00637000 { compatible = "qcom,policy-engine"; #thermal-sensor-cells = <0>; From a100f21bab63c2851136898f596a519f5184536e Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 8 Sep 2020 15:42:11 -0700 Subject: [PATCH 11/98] ARM: dts: msm: Configure Policy engine for CX rail in lahaina Enable policy engine sensor driver for CX rail policy engine hardware for lahaina. policy engine will recommend mitigation for all CX clients based on operating level. Change-Id: I3896c78a6cdd80b0511719d8707b42ac5478eb4c --- qcom/lahaina-thermal.dtsi | 61 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index ea3307042725..58f5763c1df1 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -47,6 +47,13 @@ reg = <0x00637000 0x1000>; interrupts = ; }; + + cx_pe: cx_rdpm_pe@0x00635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00635000 0x1000>; + interrupts = ; + }; }; &cpufreq_hw { @@ -1183,5 +1190,59 @@ }; }; }; + + cx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + thermal-governor = "step_wise"; + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config2: cx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config3: cx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config4: cx-pe-config4 { + temperature = <5>; + hysteresis = <2>; + type = "passive"; + }; + }; + + cooling-maps { + cx_pe_cdev_1 { + trip = <&cx_pe_config1>; + cooling-device = <&cdsp_sw 1 1>; + }; + + cx_pe_cdev_2 { + trip = <&cx_pe_config2>; + cooling-device = <&cdsp_sw 2 2>; + }; + + cx_pe_cdev_3 { + trip = <&cx_pe_config3>; + cooling-device = <&cdsp_sw 3 3>; + }; + + cx_pe_cdev_4 { + trip = <&cx_pe_config4>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; }; From 2ac8cf416b0b81590e88cfba2e12d7684980a236 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 9 Sep 2020 20:21:00 +0530 Subject: [PATCH 12/98] ARM: dts: msm: Add skip-disable-before-sw-enable flag to gx_gdsc Add flag to avoid GDSC disable when the gdsc is enabled by entity external to HLOS and there is no enable call on the GDSC. Change-Id: I8e96ed9c61d8a5cf44dfd50d6d83bff934b2cc77 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 12f216ff1a21..c08a5a86d4c5 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3851,6 +3851,7 @@ parent-supply = <&VDD_GFX_LEVEL>; vdd_parent-supply = <&VDD_GFX_LEVEL>; qcom,retain-regs; + qcom,skip-disable-before-sw-enable; status = "ok"; }; From 44bc9c82c3faa56b41dc323b997b7ef56f5f5992 Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Tue, 8 Sep 2020 10:24:21 +0530 Subject: [PATCH 13/98] ARM: dts: msm: Add QUPv3 DT nodes for shima trusted VM Add QUPv3(Common driver, GSI and I2C) DT nodes for trusted VM on Shima. Assign one GPII to trusted VM by reducing one GPII from shima primary VM set. Assign GPII0 statically to shima touch PVM usecase. Change-Id: Icd02eb71bf1349af73943fdf6c220d3cb0e000c8 --- qcom/shima-qupv3.dtsi | 7 +++--- qcom/shima-vm.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi index 3c5999d267ac..aa158a9189e4 100644 --- a/qcom/shima-qupv3.dtsi +++ b/qcom/shima-qupv3.dtsi @@ -53,7 +53,8 @@ , , ; - qcom,gpii-mask = <0xff>; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x7e>; qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; @@ -174,8 +175,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se10_i2c_active>; pinctrl-1 = <&qupv3_se10_i2c_sleep>; - dmas = <&gpi_dma0 0 2 3 64 0>, - <&gpi_dma0 1 2 3 64 0>; + dmas = <&gpi_dma0 0 2 3 64 2>, + <&gpi_dma0 1 2 3 64 2>; dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 360c435790da..8ca6ddabf91c 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -224,5 +224,56 @@ , ; }; + + /* + * QUPv3 Instances + * Qup0 2: SE 10 + */ + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x9c0000 0x2000>; + }; + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,gpii-mask = <0x80>; + qcom,ev-factor = <2>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* I2C SE */ + qupv3_se10_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + qcom,le-vm; + status = "disabled"; + }; + }; #include "shima-vm-ion.dtsi" From f408c6ee0b25f5555bab56f396b9679ada709dcd Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 11 Sep 2020 18:02:23 +0530 Subject: [PATCH 14/98] dt-bindings: Add snapshot of batterydata devicetree bindings Add snapshot of batterydata bindings as of devicetree-4.19 'commit 6d9f3e267754 ("ARM: dts: msm: Add snd node for orchid")'. Change-Id: Ib5b30add8245b62886556be6185e5d668fbfd9e9 --- bindings/batterydata/batterydata.txt | 321 +++++++++++++++++++++++++++ 1 file changed, 321 insertions(+) create mode 100644 bindings/batterydata/batterydata.txt diff --git a/bindings/batterydata/batterydata.txt b/bindings/batterydata/batterydata.txt new file mode 100644 index 000000000000..29b75cd47b57 --- /dev/null +++ b/bindings/batterydata/batterydata.txt @@ -0,0 +1,321 @@ +Battery Profile Data + +Battery Data is a collection of battery profile data made available to +the QPNP Charger and BMS drivers via device tree. + +qcom,battery-data node required properties: +- qcom,rpull-up-kohm : The vadc pullup resistor's resistance value in kOhms. +- qcom,vref-batt-therm-uv : The vadc voltage used to make readings. + For Qualcomm Technologies, Inc. VADCs, this should be + 1800000uV. + +qcom,battery-data node optional properties: +- qcom,batt-id-range-pct : The area of variation between upper and lower bound + for which a given battery ID resistance is valid. This + value is expressed as a percentage of the specified kohm + resistance provided by qcom,batt-id-kohm. + +qcom,battery-data can also include any number of children nodes. These children +nodes will be treated as battery profile data nodes. + +Profile data node required properties: +- qcom,fcc-mah : Full charge count of the battery in milliamp-hours +- qcom,default-rbatt-mohm : The nominal battery resistance value +- qcom,rbatt-capacitive-mohm : The capacitive resistance of the battery. +- qcom,flat-ocv-threshold-uv : The threshold under which the battery can be + considered to be in the flat portion of the discharge + curve. +- qcom,max-voltage-uv : The maximum rated voltage of the battery +- qcom,v-cutoff-uv : The cutoff voltage of the battery at which the device + should shutdown gracefully. +- qcom,chg-term-ua : The termination charging current of the battery. +- qcom,batt-id-kohm : The battery id resistance of the battery. It can be + used as an array which could support multiple IDs for one battery + module when the ID resistance of some battery modules goes across + several ranges. +- qcom,battery-type : A string indicating the type of battery. +- qcom,fg-profile-data : An array of hexadecimal values used to configure more + complex fuel gauge peripherals which have a large amount + of coefficients used in hardware state machines and thus + influencing the final output of the state of charge read + by software. + +Profile data node optional properties: +- qcom,chg-rslow-comp-c1 : A constant for rslow compensation in the fuel gauge. + This will be provided by the profiling tool for + additional fuel gauge accuracy during charging. +- qcom,chg-rslow-comp-c2 : A constant for rslow compensation in the fuel gauge. + This will be provided by the profiling tool for + additional fuel gauge accuracy during charging. +- qcom,chg-rslow-comp-thr : A constant for rslow compensation in the fuel gauge. + This will be provided by the profiling tool for + additional fuel gauge accuracy during charging. +- qcom,chg-rs-to-rslow: A constant for rslow compensation in the fuel gauge. + This will be provided by the profiling tool for + additional fuel gauge accuracy during charging. +- qcom,fastchg-current-ma: Specifies the maximum fastcharge current. +- qcom,fg-cc-cv-threshold-mv: Voltage threshold in mV for transition from constant + charge (CC) to constant voltage (CV). This value should + be 10 mV less than the float voltage. + This property should only be specified if + "qcom,autoadjust-vfloat" property is specified in the + charger driver to ensure a proper operation. +- qcom,thermal-coefficients: Byte array of thermal coefficients for reading + battery thermistor. This should be exactly 6 bytes + in length. + Example: [01 02 03 04 05 06] +- qcom,therm-coefficients: Array of thermal coefficients that will be used in + battery profile for GEN4 FG. This should be exactly of + size 5. +- qcom,therm-center-offset: Specifies the resistor divide ratio between pull-up + resistor and the thermistor for GEN4 FG. +- qcom,therm-pull-up: Specifies the thermistor pull-up resistor value in + KOhms. +- qcom,rslow-normal-coeffs: Array of Rslow coefficients that will be applied + when the battery temperature is greater than 0 degree + Celsius for GEN4 FG. This should be exactly of size 4. +- qcom,rslow-low-coeffs: Array of Rslow coefficients that will be applied + when the battery temperature is lower than 0 degree + Celsius for GEN4 FG. This should be exactly of size 4. +- qcom,soc-based-step-chg: A bool property to indicate if the battery will + perform SoC (State of Charge) based step charging. + If yes, the low and high thresholds defined in + "qcom,step-chg-ranges" tuples should be assigned as + SoC values in percentage. +- qcom,ocv-based-step-chg: A bool property to indicate if the battery will + perform OCV (Open Circuit Voltage) based step charging. + If yes, the low and high thresholds defined in + "qcom,step-chg-ranges" tuples should be assigned as + OCV values in microvolts. +- qcom,step-chg-ranges: Array of tuples in which a tuple describes a range + data of step charging setting. + A range contains following 3 integer elements: + [0]: the low threshold of battery voltage in uV + or SoC (State of Charge) in percentage when + SoC based step charge is used; + [1]: the high threshold of battery voltage in uV + or SoC in percentage when SoC based step charge + is used; + [2]: the FCC (full charging current) in uA when battery + voltage or SoC falls between the low and high + thresholds. + The threshold values in range should be in ascending + and shouldn't overlap. It support 8 ranges at max. +- qcom,jeita-fcc-ranges: Array of tuples in which a tuple describes a range + data of sw-jeita FCC (full charging current) setting. + A range contains following 3 integer elements: + [0]: the low threshold of battery temperature in deci-degree; + [1]: the high threshold of battery temperature in deci-degree; + [2]: the FCC in uA when battery temperature falls between + the low and high thresholds. + The threshold values in range should be in ascending + and shouldn't overlap. It support 8 ranges at max. +- qcom,jeita-fv-ranges: Array of tuples in which a tuple describes a range + data of sw-jeita FV (float voltage) setting. + A range contains following 3 integer elements: + [0]: the low threshold of battery temperature in deci-degree; + [1]: the high threshold of battery temperature in deci-degree; + [3]: the FV in uV when battery temperature falls between + the low and high thresholds. + The threshold values in range should be in ascending + and shouldn't overlap. It support 8 ranges at max. +- qcom,jeita-soft-thresholds: A tuple entry to specify ADC code for battery's soft JEITA + threshold. . +- qcom,jeita-hard-thresholds: A tuple entry to specify ADC code for battery's hard JEITA + threshold. . +- qcom,jeita-soft-hys-thresholds: A tuple entry to specify ADC code for battery's soft JEITA + threshold with hysteresis adjustment. + . + These "hysteresis" values should be specified if + "qcom,jeita-soft-thresholds" are specified. Without which SW JEITA + compensation won't function properly. +- qcom,jeita-soft-fcc-ua: A tuple entry to specify the values of Fast + charging current (in uA) that needs to be applied during + soft JEITA conditions (cool/warm). + Element 0 - FCC value for soft cool. + Element 1 - FCC value for soft warm. +- qcom,jeita-soft-fv-uv: A tuple entry to specify the values of Float + voltage (in uV) that needs to be applied during soft + JEITA conditions (cool/warm). + Element 0 - FV value for soft cool. + Element 1 - FV value for soft warm. +- qcom,batt-age-level: Battery age level. This is used only when multiple + profile loading is supported. +- qcom,soh-range: A tuple entry to specify the values of SOH range that + the battery profile has to be used for. This needs to + be specified along with "qcom,batt-age-level" for the + proper functionality. + Element 0 - SOH minimum level. + Element 1 - SOH maximum level. +- qcom,step-jeita-hysteresis: A tuple entry to allow configuring the rising + and falling hysteresis for better fine tuning of the + charge current across battery temperature thresholds. + This should be in decidegree and if not specified + default select value is 10 DeciDegC. + +Profile data node required subnodes: +- qcom,fcc-temp-lut : An 1-dimensional lookup table node that encodes + temperature to fcc lookup. The units for this lookup + table should be degrees celsius to milliamp-hours. +- qcom,pc-temp-ocv-lut : A 2-dimensional lookup table node that encodes + temperature and percent charge to open circuit voltage + lookup. The units for this lookup table should be + degrees celsius and percent to millivolts. +- qcom,rbatt-sf-lut : A 2-dimentional lookup table node that encodes + temperature and percent charge to battery internal + resistance lookup. The units for this lookup table + should be degrees celsius and percent to milliohms. + +Profile data node optional subnodes: +- qcom,ibat-acc-luit: A 2-dimentional lookup table that encodes temperature + and battery current to battery ACC (apparent charge + capacity). The units for this lookup table should be + temperature in degrees celsius, ibat in milli-amps + and ACC in milli-ampere-hour. + +Lookup table required properties: +- qcom,lut-col-legend : An array that encodes the legend of the lookup table's + columns. The length of this array will determine the + lookup table's width. +- qcom,lut-data : An array that encodes the lookup table's data. The size of this + array should be equal to the size of qcom,lut-col-legend + multiplied by 1 if it's a 1-dimensional table, or + the size of qcom,lut-row-legend if it's a 2-dimensional + table. The data should be in a flattened row-major + representation. + +Lookup table optional properties: +- qcom,lut-row-legend : An array that encodes the legend of the lookup table's rows. + If this property exists, then it is assumed that the + lookup table is a 2-dimensional table. + +Example: + +In msm8974-mtp.dtsi: + +mtp_batterydata: qcom,battery-data { + qcom,rpull-up-kohm = <100>; + qcom,vref-batt-therm-uv = <1800000>; + + /include/ "batterydata-palladium.dtsi" + /include/ "batterydata-mtp-3000mah.dtsi" +}; + +&pm8941_bms { + qcom,battery-data = <&mtp_batterydata>; +}; + +In batterydata-palladium.dtsi: + +qcom,palladium-batterydata { + qcom,fcc-mah = <1500>; + qcom,default-rbatt-mohm = <236>; + qcom,rbatt-capacitive-mohm = <50>; + qcom,flat-ocv-threshold-uv = <3800000>; + qcom,max-voltage-uv = <4200000>; + qcom,v-cutoff-uv = <3400000>; + qcom,chg-term-ua = <100000>; + qcom,batt-id-kohm = <75>; + qcom,jeita-soft-thresholds = <0x3ecc 0x1bff>; + qcom,jeita-hard-thresholds = <0x4aff 0x15aa>; + qcom,step-chg-ranges = <3600000 4000000 3000000 + 4001000 4200000 2800000 + 4201000 4400000 2000000>; + qcom,jeita-fcc-ranges = <0 100 600000 + 101 200 2000000 + 201 450 3000000 + 451 550 600000>; + qcom,jeita-fv-ranges = <0 100 4200000 + 101 450 4350000 + 451 550 4200000>; + qcom,battery-type = "palladium_1500mah"; + + qcom,fcc-temp-lut { + qcom,lut-col-legend = <(-20) 0 25 40 65>; + qcom,lut-data = <1492 1492 1493 1483 1502>; + }; + + qcom,pc-temp-ocv-lut { + qcom,lut-col-legend = <(-20) 0 25 40 65>; + qcom,lut-row-legend = <100 95 90 85 80 75 70>, + <65 60 55 50 45 40 35>, + <30 25 20 15 10 9 8>, + <7 6 5 4 3 2 1 0>; + qcom,lut-data = <4173 4167 4163 4156 4154>, + <4104 4107 4108 4102 4104>, + <4057 4072 4069 4061 4060>, + <3973 4009 4019 4016 4020>, + <3932 3959 3981 3982 3983>, + <3899 3928 3954 3950 3950>, + <3868 3895 3925 3921 3920>, + <3837 3866 3898 3894 3892>, + <3812 3841 3853 3856 3862>, + <3794 3818 3825 3823 3822>, + <3780 3799 3804 3804 3803>, + <3768 3787 3790 3788 3788>, + <3757 3779 3778 3775 3776>, + <3747 3772 3771 3766 3765>, + <3736 3763 3766 3760 3746>, + <3725 3749 3756 3747 3729>, + <3714 3718 3734 3724 3706>, + <3701 3703 3696 3689 3668>, + <3675 3695 3682 3675 3662>, + <3670 3691 3680 3673 3661>, + <3661 3686 3679 3672 3656>, + <3649 3680 3676 3669 3641>, + <3633 3669 3667 3655 3606>, + <3610 3647 3640 3620 3560>, + <3580 3607 3596 3572 3501>, + <3533 3548 3537 3512 3425>, + <3457 3468 3459 3429 3324>, + <3328 3348 3340 3297 3172>, + <3000 3000 3000 3000 3000>; + }; + + qcom,rbatt-sf-lut { + qcom,lut-col-legend = <(-20) 0 25 40 65>; + qcom,lut-row-legend = <100 95 90 85 80 75 70>, + <65 60 55 50 45 40 35>, + <30 25 20 15 10 9 8>, + <7 6 5 4 3 2 1 0>; + qcom,lut-data = <357 187 100 91 91>, + <400 208 105 94 94>, + <390 204 106 95 96>, + <391 201 108 98 98>, + <391 202 110 98 100>, + <390 200 110 99 102>, + <389 200 110 99 102>, + <393 202 101 93 100>, + <407 205 99 89 94>, + <428 208 100 91 96>, + <455 212 102 92 98>, + <495 220 104 93 101>, + <561 232 107 95 102>, + <634 245 112 98 98>, + <714 258 114 98 98>, + <791 266 114 97 100>, + <871 289 108 95 97>, + <973 340 124 108 105>, + <489 241 109 96 99>, + <511 246 110 96 99>, + <534 252 111 95 98>, + <579 263 112 96 96>, + <636 276 111 95 97>, + <730 294 109 96 99>, + <868 328 112 98 104>, + <1089 374 119 101 115>, + <1559 457 128 105 213>, + <12886 1026 637 422 3269>, + <170899 127211 98968 88907 77102>; + }; + + qcom,ibat-acc-lut { + qcom,lut-col-legend = <(-20) 0 25>; + qcom,lut-row-legend = <0 250 500 1000>; + qcom,lut-data = <1470 1470 1473>, + <1406 1406 1430>, + <1247 1247 1414>, + <764 764 1338>; + }; +}; + From 5733b16453ea05e8c203378a3d9b182f385e92f6 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 20 Aug 2020 16:15:46 +0530 Subject: [PATCH 15/98] ARM: dts: qcom: Optimize jeita-fcc-step thresholds With the current jeita-fcc-step thresholds observing multiple frequent JEITA entry-exit event while charging with higher charge current for longer time, When the JEITA condition is hit, the charge-current is reduced significantly until the battery temperature drops below sw-jeita-hys threshold which causes the overall charge time to increase. Optimize Optimize this by adding some intermediate steps between 10.00A and 1.89A. While at it also change the hysteresis for the same. Change-Id: I8812dfbad10c6cbb0726077106653b9bc27a576d --- qcom/qg-batterydata-atl436186020H_3780mAh.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi b/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi index 389a2743a930..e9a359822f57 100644 --- a/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi +++ b/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi @@ -12,12 +12,16 @@ qcom,ATL436186_020H_3780mAh { qcom,jeita-fcc-ranges = <0 100 1890000 101 200 3780000 - 201 450 10000000 + 201 420 10000000 + 421 434 8000000 + 435 450 7000000 451 550 1890000>; qcom,jeita-fv-ranges = <0 100 4400000 101 200 4400000 - 201 450 4400000 + 201 420 4400000 + 421 434 4400000 + 435 450 4400000 451 550 4050000>; qcom,step-chg-ranges = <3500000 4000000 10000000 @@ -25,6 +29,8 @@ qcom,ATL436186_020H_3780mAh { 4200001 4400000 6000000>; qcom,ocv-based-step-chg; + /* Rise-Hys = 1 DeciDegC, Fall-Hys=10 deciDegC */ + qcom,qcom,step-jeita-hysteresis = <1 10>; /* COOL = 10 degc, WARM = 45 degC */ qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>; /* COLD = 0 degC, HOT = 55 degC*/ From a0fb9e8113ceaab3e5576fb6bf3fd951ea5986fc Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Mon, 14 Sep 2020 13:06:24 +0530 Subject: [PATCH 16/98] ARM: dts: msm: enable mem_offline.bypass_send_msg for holi Enable boot param mem_offline.bypass_send_msg to skip ending AOP message for mem offline/online requests. Change-Id: I170197edc228eccd17a620a2fbb6b3a233171c1e --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index b6200c578fcd..b9739b048b41 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -420,7 +420,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; }; }; From 00100a8674befe4d73ecee084233fa407ddf26cc Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 5 Aug 2020 20:42:04 -0700 Subject: [PATCH 17/98] ARM: dts: qcom: add some more channels for pm8350b and smb139x Add CHG_TEMP, IIN_FB and ICHG_FB channels on PM8350B to read charger temperature, input current and charging current. Add SMB_TEMP, IIN_SMB and ICHG_SMB on both SMB139x charge pumps to read SMB temperature, input current and charging current which happens over reading virtual channels through PBS. Change-Id: Id08453083d7a09b15ac15032ebef3d9c8ac367e8 --- qcom/lahaina-pmic-overlay.dtsi | 55 ++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index 28c0947af072..e08b0bea9cc9 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -1,4 +1,5 @@ #include +#include #include "pmk8350.dtsi" #include "pm8350.dtsi" @@ -330,6 +331,60 @@ qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; + + pm8350b_chg_temp { + reg = ; + label = "pm8350b_chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_iin_fb { + reg = ; + label = "pm8350b_iin_fb"; + qcom,pre-scaling = <32 100>; + }; + + pm8350b_ichg_fb { + reg = ; + label = "pm8350b_ichg_fb"; + qcom,pre-scaling = <1000 305185>; + }; + + smb139x_1_smb_temp { + reg = ; + label = "smb139x_1_smb_temp"; + qcom,pre-scaling = <1 1>; + }; + + smb139x_1_ichg_smb { + reg = ; + label = "smb139x_1_ichg_smb"; + qcom,pre-scaling = <14 100>; + }; + + smb139x_1_iin_smb { + reg = ; + label = "smb139x_1_iin_smb"; + qcom,pre-scaling = <28 100>; + }; + + smb139x_2_smb_temp { + reg = ; + label = "smb139x_2_smb_temp"; + qcom,pre-scaling = <1 1>; + }; + + smb139x_2_ichg_smb { + reg = ; + label = "smb139x_2_ichg_smb"; + qcom,pre-scaling = <14 100>; + }; + + smb139x_2_iin_smb { + reg = ; + label = "smb139x_2_iin_smb"; + qcom,pre-scaling = <28 100>; + }; }; &pm8350_tz { From 20dd5297cafa2de341a269aaaced3661cac5c1e7 Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Tue, 8 Sep 2020 10:16:31 -0700 Subject: [PATCH 18/98] ARM: dts: msm: Add scm dt nodes for Olympic Add scm and scm pas device tree nodes for Olympic target. These are required for pil image authentication. Change-Id: I4fd67c5a6861e83679178cd3fa0b0f221f5142e8 --- qcom/sdxlemur.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index ba69d5c837c6..bd63804405d3 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -103,6 +103,13 @@ }; soc: soc { }; + + firmware: firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + }; }; &soc { @@ -226,6 +233,11 @@ qcom,wakeup-enable; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + }; + qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; @@ -477,6 +489,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + cache-controller@9200000 { compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2"; reg = <0x9200000 0x50000>; From 1cf5e371e7aa0c933c3195f1a5c83df49b8d3977 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Tue, 15 Sep 2020 15:48:57 +0530 Subject: [PATCH 19/98] ARM: dts: msm: Limit UFS spm level to 3 on Shima Hynix UFS2.2 is drawing 40mA current during APPS PC. This issue is seen only if PX10 is turned off and Vccq2 is ON. Since Vccq2 is always-on supply we can't turn it off. So don't turn off PX10, by updating spm_lvl to 3. In sleep state (spm-lvl=3) its drawing only .5mA. Change-Id: I1a0c8e021d7f1ab6c18bf8ddafe71972a37b28e0 --- qcom/shima.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 57f936b3eb1f..dc4cb1849c66 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1698,7 +1698,14 @@ dma-coherent; rpm-level = <3>; - spm-level = <5>; + /* + * Hynix UFS2.2 is drawing 40mA current during APPS PC. + * Issue is seen only if PX10 is turned off and Vccq2 is ON. + * Since Vccq2 is always-on supply we can't turn it off, + * so don't turn off PX10, by updating spm_lvl to 3. + * In sleep state (spm-lvl=3) its drawing only .5mA. + */ + spm-level = <3>; status = "disabled"; From 0b6ab096ec70ea597cd5aaa96374267086611fae Mon Sep 17 00:00:00 2001 From: Imran Ahmad Date: Tue, 15 Sep 2020 18:26:20 +0530 Subject: [PATCH 20/98] ARM: dts: msm: Add compatible string for ADC lite driver Add the compatible string for ADC-lite driver for reading parallel charger current channel. Change-Id: Ie0d3f90d06be4bf28661736058c5d1fb2af1ac8f --- bindings/iio/adc/qcom,spmi-vadc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/iio/adc/qcom,spmi-vadc.txt b/bindings/iio/adc/qcom,spmi-vadc.txt index aca5cecf2c47..0c01def74f7f 100644 --- a/bindings/iio/adc/qcom,spmi-vadc.txt +++ b/bindings/iio/adc/qcom,spmi-vadc.txt @@ -15,7 +15,7 @@ VADC node: Should contain "qcom,spmi-adc5" for PMIC5 ADC driver. Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver. Should contain "qcom,pms405-adc" for PMS405 PMIC - + Should contain "qcom,spmi-adc5-lite" for PMIC5 ADC-lite driver. - reg: Usage: required Value type: From a64234c4e9b0722484593277315d089e125fa74b Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Tue, 15 Sep 2020 16:57:06 +0530 Subject: [PATCH 21/98] ARM: dts: msm: Update L6C supply load to 30mA to ensure NMP mode Power grid shows the peak current for L6C is 22mA. But PMIC driver has set min threshold for NMP mode is 30mA (to make it common across LDOs). Since SDcard is voting with 22mA load, its staying in LPM mode and can lead to OCP. So increase the load to 30mA, for avoid OCP issues. Change-Id: I9fbc1ace0a5876d7c2b87f396f6a0df51b644df7 --- qcom/shima-idp.dtsi | 2 +- qcom/shima-qrd.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 4129d14e14e9..d0a694ca961b 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -77,7 +77,7 @@ vdd-io-supply = <&L6C>; qcom,vdd-io-voltage-level = <1800000 2960000>; - qcom,vdd-io-current-level = <0 22000>; + qcom,vdd-io-current-level = <0 30000>; cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; }; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 4fc8bb51cd2a..64ca396786dd 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -78,7 +78,7 @@ vdd-io-supply = <&L6C>; qcom,vdd-io-voltage-level = <1800000 2960000>; - qcom,vdd-io-current-level = <0 22000>; + qcom,vdd-io-current-level = <0 30000>; cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; }; From d191e42f51c9ba1b4b4be47609d2501eaeb9227a Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Thu, 10 Sep 2020 03:52:00 +0530 Subject: [PATCH 22/98] ARM: dts: msm: Enable smmu for ufs on holi Enable smmu for ufs on holi. Change-Id: Ie656200fdb9d648468c17e226a0dc7413227547d --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 182484754a78..45680fcc176b 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2150,7 +2150,7 @@ "MAX"; iommus = <&apps_smmu 0x60 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>; From 3d920a10afadc90fed260a46a32b7dc205f94c88 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Wed, 16 Sep 2020 09:08:24 +0800 Subject: [PATCH 23/98] ARM: dts: msm: tune USB2 compliance for holi QRD Change tune1 and bias_ctrl2. Change-Id: I1a1fa8ff315e71f7113a0c19e45e43a5a61b9b8e --- qcom/holi-qrd.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index f82bf2910819..0104c5a8e3d7 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -400,6 +400,50 @@ extcon = <&pm7250b_pdphy>, <&eud>; }; +&qusb_phy0 { + qcom,qusb-phy-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x15 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x47 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x30 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + + qcom,qusb-phy-host-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x15 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x47 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x30 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ +}; + &pm7250b_vadc { smb1390_therm@e { qcom,scale-fn-type = ; From be019afebcf3680cae9eea6170cfcb0034669809 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Wed, 16 Sep 2020 10:58:36 +0530 Subject: [PATCH 24/98] ARM: dts: msm: Add initial device tree for Yupik Add initial device tree to support Yupik on RUMI platform. Change-Id: I5d2614ce33aeac276011fb4623be767ac412dde2 --- bindings/arm/msm/msm.txt | 4 + qcom/Makefile | 9 ++ qcom/yupik-rumi-overlay.dts | 11 ++ qcom/yupik-rumi.dts | 11 ++ qcom/yupik-rumi.dtsi | 13 ++ qcom/yupik.dts | 9 ++ qcom/yupik.dtsi | 266 ++++++++++++++++++++++++++++++++++++ 7 files changed, 323 insertions(+) create mode 100644 qcom/yupik-rumi-overlay.dts create mode 100644 qcom/yupik-rumi.dts create mode 100644 qcom/yupik-rumi.dtsi create mode 100644 qcom/yupik.dts create mode 100644 qcom/yupik.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 906f11685d96..93709ab8e29b 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -56,6 +56,9 @@ SoCs: - SHIMA compatible = "qcom,shima" +- YUPIK + compatible = "qcom,yupik" + - LITO compatible = "qcom,lito" @@ -206,6 +209,7 @@ compatible = "qcom,shima-rumi" compatible = "qcom,shima-idp" compatible = "qcom,shima-atp" compatible = "qcom,shima-qrd" +compatible = "qcom,yupik-rumi" compatible = "qcom,lito-rumi" compatible = "qcom,lito-mtp" compatible = "qcom,lito-cdp" diff --git a/qcom/Makefile b/qcom/Makefile index 431e168ae8a3..1a1c6f058bd8 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -122,6 +122,15 @@ dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \ shima-idps-digital-mics.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_YUPIK) += \ + yupik-rumi-overlay.dtbo + +yupik-rumi-overlay.dtbo-base := yupik.dtb +else +dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SM8150) += \ sm8150-cdp-overlay.dtbo \ diff --git a/qcom/yupik-rumi-overlay.dts b/qcom/yupik-rumi-overlay.dts new file mode 100644 index 000000000000..45ef5d896d3f --- /dev/null +++ b/qcom/yupik-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik RUMI"; + compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi"; + qcom,msm-id = <475 0x10000>; + qcom,board-id = <0x1000f 0>; +}; diff --git a/qcom/yupik-rumi.dts b/qcom/yupik-rumi.dts new file mode 100644 index 000000000000..2085858de82d --- /dev/null +++ b/qcom/yupik-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "yupik.dtsi" +#include "yupik-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik RUMI"; + compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi"; + qcom,board-id = <0x1000f 0>; +}; diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi new file mode 100644 index 000000000000..0987448b8be5 --- /dev/null +++ b/qcom/yupik-rumi.dtsi @@ -0,0 +1,13 @@ +&soc { + timer { + clock-frequency = <5000000>; + }; + + timer@17c20000 { + clock-frequency = <5000000>; + }; + + wdog: qcom,wdt@17c10000 { + status = "disabled"; + }; +}; diff --git a/qcom/yupik.dts b/qcom/yupik.dts new file mode 100644 index 000000000000..07edde8dc0a5 --- /dev/null +++ b/qcom/yupik.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "yupik.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik SoC"; + compatible = "qcom,yupik"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi new file mode 100644 index 000000000000..835fff7b0b00 --- /dev/null +++ b/qcom/yupik.dtsi @@ -0,0 +1,266 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Yupik"; + compatible = "qcom,yupik"; + qcom,msm-id = <475 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + aliases { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + }; + + cluster2 { + + core0 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; + + chosen { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; +}; From aa9fb4f16191bc6a7cfddf4628ec594f4ca99ad6 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Wed, 16 Sep 2020 10:58:49 +0530 Subject: [PATCH 25/98] bindings: pinctrl: Add device-tree bindings for Yupik pinctrl driver Add documentation describing the device-tree properties for the Yupik pinctrl driver. Change-Id: If1498332ffa8b0ee2d4dcb6c05de8058bca7b494 --- bindings/pinctrl/qcom,yupik-pinctrl.txt | 191 ++++++++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 bindings/pinctrl/qcom,yupik-pinctrl.txt diff --git a/bindings/pinctrl/qcom,yupik-pinctrl.txt b/bindings/pinctrl/qcom,yupik-pinctrl.txt new file mode 100644 index 000000000000..819fd937ecd8 --- /dev/null +++ b/bindings/pinctrl/qcom,yupik-pinctrl.txt @@ -0,0 +1,191 @@ +Qualcomm Technologies, Inc. YUPIK TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +YUPIK platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,yupik-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio174 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@f000000 { + compatible = "qcom,yupik-pinctrl"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; From 02a65baf22ce87bb16393360d9c7ae5b6892123d Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Mon, 3 Aug 2020 23:39:48 +0530 Subject: [PATCH 26/98] ARM: dts: msm: Add pinctrl node for TLMM on Yupik SoC Add pinctrl node with compatiability of qcom,yupik-pinctrl, to enable Top Level Mode Multiplexer block(TLMM) on Yupik SoC. Change-Id: I715492d21e736e977de9674b20e932743da512cd --- qcom/yupik-pinctrl.dtsi | 11 +++++++++++ qcom/yupik.dtsi | 2 ++ 2 files changed, 13 insertions(+) create mode 100644 qcom/yupik-pinctrl.dtsi diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi new file mode 100644 index 000000000000..f878cb95d247 --- /dev/null +++ b/qcom/yupik-pinctrl.dtsi @@ -0,0 +1,11 @@ +&soc { + tlmm: pinctrl@f000000 { + compatible = "qcom,yupik-pinctrl"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 835fff7b0b00..52e33c6c58ff 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -264,3 +264,5 @@ }; }; }; + +#include "yupik-pinctrl.dtsi" From f5abb0115c45e50c3a8c08e3f5c46094869ac7d0 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Wed, 16 Sep 2020 12:55:08 +0800 Subject: [PATCH 27/98] ARM: dts: msm: enable redriver on shima QRD add redrivdr i2c node and orientation gpio node. Change-Id: I6ade3cc6e7e96cca6d94cadf42cedb1cfadf3f24 --- qcom/shima-pinctrl.dtsi | 14 ++++++++++++++ qcom/shima-qrd.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi index 68fb424daa34..91e3b21c26af 100644 --- a/qcom/shima-pinctrl.dtsi +++ b/qcom/shima-pinctrl.dtsi @@ -3080,6 +3080,20 @@ drive-strength = <2>; }; }; + + usb3phy_portselect_gpio: usb3phy_portselect_gpio { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; }; bt_en_sleep: bt_en_sleep { diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 4fc8bb51cd2a..1572cd0d8edb 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -310,3 +310,41 @@ pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep &tert_mi2s_sd0_sleep>; }; + +&usb_qmp_dp_phy { + pinctrl-names = "portselect"; +}; + +&qupv3_se5_i2c { + status = "ok"; + + redriver: redriver@1c { + compatible = "onnn,redriver"; + reg = <0x1c>; + + pinctrl-names = "enable_gpio"; + pinctrl-0 = <&usb3phy_portselect_gpio>; + orientation_gpio = <&tlmm 81 0>; + + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x6 0x4 0x4 0x6>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x2 0x1 0x1 0x2>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; +}; From 4cb33dc2349a71afca1083962a1e7285f0b4ed05 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Wed, 16 Sep 2020 12:58:15 +0530 Subject: [PATCH 28/98] ARM: dts: msm: Configure WLAN smmu node in atomic context Configure WLAN smmu node in atomic context for holi target. Change-Id: Ia1f6cc75f41d529f6e14f9fb58ea1bfae4db9a42 --- qcom/holi.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 182484754a78..7a08e1cc7921 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2723,12 +2723,14 @@ ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; iommus = <&apps_smmu 0x04A1 0x0>; + qcom,iommu-dma = "atomic"; }; ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; iommus = <&apps_smmu 0x04A2 0x0>; qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,iommu-dma = "atomic"; }; ipa_smmu_11ad: ipa_smmu_11ad { From 9926837efbbdd7fc11fa21ea2defc667cde4c690 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Tue, 8 Sep 2020 20:51:59 +0530 Subject: [PATCH 29/98] ARM: dts: msm: Add stub regulator support for yupik Yupik uses PM74xx, PM8350C and PMR735A. Add stub regulator support for the same to allow the clients to vote on them. Change-Id: Id7c489de270fb949777276878a9b1a4cd88b820f --- qcom/yupik-stub-regulator.dtsi | 471 +++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 1 + 2 files changed, 472 insertions(+) create mode 100644 qcom/yupik-stub-regulator.dtsi diff --git a/qcom/yupik-stub-regulator.dtsi b/qcom/yupik-stub-regulator.dtsi new file mode 100644 index 000000000000..fc699ff09167 --- /dev/null +++ b/qcom/yupik-stub-regulator.dtsi @@ -0,0 +1,471 @@ +#include + +/ { + VDD_GFX_LEVEL: + S7C_LEVEL: + pm8350c_s7_level: regulator-pm8350c-s7-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s7_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S1B: + pm74xx_s1: regulator-pm74xx-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2040000>; + }; + + S2B: + pm74xx_s2: regulator-pm74xx-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_s2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <640000>; + regulator-max-microvolt = <1050000>; + }; + + S7B: + pm74xx_s7: regulator-pm74xx-s7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_s7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + S8B: + pm74xx_s8: regulator-pm74xx-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_s8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1500000>; + }; + + L1B: + pm74xx_l1: regulator-pm74xx-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + }; + + L2B: + pm74xx_l2: regulator-pm74xx-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + VDD_IO_EBI_LEVEL: + L3B_LEVEL: + pm74xx_l3_level: regulator-pm74xx-l3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_LPI_MX_LEVEL: + L4B_LEVEL: + pm74xx_l4_level: regulator-pm74xx-l4-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l4_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_LPI_CX_LEVEL: + L5B_LEVEL: + pm74xx_l5_level: regulator-pm74xx-l5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + L6B: + pm74xx_l6: regulator-pm74xx-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L7B: + pm74xx_l7: regulator-pm74xx-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + L8B: + pm74xx_l8: regulator-pm74xx-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L9B: + pm74xx_l9: regulator-pm74xx-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L10B: + pm74xx_l10: regulator-pm74xx-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + L11B: + pm74xx_l11: regulator-pm74xx-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L12B: + pm74xx_l12: regulator-pm74xx-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + L13B: + pm74xx_l13: regulator-pm74xx-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + }; + + L14B: + pm74xx_l14: regulator-pm74xx-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L15B: + pm74xx_l15: regulator-pm74xx-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + }; + + L16B: + pm74xx_l16: regulator-pm74xx-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1139000>; + regulator-max-microvolt = <1236000>; + }; + + L17B: + pm74xx_l17: regulator-pm74xx-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L18B: + pm74xx_l18: regulator-pm74xx-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L19B: + pm74xx_l19: regulator-pm74xx-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + S1C: + pm8350c_s1: regulator-pm8350c-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2160000>; + regulator-max-microvolt = <2200000>; + }; + + VDD_MODEM_LEVEL: + S5C_LEVEL: + pm8350c_s5_level: regulator-pm8350c-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL: + S2C_LEVEL: + pm8350c_s2_level: regulator-pm8350c-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + S2C_LEVEL_AO: + pm8350c_s2_level_ao: regulator-pm8350c-s2-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s2_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S9C: + pm8350c_s9: regulator-pm8350c-s9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + VDD_MX_LEVEL: + S10C_LEVEL: + pm8350c_s10_level: regulator-pm8350c-s10-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s10_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL_AO: + S10C_LEVEL_AO: + pm8350c_s10_level_ao: regulator-pm8350c-s10-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s10_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + L1C: + pm8350c_l1: regulator-pm8350c-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L2C: + pm8350c_l2: regulator-pm8350c-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L3C: + pm8350c_l3: regulator-pm8350c-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + }; + + L4C: + pm8350c_l4: regulator-pm8350c-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L5C: + pm8350c_l5: regulator-pm8350c-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L6C: + pm8350c_l6: regulator-pm8350c-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + L7C: + pm8350c_l7: regulator-pm8350c-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + }; + + L8C: + pm8350c_l8: regulator-pm8350c-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L9C: + pm8350c_l9: regulator-pm8350c-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L10C: + pm8350c_l10: regulator-pm8350c-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + L11C: + pm8350c_l11: regulator-pm8350c-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + L12C: + pm8350c_l12: regulator-pm8350c-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L13C: + pm8350c_l13: regulator-pm8350c-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L1D: + pm8350b_l1: regulator-pm8350b-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350b_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + BOB: + pm8350c_bob: regulator-pm8350c-bob { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_bob"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + + L2E: + pmr735a_l2: regulator-pmr735a-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L3E: + pmr735a_l3: regulator-pmr735a-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + }; + + L4E: + pmr735a_l4: regulator-pmr735a-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1615000>; + regulator-max-microvolt = <1890000>; + }; + + L5E: + pmr735a_l5: regulator-pmr735a-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <840000>; + }; + + L6E: + pmr735a_l6: regulator-pmr735a-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <880000>; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 52e33c6c58ff..74b1ab864224 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -266,3 +266,4 @@ }; #include "yupik-pinctrl.dtsi" +#include "yupik-stub-regulator.dtsi" From b0650104bdfccbc8347b25210d7c4af2edff3046 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Wed, 16 Sep 2020 16:25:10 +0530 Subject: [PATCH 30/98] ARM: dts: msm: Move the GMU kernel IOMMU phandle to the platform device Move the GMU kernel IOMMU handle to the top level GMU platform device to let it work with devlink and remove the currently unneeded gmu_user. Change-Id: Ib467fff76e459db1d0a5cf9e026e1bb61c5cbb54 --- qcom/shima-gpu.dtsi | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 18e0d559920e..d12f59be20d4 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -420,6 +420,9 @@ regulator-names = "vddcx", "vdd"; + iommus = <&kgsl_smmu 0x5 0x400>; + qcom,iommu-dma = "disabled"; + vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; @@ -436,18 +439,5 @@ mboxes = <&qmp_aop 0>; mbox-names = "aop"; - - gmu_user: gmu_user { - compatible = "qcom,smmu-gmu-user-cb"; - iommus = <&kgsl_smmu 0x4 0x400>; - qcom,iommu-dma = "disabled"; - }; - - gmu_kernel: gmu_kernel { - compatible = "qcom,smmu-gmu-kernel-cb"; - iommus = <&kgsl_smmu 0x5 0x400>; - qcom,iommu-dma = "disabled"; - }; - }; }; From 890305b0a71685415e8efe22fcdbe02570709392 Mon Sep 17 00:00:00 2001 From: Amarnath Vangala Date: Wed, 16 Sep 2020 15:49:57 +0530 Subject: [PATCH 31/98] ARM: dts: msm: add mclk lpi gpio entry to all wsa881x entries Add mclk lpi gpio dependency to all wsa881x ananlog entries, to enable the probing at same time. Change-Id: I38293ec98fddc6217fdfb49e95021df04559c97c --- qcom/holi-audio-overlay.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 9075c50d7352..45e1fa8d6686 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -312,6 +312,7 @@ wsa881x_i2c_44: wsa881x-i2c-codec@44 { compatible = "qcom,wsa881x-i2c-codec"; reg = <0x044>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; }; wsa881x_i2c_f: wsa881x-i2c-codec@f { @@ -333,6 +334,7 @@ status = "disabled"; compatible = "qcom,wsa881x-i2c-codec"; reg = <0x045>; + qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; }; }; From 3df058d70dc94af55de8b945bbd989c176fff6e3 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Thu, 10 Sep 2020 03:52:00 +0530 Subject: [PATCH 32/98] ARM: dts: msm: Enable smmu for eMMC on holi Enable smmu for eMMC on holi. Change-Id: Ia0e5eced287c9eb052f5f1371ba9ea2792348e38 --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 182484754a78..fa3bdbcf7ee1 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2176,7 +2176,7 @@ reg-names = "hc_mem", "cqhci_mem"; iommus = <&apps_smmu 0x20 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; interrupts = , ; From 2e5321a6264f02d73debf7a3f82fd9d0ed7a546f Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Wed, 16 Sep 2020 22:43:11 +0530 Subject: [PATCH 33/98] ARM: dts: msm: Add charger type IIO channel for USB on Holi Add charger type IIO channel for USB so that the glue driver can read the charger type and set the valid current. Change-Id: Id7e73ce8ddb0acc6db00721c8f14362ec3f3990e --- qcom/holi-atp.dtsi | 4 ++++ qcom/holi-cdp.dtsi | 4 ++++ qcom/holi-mtp-usbc.dtsi | 4 ++++ qcom/holi-mtp.dtsi | 4 ++++ qcom/holi-qrd.dtsi | 4 ++++ 5 files changed, 20 insertions(+) diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index 21a7b42a5cd8..e16ecfc75980 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -296,4 +296,8 @@ &usb0 { extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; }; diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index b1379debf603..5aba97afae07 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -286,4 +286,8 @@ &usb0 { extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; }; diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index bfb99171157a..9ca299826880 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -250,4 +250,8 @@ &usb0 { extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; }; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 1bf80cf75004..7002d553d78a 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -305,4 +305,8 @@ &usb0 { extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; }; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index e8ac31401e88..cbe29f653390 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -379,4 +379,8 @@ &usb0 { extcon = <&pm7250b_pdphy>, <&eud>; + + #io-channel-cells = <1>; + io-channels= <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>; + io-channel-names = "chg_type"; }; From edfe17d17cf588bf9b42b9187456578058201cb0 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Thu, 17 Sep 2020 16:49:27 +0800 Subject: [PATCH 34/98] ARM: dts: msm: Extend pmic dump size for holi Extend pmic dump size to 256k for holi. Change-Id: I44bce7bb9c467025c0f63fc9293b55a3250ebe3d --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 182484754a78..a42af56ea35e 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -799,7 +799,7 @@ }; pmic { - qcom,dump-size = <0x10000>; + qcom,dump-size = <0x40000>; qcom,dump-id = <0xe4>; }; From ab950aebd0bf6a735bf0ab133b847ff9b0c28dd1 Mon Sep 17 00:00:00 2001 From: Author Name Date: Wed, 16 Sep 2020 01:01:32 +0530 Subject: [PATCH 35/98] ARM: dts: msm: Reduce the IOVA range for slimbus and QUP usecases This change enables SMMU page table memory savings for qpup and slim_aud. No functional change but helps saving memory table space. Change-Id: I90a40d62f22d46f99b3aa5ab6372c3ec3cff9039 --- qcom/lahaina-qupv3.dtsi | 9 ++++++--- qcom/lahaina.dtsi | 3 ++- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina-qupv3.dtsi b/qcom/lahaina-qupv3.dtsi index 4be9adc4b94e..723b2eaab701 100644 --- a/qcom/lahaina-qupv3.dtsi +++ b/qcom/lahaina-qupv3.dtsi @@ -34,7 +34,8 @@ , ; iommus = <&apps_smmu 0x5a3 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; @@ -424,7 +425,8 @@ , ; iommus = <&apps_smmu 0x43 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; @@ -762,7 +764,8 @@ , ; iommus = <&apps_smmu 0x5e3 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index ce44b9188fda..e36e52935619 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -573,7 +573,8 @@ qcom,apps-ch-pipes = <0x0>; qcom,ea-pc = <0x350>; iommus = <&apps_smmu 0x1826 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; status = "ok"; From 9e042484868b56d3f649cd043588f730c6d20339 Mon Sep 17 00:00:00 2001 From: Niranjan Dumbala Date: Thu, 17 Sep 2020 09:06:33 -0700 Subject: [PATCH 36/98] Revert "ARM: dts: msm: Add GPU SMMU clocks for holi" This reverts commit e125a334037fc4364d9d85e57f25b6e67eb8aaa5. Change-Id: Iae262255b0df2e4664c0ffefd0e79e132999295b --- qcom/holi-gpu.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index 0ccb298d8451..969737edfde3 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -314,13 +314,6 @@ msm_gpu: qcom,kgsl-3d0@5900000 { vddcx-supply = <&gpu_cx_gdsc>; - clocks = <&gcc GCC_BIMC_GPU_AXI_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - - clock-names = "gcc_bimc_gpu_axi", "gpu_cc_ahb", - "gcc_gpu_memnoc_gfx"; - gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; iommus = <&kgsl_smmu 0x0>; From 27a750f1894256c66f8bc3414b0eb63ab9f42843 Mon Sep 17 00:00:00 2001 From: Himateja Reddy Date: Thu, 17 Sep 2020 11:49:22 -0700 Subject: [PATCH 37/98] ARM: dts: msm: Add fastrpc to glink node on lahaina Add fastrpc subnode to glink node on lahaina to specify glink intent request size and number of glink intent requests. Change-Id: I166172ad098d137bf166501115044c0706666309 --- qcom/lahaina.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index ce44b9188fda..b44eb2b8893a 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4245,6 +4245,12 @@ 0x4400 2>; }; + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_slpi>, @@ -4285,6 +4291,12 @@ 0x4400 2>; }; + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + qcom,slpi_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>, @@ -4313,6 +4325,12 @@ 0x4400 2>; }; + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + qcom,msm_cdsprm_rpmsg { compatible = "qcom,msm-cdsprm-rpmsg"; qcom,glink-channels = "cdsprmglink-apps-dsp"; From 60198e71bfc3384b2094d3b4778d1d81e4906329 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Mon, 20 Jul 2020 23:37:09 +0530 Subject: [PATCH 38/98] ARM: dts: msm: Update and enable the gcc and rpmh clk node on sdxlemur Update device tree node for gcc and rpmh controller and enable the peripheral clock driver. Also enable the required GDSC's. Change-Id: If365f815e807a344b54090f9a9391d5889e4a6ba --- qcom/sdxlemur.dtsi | 45 +++++++++++++++++---------------------------- 1 file changed, 17 insertions(+), 28 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index bd63804405d3..a9a6ec23a414 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -352,22 +352,6 @@ }; }; - bi_tcxo: bi_tcxo { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <4>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - - bi_tcxo_ao: bi_tcxo_ao { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <4>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - aopcc: clock-controller@0 { compatible = "qcom,aop-qmp-clk"; mboxes = <&qmp_aop 0>; @@ -375,16 +359,16 @@ #clock-cells = <1>; }; - rpmhcc: clock-controller@1 { - compatible = "qcom,dummycc"; - clock-output-names = "rpmhcc_clocks"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + gcc: clock-controller@0x100000 { + compatible = "qcom,sdxlemur-gcc", "syscon"; + reg = <0x100000 0x1f7400>; + reg-name = "cc_base"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -431,6 +415,11 @@ system_pm { compatible = "qcom,system-pm"; }; + + rpmhcc: clock-controller@1 { + compatible = "qcom,sdxlemur-rpmh-clk"; + #clock-cells = <1>; + }; }; pdc: interrupt-controller@b210000 { @@ -444,13 +433,13 @@ /* GCC GDSCs */ gcc_pcie_gdsc: qcom,gdsc@143004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x143004 0x4>; regulator-name = "gcc_pcie_gdsc"; }; gcc_usb30_gdsc: qcom,gdsc@117004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; reg = <0x117004 0x4>; regulator-name = "gcc_usb30_gdsc"; }; From c6f67c1cefcd17c179d0486bc79d999527a87df6 Mon Sep 17 00:00:00 2001 From: Liam Mark Date: Thu, 17 Sep 2020 09:42:15 -0700 Subject: [PATCH 39/98] dt-bindings: Remove "non-coherent" SMMU dt-binding documentation This feature doesn't work properly and isn't used by any clients so remove it. Change-Id: I8ec7af8ec577831063c54d7e9a1b83b712c31668 --- bindings/iommu/arm,smmu.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index 43a93023c1f8..757b8c46cb92 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -231,8 +231,6 @@ conditions. --- "default": Pagetable coherency defaults to the coherency setting of the IOMMU device. ---- "non-coherent": - Pagetables are not coherent nor cached in the system cache.. --- "coherent" Pagetables are io-coherent. --- "LLC" From a96e9005703b43ce9f5554d6c1360e1ca7878ba0 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 17 Sep 2020 15:34:49 -0700 Subject: [PATCH 40/98] bindings: pm8941-misc: Add support for VBUS detection VBUS can be detected via a dedicated PMIC pin. Enable compatible string that adds support for reporting the VBUS status. Change-Id: I65d5879a3288e2f5e37d8f674e7216a1aebfe52a --- bindings/extcon/qcom,pm8941-misc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/extcon/qcom,pm8941-misc.txt b/bindings/extcon/qcom,pm8941-misc.txt index 35383adb10f1..91a49af6a122 100644 --- a/bindings/extcon/qcom,pm8941-misc.txt +++ b/bindings/extcon/qcom,pm8941-misc.txt @@ -8,7 +8,7 @@ PROPERTIES - compatible: Usage: required Value type: - Definition: Should contain "qcom,pm8941-misc"; + Definition: Should contain "qcom,pm8941-misc" or "qcom,pmd-vbus-det"; - reg: Usage: required From fef86e715b928216cdc8ef57d42d556a4d424496 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 17 Sep 2020 15:35:11 -0700 Subject: [PATCH 41/98] ARM: dts: msm: Add support to detect VBUS for sdxlemur SDXLemur uses the VBUS_DET peripheral on PMX65. Add support for it. Change-Id: I184e6618efc761a29532306d0a177e9d8a716aeb --- qcom/pmx65.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/pmx65.dtsi b/qcom/pmx65.dtsi index 813eed17ef68..ffe18479014c 100644 --- a/qcom/pmx65.dtsi +++ b/qcom/pmx65.dtsi @@ -34,6 +34,13 @@ interrupt-controller; #interrupt-cells = <2>; }; + + vbus_detect: qcom,pmd-vbus-det@1500 { + compatible = "qcom,pmd-vbus-det"; + reg = <0x1500>; + interrupts = <0x1 0x15 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_vbus"; + }; }; }; From a7dc085fe7ad8667e2386cd439731d6d7a950226 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Fri, 18 Sep 2020 09:22:48 +0800 Subject: [PATCH 42/98] ARM: dts: msm: add gpio-cell property to reduce audio log during bootup Add #gpio-cell property to reduce audio log during bootup. Change-Id: I4c7b4372186e28261d1ed0bc5b4d11fbcf6e7923 --- qcom/lahaina-cdp.dtsi | 1 + qcom/lahaina-mtp.dtsi | 1 + qcom/lahaina-qrd-common.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 21ae311b63e2..2244d7e0e8cb 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -209,6 +209,7 @@ &tert_mi2s_sd0_active>; pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep &tert_mi2s_sd0_sleep>; + #gpio-cells = <0>; }; }; diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 277333c2c9bd..84f6106f179a 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -190,6 +190,7 @@ &tert_mi2s_sd0_active>; pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep &tert_mi2s_sd0_sleep>; + #gpio-cells = <0>; }; }; diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index 87a2b5fff5b6..d96f9b8893b6 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -105,6 +105,7 @@ &tert_mi2s_sd0_active>; pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep &tert_mi2s_sd0_sleep>; + #gpio-cells = <0>; }; }; From 3c9e20858f413fcdd19f6c7f0ca25822d8a7aa2f Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Fri, 18 Sep 2020 16:05:35 +0530 Subject: [PATCH 43/98] ARM: dts: msm: Add IPCC node for Yupik Add IPCC node with compatible of qcom,ipcc, to enable the IPCC driver on Yupik. Change-Id: I7f9babd35e45c016315f2b9cb086a37bc2c3bcec --- qcom/yupik.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 52e33c6c58ff..253b860234f5 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1,4 +1,5 @@ #include +#include / { model = "Qualcomm Technologies, Inc. Yupik"; @@ -196,6 +197,15 @@ interrupts = ; }; + ipcc_mproc: qcom,ipcc@408000 { + compatible = "qcom,ipcc"; + reg = <0x408000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , From 4bb814ccb04c8be2dbf95a96fc8d71fcd6f16be7 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Fri, 18 Sep 2020 20:26:32 +0530 Subject: [PATCH 44/98] ARM: dts: msm: Correct SMMU HLOS vote1 clk name for Shima GPU Drop "_clk" postfix from smmu vote clock name to match with the name driver is using. This is need to ensure this clock is voted properly by driver. Change-Id: Ibebe5899d405d27be3668db4934c6704e15b9919 --- qcom/shima-gpu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 18e0d559920e..cb7082e1b0a0 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -37,7 +37,7 @@ "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "apb_pclk", - "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_hlos1_vote_gpu_smmu", "gpu_cc_cx_gmu", "gpu_cc_hub_aon", "gpu_cc_hub_cx_int"; From 3189becc0eb7fcaa4d48243da50c77f26ea51c34 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 18 Sep 2020 11:03:04 -0700 Subject: [PATCH 45/98] dt-bindings: Add CPU hotplug cooling device Add CPU hotplug cooling device, which will hotplug a CPU to achieve thermal cooling. Change-Id: I7bbc46f16c35a4b6c31b14067b5ba9a2279296ab --- bindings/thermal/qti-cpu-hotplug-cdev.txt | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 bindings/thermal/qti-cpu-hotplug-cdev.txt diff --git a/bindings/thermal/qti-cpu-hotplug-cdev.txt b/bindings/thermal/qti-cpu-hotplug-cdev.txt new file mode 100644 index 000000000000..8e85097a657d --- /dev/null +++ b/bindings/thermal/qti-cpu-hotplug-cdev.txt @@ -0,0 +1,50 @@ +QTI CPU hotplug cooling devices. + +The CPU hotplug cooling device will be used for hotpluging a CPU on a thermal +condition. This cooling device driver can register one cooling device per CPU, +which can be used by thermal zone to mitigate. + +Each child node will represent a cooling device and the child node should +point to the CPU, which will be mitigated by that cooling device instance. + +Properties: +- compatible: + Usage: required + Value type: + Definition: should be "qcom,cpu-hotplug" + +Cooling device node: +- qcom,cpu: + Usage: required + Value type: + Definition: phandle to the CPU device that this cooling device will + mitigate. + +-#cooling-cells: + Usage: required + Value type: + Definition: Must be 2. Needed for of_thermal as cooling device + identifier. Please refer to + for more + details. +Example: + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + }; From 242ad91d0eaac6b43aae3bd67a2e2e1b021bf69a Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 18 Sep 2020 11:09:28 -0700 Subject: [PATCH 46/98] ARM: dts: msm: Add CPU hotplug cooling device for lahaina Add CPU hotplug cooling device for lahaina to achieve thermal cooling. Change-Id: I7e935d75d557b22d3e8163b380bb480c469f1ea2 --- qcom/lahaina-thermal.dtsi | 43 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 58f5763c1df1..fc7bcc9c488b 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -100,6 +100,49 @@ }; }; + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; + qcom,limits-dcvs { compatible = "qcom,msm-hw-limits"; isens_vref_0p8-supply = <&pm8350_l5_ao>; From 1a5f05914d0c423c391c36b17aea143cff8aa2ae Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Sun, 20 Sep 2020 21:00:02 +0530 Subject: [PATCH 47/98] ARM: dts: msm: Add tzone-names for Shima GPU Add GPU tzone-names to get the GPU temperature on Shima. Change-Id: I54c6c0f4a10c5924b1a27eaf99f07274a112a424 --- qcom/shima-gpu.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index f1f7030c8b1f..d33fbbcaf1ae 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -52,6 +52,8 @@ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; interconnect-names = "gpu_icc_path"; From 451161e15605fd8ea20e52be8f8441fc105af144 Mon Sep 17 00:00:00 2001 From: Faiyaz Mohammed Date: Mon, 21 Sep 2020 10:40:18 +0530 Subject: [PATCH 48/98] ARM: dts: msm: Enable the split-tables feature on Shima GPU SMMU Enable the split-tables feature on Shima GPU SMMU to allow clients of that SMMU to use the split-table model for their IOVA spaces. Change-Id: I455426b509c15c7956169b199244707e3da98ea1 --- qcom/msm-arm-smmu-shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index e8ee9372a3be..c9c71235d746 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -9,6 +9,7 @@ #iommu-cells = <2>; qcom,skip-init; qcom,use-3-lvl-tables; + qcom,split-tables; #global-interrupts = <2>; #size-cells = <1>; #address-cells = <1>; From 104f3bbdb8306cbd5d29cd2a60f6c05e6a7f0305 Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Mon, 21 Sep 2020 12:56:09 +0800 Subject: [PATCH 49/98] ARM: dts: msm: Change cd-gpio polarity setting for HDK lahaina According to HDK Lahaina HW design, the logic level of cd-gpio is HIGH with card and is LOW without card. Set cd-gpio flag to GPIO_ACTIVE_HIGH for high active card installed interruption. Change-Id: Icb20ea9f0cdcac57512be2fd53cf61181ccf2066 --- qcom/lahaina-hdk.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 07ece652dcf5..d2cb8cb70d73 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -67,3 +67,7 @@ dr_mode = "host"; }; }; + +&sdhc_2 { + cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; +}; From 88cd41b90fdb4da10b80a463dd80beb3ebf9d9f0 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Mon, 21 Sep 2020 15:17:46 +0800 Subject: [PATCH 50/98] ARM: dts: msm: disable right wsa on Lahaina HDK device Disable right wsa on Lahaina HDK device. Change-Id: Ief69d294b5312ec06eb0a93aa0d9ce9e8050c14f --- qcom/lahaina-hdk.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 07ece652dcf5..d7f25716d987 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -1,5 +1,9 @@ #include "lahaina-qrd-common.dtsi" +&wsa883x_0222 { + status = "disabled"; +}; + &lahaina_snd { qcom,model = "lahaina-hdk-snd-card"; @@ -60,6 +64,8 @@ qcom,msm-mbhc-usbc-audio-supported = <0>; qcom,msm-mbhc-hphl-swh = <1>; qcom,msm-mbhc-gnd-swh = <1>; + + qcom,wsa-max-devs = <1>; }; &usb1 { From ef40754df9d7347ef480693516cd552300829b94 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 21 Sep 2020 14:02:50 +0530 Subject: [PATCH 51/98] ARM: dts: msm: update the bus width for LLCC dcvs nodes update the llcc bus width in calculating IB vote for LLCC dcvs nodes in shima target. Change-Id: I26bde264e4fd94ecd7e52fa2675b0dbe8e18d179 --- qcom/shima.dtsi | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 7d937ca17061..f8dfb8968aa7 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2196,13 +2196,13 @@ llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; - BW_OPP_ENTRY( 150, 32); /* 4576 MB/s */ - BW_OPP_ENTRY( 300, 32); /* 9155 MB/s */ - BW_OPP_ENTRY( 466, 32); /* 14220 MB/s */ - BW_OPP_ENTRY( 600, 32); /* 18310 MB/s */ - BW_OPP_ENTRY( 806, 32); /* 24596 MB/s */ - BW_OPP_ENTRY( 933, 32); /* 28472 MB/s */ - BW_OPP_ENTRY( 1066, 32); /* 30516 MB/s */ + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ + BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ + BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ + BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ + BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ + BW_OPP_ENTRY( 1066, 16); /* 15258 MB/s */ }; ddr_bw_opp_table: ddr-bw-opp-table { @@ -2530,9 +2530,9 @@ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,cachemiss-ev = <0x2A>; qcom,core-dev-table = - < 1171200 MHZ_TO_MBPS( 300, 32) >, - < 1516800 MHZ_TO_MBPS( 466, 32) >, - < 1804800 MHZ_TO_MBPS( 600, 32) >; + < 1171200 MHZ_TO_MBPS( 300, 16) >, + < 1516800 MHZ_TO_MBPS( 466, 16) >, + < 1804800 MHZ_TO_MBPS( 600, 16) >; }; cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { @@ -2578,12 +2578,12 @@ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,cachemiss-ev = <0x2A>; qcom,core-dev-table = - < 691000 MHZ_TO_MBPS( 300, 32) >, - < 940800 MHZ_TO_MBPS( 466, 32) >, - < 1209600 MHZ_TO_MBPS( 600, 32) >, - < 1651800 MHZ_TO_MBPS( 806, 32) >, - < 2361600 MHZ_TO_MBPS( 933, 32) >, - < 2707200 MHZ_TO_MBPS( 1066, 32) >; + < 691000 MHZ_TO_MBPS( 300, 16) >, + < 940800 MHZ_TO_MBPS( 466, 16) >, + < 1209600 MHZ_TO_MBPS( 600, 16) >, + < 1651800 MHZ_TO_MBPS( 806, 16) >, + < 2361600 MHZ_TO_MBPS( 933, 16) >, + < 2707200 MHZ_TO_MBPS( 1066, 16) >; }; cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { @@ -2669,8 +2669,8 @@ qcom,target-dev = <&cpu4_cpu_llcc_latfloor>; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,core-dev-table = - < 1900800 MHZ_TO_MBPS( 150, 32) >, - < 2707200 MHZ_TO_MBPS( 600, 32) >; + < 1900800 MHZ_TO_MBPS( 150, 16) >, + < 2707200 MHZ_TO_MBPS( 600, 16) >; }; cpu7_computemon: qcom,cpu7-computemon { From 4ba10f08f462ffbb4898a1e9c46d81b0be674805 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Fri, 18 Sep 2020 10:33:43 +0800 Subject: [PATCH 52/98] dt-bindings: qcom,amoled-ecm: add display-panels property Add display-panels property for the ECM device to get the display blank and unblank notifications from the active panel device and re-enable ECM dynamically. Change-Id: Ia82f60a7f21908b69a7ba19a1884e955f0bad227 --- bindings/hwmon/qcom,amoled-ecm.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/hwmon/qcom,amoled-ecm.yaml b/bindings/hwmon/qcom,amoled-ecm.yaml index 1cc8c2d1f95a..19957159ced4 100644 --- a/bindings/hwmon/qcom,amoled-ecm.yaml +++ b/bindings/hwmon/qcom,amoled-ecm.yaml @@ -53,6 +53,12 @@ properties: - const: ecm-sdam1 $ref: /schemas/types.yaml#/definitions/string-array + display-panels: + minItems: 1 + description: Array of one or more phandles of the display panel(s) + that sends the DRM blank/unblank notifications. + $ref: /schemas/types.yaml#/definitions/phandle-array + required: - compatible - reg From 435acaa1aa07dfc7f6e1561064e8d5bf579d9c9c Mon Sep 17 00:00:00 2001 From: Vishnuvardhan Prodduturi Date: Mon, 21 Sep 2020 16:56:39 +0530 Subject: [PATCH 53/98] ARM: dts: msm: add touch node for shima trustedvm Add focaltech node for trusted vm device tree and enable trusted touch on trusted vm for shima platform. Change-Id: I365460863f8c88eae07ff8807efdc59198087ad3 --- qcom/shima-vm.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 7b4540df1afb..2ef350f4a81f 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -272,7 +272,16 @@ dma-names = "tx", "rx"; qcom,wrapper-core = <&qupv3_0>; qcom,le-vm; - status = "disabled"; + status = "ok"; + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "tvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; }; }; From 9cadd4d7d22332e15ed3912e9e5759921b1d0610 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 16 Sep 2020 14:45:10 +0800 Subject: [PATCH 54/98] ARM: dts: msm: Add panel information to amoled-ecm for Lahaina platforms Add panel information for amoled-ecm device so that the driver can get display off/on notification from the DRM for the active panel and disable/re-enable ECM accordingly. Change-Id: If1cf00adf9cb3ee0a685575475b9dbab9cd71d98 --- qcom/lahaina-cdp.dtsi | 9 +++++++++ qcom/lahaina-mtp.dtsi | 8 ++++++++ qcom/lahaina-qrd-common.dtsi | 5 +++++ qcom/pm8350b.dtsi | 2 +- 4 files changed, 23 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 21ae311b63e2..f7b317f6eddf 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -182,6 +182,15 @@ status = "ok"; }; +&pm8350b_amoled_ecm { + display-panels = <&dsi_sw43404_amoled_cmd + &dsi_sw43404_amoled_video + &dsi_sw43404_amoled_fhd_plus_cmd + &dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video + &dsi_sharp_qhd_plus_dsc_cmd>; +}; + &pm8350c_switch0 { qcom,led-mask = <9>; /* Channels 1 & 4 */ qcom,symmetry-en; diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 277333c2c9bd..74aa8aca5127 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -163,6 +163,14 @@ status = "ok"; }; +&pm8350b_amoled_ecm { + display-panels = <&dsi_sw43404_amoled_cmd + &dsi_sw43404_amoled_video + &dsi_sw43404_amoled_fhd_plus_cmd + &dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video>; +}; + &pm8350c_switch0 { qcom,led-mask = <9>; /* Channels 1 & 4 */ qcom,symmetry-en; diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index 87a2b5fff5b6..ec76f9b97706 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -299,6 +299,11 @@ }; }; +&pm8350b_amoled_ecm { + display-panels = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video>; +}; + &soc { gpio_keys { compatible = "gpio-keys"; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi index c9110d289922..f92738d71ad5 100644 --- a/qcom/pm8350b.dtsi +++ b/qcom/pm8350b.dtsi @@ -208,7 +208,7 @@ }; }; - qcom,amoled-ecm@f900 { + pm8350b_amoled_ecm: qcom,amoled-ecm@f900 { compatible = "qcom,amoled-ecm"; reg = <0xf900>; nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1"; From 97175c72a58424a9d6f45b0ef965c3cb408c42c6 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Mon, 21 Sep 2020 11:25:05 +0530 Subject: [PATCH 55/98] ARM: dts: msm: Add pmesg reserved memory for holi Add pmesg reserved memory to enable the function to collect user-space log in pstore. And the mem-type is set to 2 for better performance. Change-Id: I6243e129288cfcf2f6ac73e6ae816a2c47a40515 --- qcom/holi.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index b381eb1cd692..e4f9ed939795 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -348,6 +348,13 @@ label = "dfps_data_region"; }; + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xd0000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; From 8049bbbca0f74421d06be9fd9b2b3e1c554d8464 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Mon, 14 Sep 2020 12:22:27 -0700 Subject: [PATCH 56/98] ARM: dts: msm: Add second trip threshold for skin sensor in lahaina Add second trip threshold for skin sensor, to be used by thermal HAL in lahaina. Change-Id: I7d68412c8e55d1267a00b219c779138a90a4be5e --- qcom/lahaina-pmic-overlay.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index e08b0bea9cc9..052c892cc915 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -494,6 +494,12 @@ hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; From d92e38bfdf13e55beeccae13f56e13978cbc7a7a Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Wed, 16 Sep 2020 14:38:09 -0700 Subject: [PATCH 57/98] ARM: dts: msm: free up SDPM 4 in lahaina SDPM 4 is right now used for tracking CPU. Free up this SDPM so that it can be used for HVX in lahaina. Change-Id: I3c25f7e57c1bd947c5ef0a461cb0eb9eed4f847c --- qcom/lahaina-thermal.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index fc7bcc9c488b..3ed3d6eaac4b 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -37,8 +37,7 @@ clocks = <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, <&clock_gcc GCC_UFS_PHY_AXI_CLK_SRC>; cam_cc_csi0phytiimer-supply = <&cam_cc_ipe_0_gdsc>; - cpu = <&CPU7>; - csr-id = <5 7 4>; + csr-id = <5 7>; }; mx_pe: mx_rdpm_pe@0x00637000 { From 4185055aed4bac8648204c4470bed236f15e1891 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Mon, 21 Sep 2020 15:00:25 -0700 Subject: [PATCH 58/98] ARM: dts: msm: Remove PM7250B from sdxlemur pmic overlay PM7250B is not present on all sdxlemur platforms; therefore, add it only for the boards on which it is present, in subsequent patches. Change-Id: I945f8b77783afe1fd020189baca79d602b51e4c1 --- qcom/sdxlemur-pmic-overlay.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index 67995251e247..62c32d93d892 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -1,8 +1,2 @@ #include "pmk8350.dtsi" #include "pmx65.dtsi" -#include "pm7250b.dtsi" - -&pm7250b_clkdiv { - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; -}; From 457fa54d37fdc8948299714431be3b999896911c Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Wed, 9 Sep 2020 15:28:10 -0700 Subject: [PATCH 59/98] ARM: dts: msm: Add ADC channels and thermal zones to sdxlemur SDXLemur has five thermal zones that utilize as many ADC channels, all on PMX65. Change-Id: Iabfcbe6edf761c9858a841a6853cc0bddc7e6b80 --- qcom/sdxlemur-pmic-overlay.dtsi | 208 ++++++++++++++++++++++++++++++++ 1 file changed, 208 insertions(+) diff --git a/qcom/sdxlemur-pmic-overlay.dtsi b/qcom/sdxlemur-pmic-overlay.dtsi index 62c32d93d892..67d96971500f 100644 --- a/qcom/sdxlemur-pmic-overlay.dtsi +++ b/qcom/sdxlemur-pmic-overlay.dtsi @@ -1,2 +1,210 @@ +#include + #include "pmk8350.dtsi" #include "pmx65.dtsi" + +&pmk8350_vadc { + /delete-node/ pm8350_ref_gnd; + /delete-node/ pm8350_vref_1p25; + /delete-node/ pm8350_die_temp; + /delete-node/ pm8350_vph_pwr; + + /delete-node/ pm8350b_ref_gnd; + /delete-node/ pm8350b_vref_1p25; + /delete-node/ pm8350b_die_temp; + /delete-node/ pm8350b_vph_pwr; + /delete-node/ pm8350b_vbat_sns; + + /delete-node/ pmr735a_ref_gnd; + /delete-node/ pmr735a_vref_1p25; + /delete-node/ pmr735a_die_temp; + + /delete-node/ pmr735b_ref_gnd; + /delete-node/ pmr735b_vref_1p25; + /delete-node/ pmr735b_die_temp; + + pmx65_pa_therm1 { + reg = ; + label = "pmx65_pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmx65_pa_therm2 { + reg = ; + label = "pmx65_pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmx65_mdm_case_therm { + reg = ; + label = "pmx65_mdm_case_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmx65_ambient_therm { + reg = ; + label = "pmx65_ambient_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmx65_qtm_skin_therm { + reg = ; + label = "pmx65_qtm_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PMX65_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PMX65_ADC7_AMUX_THM2_100K_PU>, + <&pmk8350_vadc PMX65_ADC7_AMUX_THM3_100K_PU>, + <&pmk8350_vadc PMX65_ADC7_AMUX_THM4_100K_PU>, + <&pmk8350_vadc PMX65_ADC7_AMUX_THM6_100K_PU>; + + pmx65_pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmx65_pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmx65_mdm_case_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmx65_ambient_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmx65_qtm_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + modem-lte-sub6-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-lte-sub6-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-skin-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-ambient-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-beamer-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmk8350_adc_tm PMX65_ADC7_AMUX_THM6_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; From 11475c9f323e79dc16b4c077c516da225e22062f Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 12 Aug 2020 11:54:47 +0530 Subject: [PATCH 60/98] ARM: dts: msm: Add dummy clock nodes for clock controllers for YUPIK Dummy clock nodes are required for clocks client to request, so add support for the same. Also add the dummy GDSCs required by clients. Change-Id: I2e36c960b4d2e94a492a74f17e5423f73d5adf74 --- qcom/shima-gdsc.dtsi | 14 +++ qcom/yupik.dtsi | 227 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 241 insertions(+) diff --git a/qcom/shima-gdsc.dtsi b/qcom/shima-gdsc.dtsi index 4b08898def04..d6d058295306 100644 --- a/qcom/shima-gdsc.dtsi +++ b/qcom/shima-gdsc.dtsi @@ -32,6 +32,13 @@ status = "disabled"; }; + gcc_usb30_sec_gdsc: qcom,gdsc@19e004 { + compatible = "qcom,gdsc"; + reg = <0x19e004 0x4>; + regulator-name = "gcc_usb30_sec_gdsc"; + status = "disabled"; + }; + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c { compatible = "qcom,gdsc"; reg = <0x17d05c 0x4>; @@ -220,4 +227,11 @@ regulator-name = "video_cc_mvs1c_gdsc"; status = "disabled"; }; + + video_cc_mvsc_gdsc: qcom,gdsc@aaf2004 { + compatible = "qcom,gdsc"; + reg = <0xaaf2004 0x4>; + regulator-name = "video_cc_mvsc_gdsc"; + status = "disabled"; + }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 74b1ab864224..103ef0178a48 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1,3 +1,10 @@ +#include +#include +#include +#include +#include +#include +#include #include / { @@ -263,7 +270,227 @@ status = "disabled"; }; }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie-0-pipe-clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_1_pipe_clk: pcie-1-pipe-clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + aopcc: qcom,aopcc { + compatible = "qcom,dummycc"; + clock-output-names = "aopcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rpmhcc: qcom,rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,dummycc"; + clock-output-names = "camcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,dummycc"; + clock-output-names = "videocc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +#include "shima-gdsc.dtsi" #include "yupik-pinctrl.dtsi" #include "yupik-stub-regulator.dtsi" + +&gcc_pcie_0_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_pcie_1_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_usb30_sec_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_titan_top_gdsc { + compatible = "regulator-fixed"; + reg = <0xad0c194 0x4>; + status = "ok"; +}; + +&cam_cc_bps_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&cam_cc_ife_0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_ife_1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_ife_2_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_ipe_0_gdsc { + compatible = "regulator-fixed"; + qcom,support-hw-trigger; + status = "ok"; +}; + +&disp_cc_mdss_core_gdsc { + compatible = "regulator-fixed"; + reg = <0xaf01004 0x4>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gpu_gx_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&video_cc_mvs0_gdsc { + compatible = "regulator-fixed"; + reg = <0xaaf3004 0x4>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&video_cc_mvsc_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; From 0837856feec13b57953fcdd1c3bc10d692f839f3 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 21 Sep 2020 12:25:14 +0530 Subject: [PATCH 61/98] ARM: dts: msm: Update QC2 max ICL for PM7250B Set adapter current to 2A for QC2 to align with the 18W rating. Change-Id: I598722d1bb7e14882cffba3fe75580cf326108b8 --- qcom/pm7250b.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 12a626a950a8..d6febd590a60 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -29,6 +29,7 @@ qcom,thermal-mitigation = <5400000 4500000 4000000 3500000 3000000 2500000 2000000 1500000 1000000 500000>; + qcom,hvdcp2-max-icl-ua = <2000000>; qcom,chgr@1000 { reg = <0x1000>; From 436dcfe2614314fa9c6e8d14bb30c9196b2cf7f0 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Tue, 22 Sep 2020 12:28:52 +0530 Subject: [PATCH 62/98] ARM: dts: msm: Add entry for non secure display heap memory Add entry to use non secure display heap memory for TUI usecase for shima target. Allocated buffers from this heap will be exported to the secondary VM to use it for composition during TUI session. Change-Id: I86387eb36a5babce9a3d53a2ca15ab4deff40117 --- qcom/shima-ion.dtsi | 5 +++++ qcom/shima.dtsi | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/qcom/shima-ion.dtsi b/qcom/shima-ion.dtsi index fc45b51bedde..2b67df9f2277 100644 --- a/qcom/shima-ion.dtsi +++ b/qcom/shima-ion.dtsi @@ -53,5 +53,10 @@ memory-region = <&audio_cma_mem>; qcom,ion-heap-type = "DMA"; }; + qcom,ion-heap@3 { /* NON SECURE DISPLAY HEAP */ + reg = ; + memory-region = <&non_secure_display_memory>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 798ef30db12d..c82806ce3634 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -469,6 +469,14 @@ reg = <0x0 0xe3300000 0x0 0x0100000>; label = "dfps_data_memory"; }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x6400000>; + }; }; chosen { From 4fe8ee1b6a1e411925f23858c64e1c1c96080107 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Tue, 22 Sep 2020 15:49:07 +0530 Subject: [PATCH 63/98] ARM: dts: msm: define new sound card for holi wcd938x with aatc variant Add new sound card to support new mixer path xml for wcd938x with AATC variant of holi. Change-Id: I1caf0fbc9c3471ea4a278f43fda618a7a6df4373 --- qcom/holi-mtp-usbc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index cd6ef96fb833..31d159ac82f7 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -95,6 +95,7 @@ }; &holi_snd { + qcom,model = "holi-mtp-usbc-snd-card"; qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>; From 9993005af1d1ebd8f3f8f7e0820b16d195f2d6f9 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Mon, 21 Sep 2020 14:06:54 +0530 Subject: [PATCH 64/98] ARM: dts: qcom: Disable smb1396 slave node for holi Disable smb1396 slave node on holi. Change-Id: Iae114ce844c10a7904a87bd70b4653e43621ea86 --- qcom/holi-mtp-usbc.dtsi | 24 ++++-------------------- qcom/holi-mtp.dtsi | 24 ++++-------------------- qcom/holi-qrd.dtsi | 24 ++++-------------------- 3 files changed, 12 insertions(+), 60 deletions(-) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index ce89821b2afb..34b0469f05bc 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -135,8 +135,7 @@ <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, - <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>, - <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>; + <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -167,8 +166,7 @@ "cp_switcher_en", "cp_enable", "cp_ilim", - "cp_die_temp", - "current_capability"; + "cp_die_temp"; qcom,battery-data = <&mtp_batterydata>; qcom,sec-charger-config = <1>; qcom,auto-recharge-soc = <98>; @@ -266,20 +264,14 @@ }; &smb1396_div2_cp_master { - io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>, - <&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>, - <&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>, - <&pm7250b_vadc ADC5_AMUX_THM2>, + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; - io-channel-names = "current_capability", - "cp_enable", - "cp_input_current_max", - "die_temp", + io-channel-names = "die_temp", "real_type", "adapter_cc_mode", "pd_current_max", @@ -291,14 +283,6 @@ status = "ok"; }; -&smb1396_slave { - status = "ok"; -}; - -&smb1396_div2_cp_slave { - status = "ok"; -}; - &pm7250b_pdphy { vdd-pdphy-supply = <&L3A>; vbus-supply = <&smb5_vbus>; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index e88f4165c040..6ca3ac15d197 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -192,8 +192,7 @@ <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, - <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>, - <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>; + <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -224,8 +223,7 @@ "cp_switcher_en", "cp_enable", "cp_ilim", - "cp_die_temp", - "current_capability"; + "cp_die_temp"; qcom,battery-data = <&mtp_batterydata>; qcom,sec-charger-config = <1>; qcom,auto-recharge-soc = <98>; @@ -307,20 +305,14 @@ }; &smb1396_div2_cp_master { - io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>, - <&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>, - <&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>, - <&pm7250b_vadc ADC5_AMUX_THM2>, + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; - io-channel-names = "current_capability", - "cp_enable", - "cp_input_current_max", - "die_temp", + io-channel-names = "die_temp", "real_type", "adapter_cc_mode", "pd_current_max", @@ -332,14 +324,6 @@ status = "ok"; }; -&smb1396_slave { - status = "ok"; -}; - -&smb1396_div2_cp_slave { - status = "ok"; -}; - #include "camera/holi-camera-sensor-mtp.dtsi" &pm7250b_charger { diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 0104c5a8e3d7..006fcc15a2cc 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -267,8 +267,7 @@ <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, - <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>, - <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>; + <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -299,8 +298,7 @@ "cp_switcher_en", "cp_enable", "cp_ilim", - "cp_die_temp", - "current_capability"; + "cp_die_temp"; qcom,battery-data = <&qrd_batterydata>; qcom,sec-charger-config = <1>; qcom,auto-recharge-soc = <98>; @@ -480,20 +478,14 @@ }; &smb1396_div2_cp_master { - io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>, - <&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>, - <&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>, - <&pm7250b_vadc ADC5_AMUX_THM2>, + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>, <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; - io-channel-names = "current_capability", - "cp_enable", - "cp_input_current_max", - "die_temp", + io-channel-names = "die_temp", "real_type", "adapter_cc_mode", "pd_current_max", @@ -504,11 +496,3 @@ qcom,parallel-output-mode = <2>; /* VBAT */ status = "ok"; }; - -&smb1396_slave { - status = "ok"; -}; - -&smb1396_div2_cp_slave { - status = "ok"; -}; From 62fb4efce30af9250c21bb4f78f97dcaed6ce2e9 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Mon, 21 Sep 2020 14:31:22 +0530 Subject: [PATCH 65/98] ARM: dts: qcom: Add SMB1355 charger device Add SMB1355 parallel charger with all it's required configuration. Change-Id: I943bfa7d69d22d65901300edc989442809d179df --- qcom/smb1355.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 qcom/smb1355.dtsi diff --git a/qcom/smb1355.dtsi b/qcom/smb1355.dtsi new file mode 100644 index 000000000000..0638aae703d0 --- /dev/null +++ b/qcom/smb1355.dtsi @@ -0,0 +1,39 @@ +#include + +smb1355: qcom,smb1355@c { + compatible = "qcom,i2c-pmic"; + reg = <0xc>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1355"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10 0x12 0x13 0x16>; + status = "disabled"; + + smb1355_charger: qcom,smb1355-charger@1000 { + compatible = "qcom,smb1355"; + reg = <0x1000 0x700>; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&smb1355>; + status = "disabled"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x16 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-bark", + "temperature-change"; + }; + }; +}; From 09a68ad8b2f1914e4ac03ac15de00bfc59bb222e Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Fri, 11 Sep 2020 13:05:35 +0530 Subject: [PATCH 66/98] ARM: dts: msm: Enable 747MHz GPU Fmax for Shima Enable 747MHz GPU Fmax as per SKU definitions. Change-Id: I2f38e8399ddda1aa30d5e1ef5fc56ffffc8d5b2b --- qcom/shima-gpu.dtsi | 68 ++++++++++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 20 deletions(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index d33fbbcaf1ae..54bd3a552e1c 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -143,10 +143,24 @@ #size-cells = <0>; qcom,speed-bin = <0>; - qcom,initial-pwrlevel = <4>; + qcom,initial-pwrlevel = <5>; qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <747000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <676000000>; qcom,level = ; @@ -154,13 +168,13 @@ qcom,bus-min-ddr7 = <10>; qcom,bus-max-ddr7 = <11>; - qcom,bus-freq-ddr8 = <11>; + qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <608000000>; qcom,level = ; @@ -173,8 +187,8 @@ qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <540000000>; qcom,level = ; @@ -187,8 +201,8 @@ qcom,bus-max-ddr8 = <10>; }; - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -201,8 +215,8 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <285000000>; qcom,level = ; @@ -307,10 +321,24 @@ #size-cells = <0>; qcom,speed-bin = <158>; - qcom,initial-pwrlevel = <4>; + qcom,initial-pwrlevel = <5>; qcom,gpu-pwrlevel@0 { reg = <0>; + qcom,gpu-freq = <747000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <11>; + + qcom,bus-freq-ddr8 = <11>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <676000000>; qcom,level = ; @@ -318,13 +346,13 @@ qcom,bus-min-ddr7 = <10>; qcom,bus-max-ddr7 = <11>; - qcom,bus-freq-ddr8 = <11>; + qcom,bus-freq-ddr8 = <10>; qcom,bus-min-ddr8 = <9>; qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@1 { - reg = <1>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <608000000>; qcom,level = ; @@ -337,8 +365,8 @@ qcom,bus-max-ddr8 = <11>; }; - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <540000000>; qcom,level = ; @@ -351,8 +379,8 @@ qcom,bus-max-ddr8 = <10>; }; - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <443000000>; qcom,level = ; @@ -365,8 +393,8 @@ qcom,bus-max-ddr8 = <9>; }; - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <285000000>; qcom,level = ; From ecb995c591a5bf79d1d29b2e7ac40665f675fec8 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 22 Sep 2020 23:26:50 +0800 Subject: [PATCH 67/98] ARM: dts: msm: Extend pmic dump size for holi Extend pmic dump size to 2MB for holi. Change-Id: I46b8ac544d4575202a4c0ee6e1828a85c1324fb3 --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e4f9ed939795..165d453efd75 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -814,7 +814,7 @@ }; pmic { - qcom,dump-size = <0x40000>; + qcom,dump-size = <0x200000>; qcom,dump-id = <0xe4>; }; From 24232aa76a9648f76782306e20e8165c99f5d860 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 17 Sep 2020 17:59:13 -0700 Subject: [PATCH 68/98] ARM: dts: msm: Add PCIe0 PHY settings v1.01 for sdxlemur Add initial PCIe0 PHY setting version 1.01 based on hardware recommendation for sdxlemur. Change-Id: I977b744f7affb74dada2f7be1857caace628b06e --- qcom/sdxlemur-pcie.dtsi | 144 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 753019979959..11ef2356d6b2 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -96,10 +96,152 @@ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; - qcom,pcie-phy-ver = <0>; + qcom,pcie-phy-ver = <1101>; qcom,phy-status-offset = <0x1214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x1240>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x1010 0x01 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xde 0x0 + 0x1028 0x07 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x14 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x0a 0x0 + 0x10b0 0x1a 0x0 + 0x10b4 0x14 0x0 + 0x10b8 0x34 0x0 + 0x10bc 0x82 0x0 + 0x10c4 0xd0 0x0 + 0x10cc 0x55 0x0 + 0x10d0 0x55 0x0 + 0x10d4 0x03 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x34 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x0a 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x1174 0x20 0x0 + 0x117c 0x06 0x0 + 0x11a0 0x14 0x0 + 0x11a8 0x0f 0x0 + 0x0220 0x16 0x0 + 0x03c0 0x38 0x0 + 0x0a20 0x16 0x0 + 0x0bc0 0x38 0x0 + 0x0364 0xcc 0x0 + 0x036c 0xcc 0x0 + 0x0378 0x31 0x0 + 0x037c 0xc5 0x0 + 0x0380 0xcc 0x0 + 0x0384 0xb6 0x0 + 0x0388 0xc2 0x0 + 0x038c 0x17 0x0 + 0x0390 0xfb 0x0 + 0x0394 0x0f 0x0 + 0x039c 0xee 0x0 + 0x03a0 0xbf 0x0 + 0x03a4 0x80 0x0 + 0x03a8 0x81 0x0 + 0x03ac 0xdf 0x0 + 0x03b0 0x5f 0x0 + 0x0b64 0xcc 0x0 + 0x0b6c 0xcc 0x0 + 0x0b78 0x31 0x0 + 0x0b7c 0xc5 0x0 + 0x0b80 0xcc 0x0 + 0x0b84 0xb6 0x0 + 0x0b88 0xc2 0x0 + 0x0b8c 0x17 0x0 + 0x0b90 0xfb 0x0 + 0x0b94 0x0f 0x0 + 0x0b9c 0xee 0x0 + 0x0ba0 0xbf 0x0 + 0x0ba4 0x80 0x0 + 0x0ba8 0x81 0x0 + 0x0bac 0xdf 0x0 + 0x0bb0 0x5f 0x0 + 0x03b4 0x20 0x0 + 0x022c 0x3f 0x0 + 0x0230 0x2d 0x0 + 0x0bb4 0x20 0x0 + 0x0a2c 0x3f 0x0 + 0x0a30 0x2d 0x0 + 0x0078 0x05 0x0 + 0x007c 0xf6 0x0 + 0x0878 0x05 0x0 + 0x087c 0xf6 0x0 + 0x0290 0x05 0x0 + 0x0a90 0x05 0x0 + 0x03f8 0x1f 0x0 + 0x0400 0x1f 0x0 + 0x0408 0x1f 0x0 + 0x0410 0x1f 0x0 + 0x0418 0x1f 0x0 + 0x0420 0x1f 0x0 + 0x03f4 0x1f 0x0 + 0x03fc 0x1f 0x0 + 0x0404 0x1f 0x0 + 0x0bf8 0x1f 0x0 + 0x0c00 0x1f 0x0 + 0x0c08 0x1f 0x0 + 0x0c10 0x1f 0x0 + 0x0c18 0x1f 0x0 + 0x0c20 0x1f 0x0 + 0x0bf4 0x1f 0x0 + 0x0bfc 0x1f 0x0 + 0x0c04 0x1f 0x0 + 0x0208 0x0c 0x0 + 0x0a08 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0a0c 0x0a 0x0 + 0x02dc 0x0a 0x0 + 0x0adc 0x0a 0x0 + 0x0308 0x0b 0x0 + 0x0b08 0x0b 0x0 + 0x027c 0x1f 0x0 + 0x0a7c 0x1f 0x0 + 0x02b4 0x00 0x0 + 0x0ab4 0x00 0x0 + 0x02ec 0x0d 0x0 + 0x0aec 0x0d 0x0 + 0x02c4 0x00 0x0 + 0x02c8 0x1f 0x0 + 0x0ac4 0x00 0x0 + 0x0ac8 0x1f 0x0 + 0x0030 0x1a 0x0 + 0x0034 0x0c 0x0 + 0x0830 0x1a 0x0 + 0x0834 0x0c 0x0 + 0x141c 0xc1 0x0 + 0x1490 0x00 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x22 0x0 + 0x1508 0x02 0x0 + 0x14a0 0x16 0x0 + 0x1584 0x28 0x0 + 0x1370 0x2e 0x0 + 0x155c 0x2e 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; pcie0_rp: pcie0_rp { reg = <0 0 0 0 0>; From 17f04c91b5039101976edb0444c243e0362346cb Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Wed, 23 Sep 2020 10:30:40 +0800 Subject: [PATCH 69/98] ARM: dts: msm: disable wsa_spkr_en2 for Lahaina HDK device Disable wsa_spkr_en2 for Lahaina HDK device. Change-Id: Ibe689b525e1518d8f34387dfe4973e999544ab46 --- qcom/lahaina-hdk.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index d7f25716d987..37ee98b48a83 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -4,6 +4,10 @@ status = "disabled"; }; +&wsa_spkr_en2 { + status = "disabled"; +}; + &lahaina_snd { qcom,model = "lahaina-hdk-snd-card"; From 0012c033a287818135b4b6ac0b23650026d99a53 Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Wed, 10 Jun 2020 01:00:12 -0700 Subject: [PATCH 70/98] ARM: dts: msm: new vdd power rail of USB QMP PHY for lahaina-v2 The (secondary) USB QMP PHY uses a different power rail for its VDD supply on lahaina-v2. Update it to &pm8350_l5. Change-Id: I29d133cacd12a1108370230dcc1c2f80385ad77e --- qcom/lahaina-v2.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index 1391441bb5d8..f089e5cd052f 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -126,6 +126,11 @@ compatible = "qcom,lahaina-camcc-v2", "syscon"; }; +&usb_qmp_phy { + vdd-supply = <&pm8350_l5>; + qcom,vdd-voltage-level = <0 880000 888000>; +}; + #include "lahaina-v2-gpu.dtsi" &cpu0_cpu_l3_tbl { From ea8649d729ca774297b0e3137254a973fa7ebc97 Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Wed, 23 Sep 2020 18:19:28 +0530 Subject: [PATCH 71/98] ARM: dts: msm: Add cnss-enable-self-recovery flag for lahaina Add cnss-enable-self-recovery flag for lahaina. It enables self recovery on link down. Update the documentation for the cnss-enable-self-recovery flag. Change-Id: Ifd9f3c23ec8e6c56874f6964cd8134520c2e9c6d --- bindings/cnss/cnss-wlan.txt | 2 ++ qcom/lahaina.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index f047adc4b3f4..02d983d74138 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -85,6 +85,8 @@ Optional properties: - qcom,bus-bw-cfg: Bus bandwidth voting data - qcom,tcs_offset_int_pow_amp_vreg: TCS CMD register offset for Voltage regulator used in internal power amplifier for QCA6490 + - cnss-enable-self-recovery: Boolean property to enable self recovery when + recovery is trigeered with reason link down. Example: diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index bc26eca67236..2f48611e3666 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5364,6 +5364,7 @@ /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<2> offset */ qcom,tcs_offset_int_pow_amp_vreg = <0x4D0>; use-pm-domain; + cnss-enable-self-recovery; vdd-wlan-aon-supply = <&S2E>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From af16f9ab870e1b902fe7152b743a723bb9ecb7e4 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 14 Aug 2020 01:31:04 +0530 Subject: [PATCH 72/98] dt-bindings: interconnect: add interconnect bindings Add interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: Icf836295d471a2ee661f772dea883d0bf07ede9c --- bindings/interconnect/qcom,epss-l3.txt | 1 + bindings/interconnect/qcom,yupik.txt | 31 ++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 bindings/interconnect/qcom,yupik.txt diff --git a/bindings/interconnect/qcom,epss-l3.txt b/bindings/interconnect/qcom,epss-l3.txt index 8bd41c0a753e..d3a31ad4e6df 100644 --- a/bindings/interconnect/qcom,epss-l3.txt +++ b/bindings/interconnect/qcom,epss-l3.txt @@ -10,6 +10,7 @@ Required properties : "qcom,lahaina-epss-l3-cpu", "qcom,shima-epss-l3-cpu", "qcom,shima-epss-l3-shared"; + "qcom,yupik-epss-l3-cpu", - reg : Address and length of the register set for the device - clock-names: should contain "xo", "alternate" - clocks: list of phandle and clock specifier pairs corresponding to diff --git a/bindings/interconnect/qcom,yupik.txt b/bindings/interconnect/qcom,yupik.txt new file mode 100644 index 000000000000..f60a0b12fe7e --- /dev/null +++ b/bindings/interconnect/qcom,yupik.txt @@ -0,0 +1,31 @@ +Qualcomm Technologies, Inc. Yupik Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +Yupik interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must point to at +least one RPMh device child node pertaining to their RSC and each provider +can map to multiple RPMh resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,yupik-aggre1_noc", + "qcom,yupik-aggre2_noc", + "qcom,yupik-clk_virt", + "qcom,yupik-config_noc", + "qcom,yupik-dc_noc", + "qcom,yupik-gem_noc", + "qcom,yupik-lpass_ag_noc", + "qcom,yupik-mc_virt", + "qcom,yupik-mmss_noc", + "qcom,yupik-nsp_noc", + "qcom,yupik-system_noc", +- #interconnect-cells : should contain 1 + +Examples: + +aggre1_noc: interconnect@16e0000 { + compatible = "qcom,yupik-aggre1_noc"; + interconnect-cells = <1>; +}; From babd671c62e0c2ee9b58a663fe7d9e6f70b3bae3 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 23 Sep 2020 11:14:38 -0700 Subject: [PATCH 73/98] dt-bindings: arm: msm: update documentation for PCIe internal AUX CLK PCIe internal AUX clock frequency used to be either 1MHz or 19.2MHz. The devicetree entry was a boolean type to determine which frequency to program in PCIe controller. Newer chipsets may support other frequencies such as 16.6MHz. Update the devicetree entry so that it accepts a decimal value for the desired frequency to be programmed in PCIe controller. Change-Id: I5818f5973ddbbce4268eafb6e99202daeba4234a --- bindings/pci/pci-msm.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index a864094c6b12..8a9fa1e1c6fe 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -229,10 +229,12 @@ interconnects: link into l1ss sleep while idle in l1ss. If this is omitted, the default timeout is 100ms. -- qcom,use-19p2mhz-aux-clk: +- qcom,aux-clk-freq: Usage: optional - Value type: - Definition: Set PCIe AUX clock frequency to 19.2MHz + Value type: + Definition: Override reset value for PCIe internal aux clock frequency. + Value will be the actual frequency rounded up to the nearest + decimal. For example, use 17 for 16.6MHz. - qcom,common-clk-en: Usage: optional @@ -504,7 +506,6 @@ Example qcom,link-check-max-count = <40> /* 200ms */ qcom,boot-option = <0x1>; qcom,drv-supported; - qcom,use-19p2mhz-aux-clk; qcom,common-clk-en; qcom,clk-power-manage-en; qcom,n-fts = <0x50>; From 2b01efc315a7ddd1bc0b914d58fac4d9df2d5a1b Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 23 Sep 2020 11:21:33 -0700 Subject: [PATCH 74/98] ARM: dts: msm: remove deprecated PCIe AUX CLK frequency for lahaina PCIe internal AUX clock frequency setting has been change from boolean to u32. On Lahaina, the reset value of this settings is correct and does not need the new devicetree entry to override it. Therefore, remove the deprecated entry for Lahaina. Change-Id: I4b0eb9f3e98ffdf894d4245212e64af618ac80e0 --- qcom/lahaina-pcie.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 451f2627764f..f15c2e4eda1b 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -103,7 +103,6 @@ qcom,drv-supported; qcom,l1ss-sleep-disable = <0x1>; qcom,drv-l1ss-timeout-us = <5000>; - qcom,use-19p2mhz-aux-clk; qcom,no-l0s-supported; qcom,l1-2-th-scale = <2>; qcom,l1-2-th-value = <70>; @@ -330,7 +329,6 @@ qcom,boot-option = <0x1>; qcom,drv-supported; - qcom,use-19p2mhz-aux-clk; qcom,wr-halt-size = <0x8>; qcom,no-l0s-supported; qcom,slv-addr-space-size = <0x20000000>; From e57572252768c3f3965fcb4df71ade35693bcb26 Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Thu, 24 Sep 2020 12:13:18 +0530 Subject: [PATCH 75/98] dt-bindings: input: touchscren: add description for synaptics_dsx Add new file for synaptics_dsx touchscreen drive IC. Change-Id: I92e089bfad8736e286fd308e98b5b5daf5fefeed --- .../input/touchscreen/synaptics_dsx_i2c.txt | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 bindings/input/touchscreen/synaptics_dsx_i2c.txt diff --git a/bindings/input/touchscreen/synaptics_dsx_i2c.txt b/bindings/input/touchscreen/synaptics_dsx_i2c.txt new file mode 100644 index 000000000000..131942dd0ae9 --- /dev/null +++ b/bindings/input/touchscreen/synaptics_dsx_i2c.txt @@ -0,0 +1,62 @@ +Synaptics DSXV27 touch controller + +Please add this description here: The Synaptics Touch controller is connected to the +host processor via I2C. The controller generates interrupts when the user touches +the panel. The host controller is expected to read the touch coordinates over I2C and +pass the coordinates to the rest of the system. + +Required properties: + + - compatible : should be "synaptics,dsx-i2c". + - reg : i2c slave address of the device. + - interrupt-parent : parent of interrupt. + - synaptics,irq-gpio : irq gpio. + - synaptics,reset-gpio : reset gpio. + - vdd_supply : digital voltage power supply needed to power device. + - avdd_supply : analog voltage power supply needed to power device. + - synaptics,pwr-reg-name : power reg name of digital voltage. + - synaptics,bus-reg-name : bus reg name of analog voltage. + +Optional property: + - synaptics,ub-i2c-addr : addr of ub-i2c. + - synaptics,irq-on-state : status of irq gpio. + - synaptics,cap-button-codes : virtual key code mappings to be used. + - synaptics,vir-button-codes : virtual key code and the response region on panel. + - synaptics,x-flip : modify orientation of the x axis. + - synaptics,y-flip : modify orientation of the y axis. + - synaptics,reset-delay-ms : reset delay for controller (ms), default 100. + - synaptics,power-delay-ms : power delay for controller (ms), default 100. + - synaptics,reset-active-ms : reset active time for controller (ms), default 20. + - synaptics,max-y-for-2d : maximal y value of the panel. + - clock-names : Clock names used for secure touch. They are: "iface_clk", "core_clk" + - clocks : Defined if 'clock-names' DT property is defined. These clocks + are associated with the underlying I2C bus. + +Example: + i2c@78b7000 { + status = "ok"; + synaptics@4b { + compatible = "synaptics,dsx-i2c"; + reg = <0x4b>; + interrupt-parent = <&tlmm>; + interrupts = <65 0x2008>; + vdd_supply = <&pmtitanium_l17>; + avdd_supply = <&pmtitanium_l6>; + synaptics,pwr-reg-name = "vdd"; + synaptics,bus-reg-name = "avdd"; + synaptics,ub-i2c-addr = <0x2c>; + synaptics,irq-gpio = <&tlmm 65 0x2008>; + synaptics,reset-gpio = <&tlmm 99 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-active-ms = <20>; + synaptics,max-y-for-2d = <1919>; /* remove if no virtual buttons */ + synaptics,cap-button-codes = <139 172 158>; + synaptics,vir-button-codes = <139 180 2000 320 160 172 540 2000 320 160 158 900 2000 320 160>; + /* Underlying clocks used by secure touch */ + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; + }; + }; From 015f417801c6e83b0a2cb27420e515d2af9dfa19 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Thu, 24 Sep 2020 15:15:34 +0800 Subject: [PATCH 76/98] ARM: dts: msm: support 4 lanes display on shima QRD allow USB request redriver to enter DP only mode. Change-Id: Iaadf5d1c33412da262a5151b32c00d5630be8b4b --- qcom/shima-qrd.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 1572cd0d8edb..365de2bb9f2c 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -311,6 +311,10 @@ &tert_mi2s_sd0_sleep>; }; +&usb0 { + ssusb_redriver = <&redriver>; +}; + &usb_qmp_dp_phy { pinctrl-names = "portselect"; }; From 8572f0b491a8afdb7238a30eaf553ffa41f74b1d Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 24 Sep 2020 10:16:30 -0700 Subject: [PATCH 77/98] ARM: dts: msm: Enable USB AHB reset on sdxlemur Rumi AHB reset was disabled as USB enumeration was failing on sdxlemur Rumi due to a RTL related issue. The issue is fixed on RTL version>=E3.9. Hence enable AHB reset as part of PHY reset on Rumi. Change-Id: I2838ac4d624f55901a62d5ee74c1ad7b709f1ab8 --- qcom/sdxlemur-rumi.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur-rumi.dtsi b/qcom/sdxlemur-rumi.dtsi index f7394765df36..d0967c1dacf5 100644 --- a/qcom/sdxlemur-rumi.dtsi +++ b/qcom/sdxlemur-rumi.dtsi @@ -13,8 +13,8 @@ compatible = "qcom,usb-emu-phy"; reg = <0x0a720000 0x9500>; - qcom,emu-init-seq = <0xfffdf 0x4 - 0xfffd0 0x4 + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 0x100000 0x20 0x0 0x20 0x101f0 0x20 From ae6ad3a83902b23df56e868ea63efcd8ad7dda3b Mon Sep 17 00:00:00 2001 From: Arun Menon Date: Thu, 24 Sep 2020 16:01:21 -0700 Subject: [PATCH 78/98] ARM: dts: msm: Change prng dtsi config from 32 bit to 64 bits Set PRNG TPDM to 64 bits for entropy collection to work. Acked-by : Yin Ling Liong Change-Id: I3857164e8bc00fd531083b9c0354d91a895b3f63 --- qcom/lahaina-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index fbe7d8b89e88..3342e9e9e0f5 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -1007,7 +1007,7 @@ <15 64>, <20 64>, <22 32>, - <23 32>, + <23 64>, <24 32>, <27 32>, <28 32>, From ed3930673281f69e3be79a15b7062c70c5160f1d Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Fri, 25 Sep 2020 10:47:40 +0800 Subject: [PATCH 79/98] ARM: dts: msm: add touch for Holi 90hz panel Add touch node associated with new 90Hz panel for QRD Holi devices. Change-Id: I846d18217128c7ab691fc216cf8003e226df0817 --- qcom/holi-qrd.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 7ff5d15c5ea8..a9d92ea08dcb 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -120,7 +120,9 @@ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&pmx_ts_release>; - panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + panel = <&dsi_r66451_amoled_90hz_cmd + &dsi_r66451_amoled_90hz_video + &dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; }; }; From b607012878fe3b8ccbdde09ca04c235303df0364 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Fri, 25 Sep 2020 12:03:32 -0700 Subject: [PATCH 80/98] ARM: dts: msm: Remove interconnect phandles from clock nodes Clock optionally votes for interconnect in runtime_resume and runtime_suspend to ensure access to its configuration registers. However, interconnect also votes for clocks when configuring QoS. This can lead to deadlocks between the clock and interconnect frameworks. Voting for interconnects isn't strictly necessary for register access currently, since the required bus (CNOC) is always on when HLOS is running. Voting may become necessary in the future, but until then remove the interconnect phandles to prevent the deadlocks. Change-Id: If4392361a394b7ace52cb95a0ac2184bf64a7882 --- qcom/lahaina.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index bc26eca67236..7d3ebada79b5 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2347,7 +2347,6 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; @@ -2360,7 +2359,6 @@ reg-names = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; @@ -2372,7 +2370,6 @@ reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; From 2362bf12bcde3a15ab40614ab1a8222ea3565c40 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 14 Aug 2020 01:29:41 +0530 Subject: [PATCH 81/98] ARM: dts: msm: add stub interconnect devices for YUPIK Add stub interconnect devices for aggre1_noc, aggre2_noc, config_noc, dc_noc, gem_noc, lpass_ag_noc, mc_virt_noc, mmss_noc, nsp_noc, system_noc, This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I3dc8f90709f3db9f7e901e8a00876efe9ceecde0 --- qcom/yupik.dtsi | 62 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 103ef0178a48..6e62ea188e5e 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -5,6 +5,9 @@ #include #include #include +#include +#include +#include #include / { @@ -373,6 +376,65 @@ #reset-cells = <1>; }; + clk_virt: interconnect { + compatible = "qcom,yupik-clk_virt"; + #interconnect-cells = <1>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,yupik-config_noc"; + #interconnect-cells = <1>; + }; + + mc_virt: interconnect@1580000 { + compatible = "qcom,yupik-mc_virt"; + #interconnect-cells = <1>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,yupik-system_noc"; + #interconnect-cells = <1>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,yupik-aggre1_noc"; + #interconnect-cells = <1>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,yupik-aggre2_noc"; + #interconnect-cells = <1>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,yupik-mmss_noc"; + #interconnect-cells = <1>; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,yupik-lpass_ag_noc"; + #interconnect-cells = <1>; + }; + + dc_noc: interconnect@90e0000 { + compatible = "qcom,yupik-dc_noc"; + #interconnect-cells = <1>; + }; + + gem_noc: interconnect@9100000 { + compatible = "qcom,yupik-gem_noc"; + #interconnect-cells = <1>; + }; + + nsp_noc: interconnect@a0c0000 { + compatible = "qcom,yupik-nsp_noc"; + #interconnect-cells = <1>; + }; + + epss_l3_cpu: l3_cpu@18590000 { + compatible = "qcom,yupik-epss-l3-cpu"; + #interconnect-cells = <1>; + }; }; #include "shima-gdsc.dtsi" From 67ee5abaa139d9a500aa43c8d26ddd996968bb63 Mon Sep 17 00:00:00 2001 From: Murali Nalajala Date: Fri, 25 Sep 2020 15:22:18 -0700 Subject: [PATCH 82/98] ARM: dts: msm: enable vm console suspend Keeping "no_console_suspend" causing a frequent wakeups when VM enter into suspend state. This is because console is implemented on RM console where RM console interrupts are configured as wakeup capable. Remove "no_console_suspend" to avoid wakeups. User can control this feature using below node. echo Y > /sys/module/printk/parameters/console_suspend. Change-Id: Iefd7f78c4155c9fa80e634c5799aa52024804c86 --- qcom/lahaina-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 24826e34f88b..4dd0d3ebe88e 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -15,7 +15,7 @@ }; chosen { - bootargs = "nokaslr no_console_suspend root=/dev/ram rw init=/init console=hvc0 loglevel=8"; + bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8"; linux,initrd-start = <0x2a900000>; linux,initrd-end = <0x2b100000>; /* 8 MB */ kaslr-seed = <0xfeedbeef 0xc0def00d>; From cc49071b3b5f92c1c55d1020f6c3b6b1860b2bfc Mon Sep 17 00:00:00 2001 From: Murali Nalajala Date: Sat, 26 Sep 2020 09:40:25 -0700 Subject: [PATCH 83/98] ARM: dts: msm: increase vm log buf size for lahaina Increase log_buf size for shima, to avoid losing bootup logs which might be required for debugging. Change-Id: Ie8ec6cd7dc084cc3fc41d280ff6e008ac8d9cd8f --- qcom/lahaina-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 4dd0d3ebe88e..566dcd1074bd 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -15,7 +15,7 @@ }; chosen { - bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8"; + bootargs = "nokaslr log_buf_len=256K root=/dev/ram rw init=/init console=hvc0 loglevel=8"; linux,initrd-start = <0x2a900000>; linux,initrd-end = <0x2b100000>; /* 8 MB */ kaslr-seed = <0xfeedbeef 0xc0def00d>; From dd31ba30eb4d0ac32ebfade3877e8e16a4b840e2 Mon Sep 17 00:00:00 2001 From: Wenjun Zhang Date: Fri, 7 Aug 2020 13:42:56 +0800 Subject: [PATCH 84/98] ARM: dts: msm: enable lt9611uxc for hdk8350 Add lt9611uxc pincttl and dts configure. Change-Id: I9c559051a4779e3b41c6cdc941c3f7fa00765e24 --- qcom/lahaina-hdk.dtsi | 103 ++++++++++++++++++++++++++++++++++++++ qcom/lahaina-pinctrl.dtsi | 13 +++++ 2 files changed, 116 insertions(+) diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi index 5b02c6e0b39f..005e4ff816c5 100644 --- a/qcom/lahaina-hdk.dtsi +++ b/qcom/lahaina-hdk.dtsi @@ -81,3 +81,106 @@ &sdhc_2 { cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; }; + +&qupv3_se15_i2c { + status = "ok"; + + lt9611: lt,lt9611@2b { + compatible = "lt,lt9611uxc"; + reg = <0x2b>; + interrupt-parent = <&tlmm>; + interrupts = <50 0>; + interrupt-names = "lt_irq"; + lt,irq-gpio = <&tlmm 50 0x0>; + lt,reset-gpio = <&tlmm 48 0x0>; + lt,hdmi-3p3-en = <&tlmm 47 0x0>; + lt,hdmi-1p2-en = <&tlmm 49 0x0>; + lt,non-pluggable; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_pins>; + + lt,preferred-mode = "1920x1080"; + + lt,customize-modes { + lt,customize-mode-id@0 { + lt,mode-h-active = <1920>; + lt,mode-h-front-porch = <88>; + lt,mode-h-pulse-width = <44>; + lt,mode-h-back-porch = <148>; + lt,mode-h-active-high; + lt,mode-v-active = <1080>; + lt,mode-v-front-porch = <4>; + lt,mode-v-pulse-width = <5>; + lt,mode-v-back-porch = <36>; + lt,mode-v-active-high; + lt,mode-refresh-rate = <60>; + lt,mode-clock-in-khz = <148500>; + }; + + lt,customize-mode-id@1 { + lt,mode-h-active = <3840>; + lt,mode-h-front-porch = <176>; + lt,mode-h-pulse-width = <88>; + lt,mode-h-back-porch = <400>; + lt,mode-h-active-high; + lt,mode-v-active = <2160>; + lt,mode-v-front-porch = <8>; + lt,mode-v-pulse-width = <10>; + lt,mode-v-back-porch = <72>; + lt,mode-v-active-high; + lt,mode-refresh-rate = <60>; + lt,mode-clock-in-khz = <608040>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt9611_in_0: endpoint { + remote-endpoint = <&ext_dsi_0_out>; + }; + }; + + port@1 { + reg = <1>; + lt9611_in_1: endpoint { + remote-endpoint = <&ext_dsi_1_out>; + }; + }; + }; + }; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ext_dsi_0_out: endpoint { + remote-endpoint = <<9611_in_0>; + }; + }; + }; +}; + +&sde_dsi1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + ext_dsi_1_out: endpoint { + remote-endpoint = <<9611_in_1>; + }; + }; + }; +}; diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi index 4da16fb2cccb..3c81288625d9 100644 --- a/qcom/lahaina-pinctrl.dtsi +++ b/qcom/lahaina-pinctrl.dtsi @@ -380,6 +380,19 @@ }; }; + lt9611_pins: lt9611_pins { + mux { + pins = "gpio47", "gpio48", "gpio49", "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", "gpio50"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + nfc { nfc_int_active: nfc_int_active { /* active state */ From 690d106d3d544e9c979c8b33135f934a446d23df Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Tue, 1 Sep 2020 20:21:57 +0530 Subject: [PATCH 85/98] ARM: dts: msm: add initial support for hw memlat devices Add initial support for RIMPS memlat devices, it votes for L3 clock based on the IPM ratio falling below set_threshold. Change-Id: I2d2a5f8688513dd4fac23f16dc4e140f4fce0b0f --- qcom/holi.dtsi | 266 ++++++++++++++++++------------------------------- 1 file changed, 98 insertions(+), 168 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 165d453efd75..e5a0ef6954b8 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -434,6 +434,19 @@ }; }; + sram: sram@fd04480 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x0fd04480 0x0 0x80>; + ranges = <0x0 0x0 0x0 0x0fd04480 0x0 0x80>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scp-shmem"; + reg = <0x0 0x0 0x0 0x80>; + }; + }; + chosen { bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; }; @@ -1315,66 +1328,6 @@ qcom,count-unit = <0x10000>; }; - cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>; - }; - - cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>; - }; - - cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>; - }; - - cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>; - }; - - cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>; - }; - - cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>; - }; - cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { compatible = "qcom,devfreq-icc"; governor = "compute"; @@ -1383,26 +1336,6 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; - cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>; - }; - - cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { - compatible = "qcom,devfreq-icc-l3"; - reg = <0xFD90100 0xa0>; - reg-names = "ftbl-base"; - governor = "mem_latency"; - interconnects = - <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS - &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>; - }; - cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { compatible = "qcom,devfreq-icc"; governor = "mem_latency"; @@ -1427,78 +1360,10 @@ operating-points-v2 = <&ddr_bw_opp_table>; }; - cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { - qcom,core-dev-table = - < 710400 300000000 >, - < 940800 518400000 >, - < 1190400 748800000 >, - < 1478400 921600000 >, - < 1574400 1305600000 >, - < 1804800 1459000000 >; - }; - - cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl { - qcom,core-dev-table = - < 1017600 518400000 >, - < 1248000 748800000 >, - < 1536000 921600000 >, - < 1651200 1171200000 >, - < 1804800 1305600000 >, - < 2035200 1459000000 >; - }; - cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0>; - qcom,target-dev = <&cpu0_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU1>; - qcom,target-dev = <&cpu1_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU2>; - qcom,target-dev = <&cpu2_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU3>; - qcom,target-dev = <&cpu3_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU4>; - qcom,target-dev = <&cpu4_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - - cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU5>; - qcom,target-dev = <&cpu5_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; - }; - cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; @@ -1527,26 +1392,6 @@ compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU6 &CPU7>; - cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6>; - qcom,target-dev = <&cpu6_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,access-ev = <0x2B>; - qcom,wb-ev = <0x18>; - qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; - }; - - cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU7>; - qcom,target-dev = <&cpu7_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,access-ev = <0x2B>; - qcom,wb-ev = <0x18>; - qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; - }; - cpu6_cpu_ddr_latmon: qcom,cpu6-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU6 &CPU7>; @@ -1573,6 +1418,91 @@ }; }; + rimps: qcom,rimps@0f400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,rimps"; + reg = <0x0f400000 0x10>, + <0x0fd90000 0x2000>; + #mbox-cells = <1>; + interrupts = <0 22 4>; + }; + + cpu0_grp: qcom,cpu0_grp { + compatible = "qcom,rimps-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0fd04980 0x300>; + reg-names = "pmu-base"; + + cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon { + compatible = "qcom,rimps-memlat-mon-l3"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cachemiss-ev = <0x17>; + reg = <0xfd90100 0xa0>, <0xfd90320 0x4>; + reg-names = "ftbl-base", "perf-base"; + + qcom,core-dev-table = + < 710400 300000000 >, + < 940800 518400000 >, + < 1190400 748800000 >, + < 1478400 921600000 >, + < 1574400 1305600000 >, + < 1804800 1459000000 >; + }; + }; + + cpu6_grp: qcom,cpu6_grp { + compatible = "qcom,rimps-memlat-cpugrp"; + qcom,cpulist = <&CPU6 &CPU7>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0fd04980 0x300>; + reg-names = "pmu-base"; + + cpu6_rimps_l3_latmon: qcom,cpu6-rimps-l3-latmon { + compatible = "qcom,rimps-memlat-mon-l3"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cachemiss-ev = <0x17>; + qcom,wb-ev = <0x18>; + qcom,access-ev = <0x2B>; + reg = <0xfd90100 0xa0>, <0xfd90320 0x4>; + reg-names = "ftbl-base", "perf-base"; + + qcom,core-dev-table = + < 1017600 518400000 >, + < 1248000 748800000 >, + < 1536000 921600000 >, + < 1651200 1171200000 >, + < 1804800 1305600000 >, + < 2035200 1459000000 >; + }; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&rimps 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_memlat: protocol@80 { + reg = <0x80>; + #clock-cells = <1>; + }; + }; + + rimps_log: qcom,rimps_log@fd04780 { + compatible = "qcom,rimps-log"; + reg = <0x0fd04580 0x200>, + <0x0fd04780 0x200>; + mboxes = <&rimps 1>; + }; + tcsr_mutex_block: syscon@340000 { compatible = "syscon"; reg = <0x340000 0x20000>; From f53721e040fe5d5d09cf3f31f4798212b602485a Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Mon, 17 Aug 2020 15:52:56 +0530 Subject: [PATCH 86/98] ARM: dts: msm: reserved memory for yupik Add carveout memory regions for yupik. This carveout memory is used by various subsystems for their purpose. Change-Id: I67d4224a4e2452b1c7645f76883f5e40a6ecc3d3 --- qcom/yupik.dtsi | 117 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 6e62ea188e5e..7c8173cfd526 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -177,6 +177,123 @@ }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: cmd_db@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + secdata_apss_mem: secdata_apss@808ff000 { + no-map; + reg = <0x0 0x808ff000 0x0 0x1000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + wlan_fw_mem: wlan_fw@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0xc00000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap@81800000 { + no-map; + reg = <0x0 0x81800000 0x0 0x1e00000>; + }; + + pil_cvp_mem: camera@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x500000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + pil_camera_mem: video@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0x500000>; + }; + + pil_video_mem: cvp@8b200000 { + no-map; + reg = <0x0 0x8b200000 0x0 0x500000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_mem: mpss@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0xf600000>; + }; + + pil_wpss_mem: wlan@9ae00000 { + no-map; + reg = <0x0 0x9ae00000 0x0 0x1900000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + soc: soc { }; chosen { }; From 6019f2707aea4483b7085ebd2de78276ad157810 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 28 Sep 2020 18:54:28 +0530 Subject: [PATCH 87/98] ARM: dts: msm: Update focaltech enteries on shima trustedvm Add display-coords and max-touch focaltech touch enteries on trusted vm for shima platform. Change-Id: I760f5e7c23527243320ac438173a0de35ded7cb6 --- qcom/shima-vm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 2ef350f4a81f..03d7359ab920 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -276,6 +276,8 @@ focaltech@38 { compatible = "focaltech,fts_ts"; reg = <0x38>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "tvm"; focaltech,trusted-touch-spi-irq = <566>; From 58dced493dbf42f19ac1527532700627342e8159 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 28 Sep 2020 19:59:20 +0530 Subject: [PATCH 88/98] ARM: dts: msm: Update focaltech enteries on lahaina qrd trustedvm Add display-coords and max-touch focaltech touch enteries on trusted vm for lahaina QRD platform. Change-Id: Id3b9029f35462f9af9a6a657e401ed9fdf3c21cb --- qcom/lahaina-vm-qrd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina-vm-qrd.dtsi b/qcom/lahaina-vm-qrd.dtsi index f2010601c08b..863f06638c78 100644 --- a/qcom/lahaina-vm-qrd.dtsi +++ b/qcom/lahaina-vm-qrd.dtsi @@ -5,6 +5,8 @@ focaltech@38 { compatible = "focaltech,fts_ts"; reg = <0x38>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "tvm"; focaltech,trusted-touch-spi-irq = <566>; From e913d2e227badd475cb311c587749904bb0a963c Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Mon, 28 Sep 2020 11:47:52 -0700 Subject: [PATCH 89/98] ARM: dts: msm: Add modem mitigation for policy engine in lahaina Add Modem mitigation for both CX and MX policy engine violation in lahaina. Change-Id: I1486e167ca4168d835191c8a18d91c4ef5fd8a96 --- qcom/lahaina-thermal.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 3ed3d6eaac4b..933fdf203ac5 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -1218,6 +1218,12 @@ hysteresis = <1>; type = "passive"; }; + + mx_pe_config3: mx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; }; cooling-maps { @@ -1230,6 +1236,11 @@ trip = <&mx_pe_config2>; cooling-device = <&msm_gpu 1 1>; }; + + mx_pe_cdev_3 { + trip = <&mx_pe_config3>; + cooling-device = <&modem_tj 1 1>; + }; }; }; @@ -1258,6 +1269,12 @@ }; cx_pe_config4: cx-pe-config4 { + temperature = <4>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config5: cx-pe-config5 { temperature = <5>; hysteresis = <2>; type = "passive"; @@ -1282,6 +1299,11 @@ cx_pe_cdev_4 { trip = <&cx_pe_config4>; + cooling-device = <&modem_tj 1 1>; + }; + + cx_pe_cdev_5 { + trip = <&cx_pe_config5>; cooling-device = <&cdsp_sw 4 4>; }; }; From 8fd1f5ec43991e0eb8c4cd34b72e8a4d0ea39784 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 18 Sep 2020 17:01:13 -0700 Subject: [PATCH 90/98] ARM: dts: msm: Add emergency skin rule for lahaina Add emergency skin rule based on xo-therm to trigger frequency mitigation and core isolation at 78C and hotplug at 80C. Change-Id: I9fef2b9bdf827f9b660d7c1e34d55607cbd4b97b --- qcom/lahaina-pmic-overlay.dtsi | 21 ++++++++++++ qcom/lahaina-thermal-overlay.dtsi | 56 +++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index 052c892cc915..5bb23e5950e5 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -607,6 +607,27 @@ }; }; }; + + xo-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + + trips { + xo_config0: active-config0 { + temperature = <78000>; + hysteresis = <8000>; + type = "passive"; + }; + + xo_config1: active-config1 { + temperature = <80000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; }; &soc { diff --git a/qcom/lahaina-thermal-overlay.dtsi b/qcom/lahaina-thermal-overlay.dtsi index 2889f53abedb..15a3f166fc78 100644 --- a/qcom/lahaina-thermal-overlay.dtsi +++ b/qcom/lahaina-thermal-overlay.dtsi @@ -296,4 +296,60 @@ }; }; }; + + xo-therm-step { + cooling-maps { + cpu4_freq_cdev { + trip = <&xo_config0>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu7_freq_cdev { + trip = <&xo_config0>; + cooling-device = <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu4_iso_cdev { + trip = <&xo_config0>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu5_iso_cdev { + trip = <&xo_config0>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + cpu6_iso_cdev { + trip = <&xo_config0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu7_iso_cdev { + trip = <&xo_config0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + cpu4_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + + cpu5_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + + cpu6_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + + cpu7_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; }; From b7e3313c0c981eab7be798fa121dd4c6bf67f3a9 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Thu, 10 Sep 2020 16:12:06 -0700 Subject: [PATCH 91/98] ARM: dts: msm: Update core isolation and hotplug threshold for lahaina Update core isolation and hotplug threshold for silver CPUs to 110C and 112C. Update core isolation and hotplug threshold for gold and gold plus to 108C and 110C. Change-Id: Id7d883e751a773869dea9f320e7f055da7584a69 --- qcom/lahaina-thermal.dtsi | 168 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 933fdf203ac5..8be59cb4c62e 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -778,6 +778,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu00_config1: cpu00-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -785,6 +791,17 @@ trip = <&cpu00_config>; cooling-device = <&cpu0_isolate 1 1>; }; + + cpu00_cdev1 { + trip = <&cpu00_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu00_cdev2 { + trip = <&cpu00_config1>; + cooling-device = <&cpu0_hotplug 1 1>; + }; }; }; @@ -799,6 +816,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu01_config1: cpu01-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -806,6 +829,17 @@ trip = <&cpu01_config>; cooling-device = <&cpu1_isolate 1 1>; }; + + cpu01_cdev1 { + trip = <&cpu01_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu01_cdev2 { + trip = <&cpu01_config1>; + cooling-device = <&cpu1_hotplug 1 1>; + }; }; }; @@ -820,6 +854,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu02_config1: cpu02-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -827,6 +867,17 @@ trip = <&cpu02_config>; cooling-device = <&cpu2_isolate 1 1>; }; + + cpu02_cdev1 { + trip = <&cpu02_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu02_cdev2 { + trip = <&cpu02_config1>; + cooling-device = <&cpu2_hotplug 1 1>; + }; }; }; @@ -841,6 +892,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu03_config1: cpu03-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -848,6 +905,17 @@ trip = <&cpu03_config>; cooling-device = <&cpu3_isolate 1 1>; }; + + cpu03_cdev1 { + trip = <&cpu03_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu03_cdev2 { + trip = <&cpu03_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; }; }; @@ -858,6 +926,12 @@ thermal-governor = "step_wise"; trips { cpu10_config: cpu10-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu10_config1: cpu10-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -875,6 +949,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu10_cdev2 { + trip = <&cpu10_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; }; }; @@ -885,6 +964,12 @@ thermal-governor = "step_wise"; trips { cpu11_config: cpu11-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu11_config1: cpu11-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -902,6 +987,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu11_cdev2 { + trip = <&cpu11_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; }; }; @@ -912,6 +1002,12 @@ thermal-governor = "step_wise"; trips { cpu12_config: cpu12-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu12_config1: cpu12-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -929,6 +1025,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu12_cdev2 { + trip = <&cpu12_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; }; }; @@ -939,6 +1040,12 @@ thermal-governor = "step_wise"; trips { cpu13_config: cpu13-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu13_config1: cpu13-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -956,6 +1063,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu13_cdev2 { + trip = <&cpu13_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; }; }; @@ -966,6 +1078,12 @@ thermal-governor = "step_wise"; trips { cpu14_config: cpu14-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu14_config1: cpu14-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -983,6 +1101,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu14_cdev2 { + trip = <&cpu14_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; }; }; @@ -993,6 +1116,12 @@ thermal-governor = "step_wise"; trips { cpu15_config: cpu15-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu15_config1: cpu15-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -1010,6 +1139,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu15_cdev2 { + trip = <&cpu15_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; }; }; @@ -1020,6 +1154,12 @@ thermal-governor = "step_wise"; trips { cpu16_config: cpu16-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu16_config1: cpu16-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -1031,6 +1171,17 @@ trip = <&cpu16_config>; cooling-device = <&cpu7_isolate 1 1>; }; + + cpu16_cdev1 { + trip = <&cpu16_config>; + cooling-device = <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu16_cdev2 { + trip = <&cpu16_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; }; }; @@ -1041,6 +1192,12 @@ thermal-governor = "step_wise"; trips { cpu17_config: cpu17-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu17_config1: cpu17-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -1052,6 +1209,17 @@ trip = <&cpu17_config>; cooling-device = <&cpu7_isolate 1 1>; }; + + cpu17_cdev1 { + trip = <&cpu17_config>; + cooling-device = <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu17_cdev2 { + trip = <&cpu17_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; }; }; From b69712d471e1cf4e4b2e98ada10ee7972c047cb8 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 29 Sep 2020 10:32:14 +0530 Subject: [PATCH 92/98] ARM: dts: msm: Disable wakeup capability for soundwire gpio Disable wakeup capability for soundwire gpio to avoid frequent wakeup during power collapse. Also register wakeup event listener as part of tx macro. Change-Id: I20367d0c7798a76eaebfaf3a5e00db78abca72fa --- qcom/shima-audio-overlay.dtsi | 2 +- qcom/shima-audio.dtsi | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 46490d3e67a6..5c44652dd529 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -33,7 +33,6 @@ qcom,va-dmic-sample-rate = <600000>; qcom,default-clk-id = ; qcom,is-used-swr-gpio = <0>; - qcom,disable-afe-wakeup-event-listener = <1>; }; tx_macro: tx-macro@3220000 { @@ -44,6 +43,7 @@ <&clock_audio_tx_2 0>; qcom,tx-swr-gpios = <&tx_swr_gpios>; qcom,tx-dmic-sample-rate = <2400000>; + qcom,disable-afe-wakeup-event-listener = <1>; swr2: tx_swr_master { compatible = "qcom,swr-mstr"; #address-cells = <2>; diff --git a/qcom/shima-audio.dtsi b/qcom/shima-audio.dtsi index 752938f13ecf..10ee18cc06de 100644 --- a/qcom/shima-audio.dtsi +++ b/qcom/shima-audio.dtsi @@ -109,6 +109,7 @@ pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep &rx_swr_data1_sleep>; qcom,lpi-gpios; + qcom,tlmm-pins = <172>; #gpio-cells = <0>; }; From 24076fd7c4e619ccab338181ebe05f426f8fa05c Mon Sep 17 00:00:00 2001 From: Fei Mao Date: Mon, 28 Sep 2020 12:40:48 +0800 Subject: [PATCH 93/98] ARM: dts: msm: New touch node for Lahaina CDP Add Synaptics touch node for qsync wqhd panel on Lahaina devices. Change-Id: I0fb7c9cdbcedb0ddd693fd62cd0b64a928327e77 --- qcom/lahaina-cdp.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 744c2ed73802..5bee66f2ef19 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -124,6 +124,32 @@ atmel,display-coords = <0 0 339 729>; panel = <&dsi_sharp_qhd_plus_dsc_cmd>; }; + + synaptics_dsx@22 { + compatible = "synaptics,dsx-i2c"; + reg = <0x22>; + interrupt-parent = <&tlmm>; + interrupts = <23 0x2008>; + vdd-supply = <&L8C>; + avdd-supply = <&L3C>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,ub-i2c-addr = <0x22>; + synaptics,max-y-for-2d = <1859>; + synaptics,irq-gpio = <&tlmm 23 0x2008>; + synaptics,reset-gpio = <&tlmm 22 0x00>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + + panel = <&dsi_sharp_qsync_wqhd_cmd &dsi_sharp_qsync_wqhd_video>; + }; }; &sdhc_2 { From 2af32db2474b746eb0860938357e0519558348a1 Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Tue, 29 Sep 2020 12:11:12 +0530 Subject: [PATCH 94/98] ARM: dts: msm: add is-always-on flag to fix HS LPI issue for holi Added is-always-on flag to skip the audio_hm vote during bootup and to vote/unvote during swrm_runtime_suspend and swrm_runtime_resume. Change-Id: Ifce00a198056590a3de7076c17b3c9f45a30fbc7 --- qcom/holi-audio-overlay.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 45e1fa8d6686..987572a7db74 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -57,6 +57,7 @@ qcom,swr-num-dev = <1>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; + qcom,is-always-on = <1>; wcd937x_tx_slave: wcd937x-tx-slave { compatible = "qcom,wcd937x-slave"; reg = <0x0A 0x01170223>; From 2c77fff619eafb24bfb5c328d4e7afdd0137243a Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 29 Sep 2020 15:31:37 +0800 Subject: [PATCH 95/98] ARM: dts: msm: Correct name of funnel merg on holi Correct name of funnel merg to "coresight-funnel-merg" on holi. Change-Id: If4c7d688f333f6b2d75e6570f40a1b401fefe55a --- qcom/holi-coresight.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index bb43ec947b84..95a7723749e2 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -1906,13 +1906,13 @@ }; }; - funnel_merge: funnel@8045000 { + funnel_merg: funnel@8045000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb908>; reg = <0x08045000 0x1000>; reg-names = "funnel-base"; - coresight-name = "coresight-funnel-merge"; + coresight-name = "coresight-funnel-merg"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; From 8e5996c2ef9170805f371c7856726f7c87edaa28 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 18 Aug 2020 12:47:51 +0530 Subject: [PATCH 96/98] ARM: dts: msm: Add Qpic Nand support for sdxlemur Add QPIC NAND Controller support for sdxlemur in device tree. Change-Id: I411d63c2b0c9aed2f43dcdc5a05d6527ca97d01b --- qcom/sdxlemur-cdp.dtsi | 3 +++ qcom/sdxlemur-mtp.dtsi | 3 +++ qcom/sdxlemur-rumi.dtsi | 4 ++++ qcom/sdxlemur.dtsi | 17 +++++++++++++++++ 4 files changed, 27 insertions(+) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 768d9aaa521c..0439a942f1ec 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -4,3 +4,6 @@ }; +&qnand_1 { + status = "ok"; +}; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 768d9aaa521c..0439a942f1ec 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -4,3 +4,6 @@ }; +&qnand_1 { + status = "ok"; +}; diff --git a/qcom/sdxlemur-rumi.dtsi b/qcom/sdxlemur-rumi.dtsi index f7394765df36..ec2a407bd2fa 100644 --- a/qcom/sdxlemur-rumi.dtsi +++ b/qcom/sdxlemur-rumi.dtsi @@ -26,6 +26,10 @@ }; +&qnand_1 { + status = "ok"; +}; + &usb { dwc3@a600000 { usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a9a6ec23a414..de55954f16c2 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -386,6 +386,23 @@ status = "ok"; }; + qnand_1: nand@1b00000 { + compatible = "qcom,msm-nand"; + reg = <0x01b00000 0x1000>, + <0x01b04000 0x1c000>; + reg-names = "nand_phys", + "bam_phys"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = ; + interrupt-names = "bam_irq"; + + clock-names = "core_clk"; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + + status = "disabled"; + }; + apsscc: clock-controller@17808000 { compatible = "qcom,dummycc"; clock-output-names = "apsscc_clocks"; From db96ff8891453758c05591c58cba1a7ccca26eaf Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 18 Sep 2020 11:27:03 +0530 Subject: [PATCH 97/98] ARM: dts: qcom: enable display on trusted vm for shima Enable display on trusted vm for shima target by including display dt files. Change-Id: I5fd30dd9c84f8f8c640eaa9e2b64039f14811d32 --- qcom/shima-vm.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 03d7359ab920..242012055766 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -1,4 +1,7 @@ #include +#include +#include +#include / { #address-cells = <0x2>; @@ -288,3 +291,5 @@ }; #include "lahaina-vm-ion.dtsi" +#include "display/trustedvm-shima-sde.dtsi" +#include "display/trustedvm-shima-sde-display.dtsi" From ec587be585ef895079a86eeed7580ee2711e39b3 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Thu, 1 Oct 2020 11:19:31 -0700 Subject: [PATCH 98/98] ARM: dts: msm: Update modem mitigation threshold for lahaina Update modem mitigation threshold and hysteresis for lahaina as per recommendation. sensor mdmss-1-step/mdmss-2-step algo_type step_wise polling_delay 0 passive_delay 0 trip 0 2 set_temp 95000 98000 105000 clr_temp 3000 2000 5000 device modem_tj modem_tj modem_tj upper_limit 1 2 3 lower_limit 1 2 3 Above is the new updated configuration. Change-Id: I6eddbe2ab29fb9942cdd608b1bd507fd9aa1c910 --- qcom/lahaina-thermal-modem.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/lahaina-thermal-modem.dtsi b/qcom/lahaina-thermal-modem.dtsi index 35b1ab87bc54..c13e66fa1abb 100644 --- a/qcom/lahaina-thermal-modem.dtsi +++ b/qcom/lahaina-thermal-modem.dtsi @@ -465,13 +465,13 @@ trips { mdmss10_config: active-config0 { temperature = <95000>; - hysteresis = <5000>; + hysteresis = <3000>; type = "passive"; }; mdmss11_config: active-config1 { - temperature = <100000>; - hysteresis = <5000>; + temperature = <98000>; + hysteresis = <2000>; type = "passive"; }; @@ -508,13 +508,13 @@ trips { mdmss20_config: active-config0 { temperature = <95000>; - hysteresis = <5000>; + hysteresis = <3000>; type = "passive"; }; mdmss21_config: active-config1 { - temperature = <100000>; - hysteresis = <5000>; + temperature = <98000>; + hysteresis = <2000>; type = "passive"; };