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Merge "disp: msm: dp: use correct lane_count to validate mode"

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qctecmdr 2020-10-13 00:22:43 -07:00 • committed by Gerrit - the friendly Code Review server
commit bd70659510
3 changed files with 19 additions and 12 deletions
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5
msm/dp/dp_ctrl.c
View file

@ -1012,14 +1012,15 @@ static void dp_ctrl_mst_calculate_rg(struct dp_ctrl_private *ctrl,
u64 raw_target_sc, target_sc_fixp;
u64 ts_denom, ts_enum, ts_int;
u64 pclk = panel->pinfo.pixel_clk_khz;
u64 lclk = panel->link_info.rate;
u64 lanes = panel->link_info.num_lanes;
u64 lclk = 0;
u64 lanes = ctrl->link->link_params.lane_count;
u64 bpp = panel->pinfo.bpp;
u64 pbn = panel->pbn;
u64 numerator, denominator, temp, temp1, temp2;
u32 x_int = 0, y_frac_enum = 0;
u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp;
lclk = drm_dp_bw_code_to_link_rate(ctrl->link->link_params.bw_code);
if (panel->pinfo.comp_info.comp_ratio > 1)
bpp = DSC_BPP(panel->pinfo.comp_info.dsc_info.config);

5
msm/dp/dp_display.c
View file

@ -2596,13 +2596,10 @@ end:
static int dp_display_validate_link_clock(struct dp_display_private *dp,
struct drm_display_mode *mode, struct dp_display_mode dp_mode)
{
struct drm_dp_link *link_info;
u32 mode_rate_khz = 0, supported_rate_khz = 0, mode_bpp = 0;
bool dsc_en;
int rate;
link_info = &dp->panel->link_info;
dsc_en = (dp_mode.timing.comp_info.comp_ratio > 1) ? true : false;
mode_bpp = dsc_en ?
DSC_BPP(dp_mode.timing.comp_info.dsc_info.config)
@ -2610,7 +2607,7 @@ static int dp_display_validate_link_clock(struct dp_display_private *dp,
mode_rate_khz = mode->clock * mode_bpp;
rate = drm_dp_bw_code_to_link_rate(dp->link->link_params.bw_code);
supported_rate_khz = link_info->num_lanes * rate * 8;
supported_rate_khz = dp->link->link_params.lane_count * rate * 8;
if (mode_rate_khz > supported_rate_khz) {
DP_DEBUG("mode_rate: %d kHz, supported_rate: %d kHz\n",

21
msm/dp/dp_panel.c
View file

@ -1180,8 +1180,11 @@ static void _dp_panel_dsc_bw_overhead_calc(struct dp_panel *dp_panel,
int tot_num_hor_bytes, tot_num_dummy_bytes;
int dwidth_dsc_bytes, eoc_bytes;
u32 num_lanes;
struct dp_panel_private *panel;
num_lanes = dp_panel->link_info.num_lanes;
panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
num_lanes = panel->link->link_params.lane_count;
num_slices = dsc->slice_per_pkt;
eoc_bytes = dsc_byte_cnt % num_lanes;
@ -1832,18 +1835,23 @@ end:
static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,
u32 mode_edid_bpp, u32 mode_pclk_khz)
{
struct drm_dp_link *link_info;
struct dp_link_params *link_params;
struct dp_panel_private *panel;
const u32 max_supported_bpp = 30;
u32 min_supported_bpp = 18;
u32 bpp = 0, data_rate_khz = 0;
panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
if (dp_panel->dsc_en)
min_supported_bpp = 24;
bpp = min_t(u32, mode_edid_bpp, max_supported_bpp);
link_info = &dp_panel->link_info;
data_rate_khz = link_info->num_lanes * link_info->rate * 8;
link_params = &panel->link->link_params;
data_rate_khz = link_params->lane_count *
drm_dp_bw_code_to_link_rate(link_params->bw_code) * 8;
for (; bpp > min_supported_bpp; bpp -= 6) {
if (dp_panel->dsc_en) {
@ -2620,8 +2628,9 @@ cached:
dp_panel_setup_dhdr_vsif(panel);
input.mdp_clk = core_clk_rate;
input.lclk = dp_panel->link_info.rate;
input.nlanes = dp_panel->link_info.num_lanes;
input.lclk = drm_dp_bw_code_to_link_rate(
panel->link->link_params.bw_code);
input.nlanes = panel->link->link_params.lane_count;
input.pclk = dp_panel->pinfo.pixel_clk_khz;
input.h_active = dp_panel->pinfo.h_active;
input.mst_target_sc = dp_panel->mst_target_sc;