From bd82334bfe25fe533a199177fd9c16f87f6ea82f Mon Sep 17 00:00:00 2001
From: Odelu Kukatla <okukatla@qti.qualcomm.com>
Date: Mon, 19 Apr 2021 17:19:55 +0530
Subject: [PATCH] ARM: dts: msm: update interconnect devices for Monaco

Update the interconnect devices for cnoc, snoc, bimc, clk_virt,
mmnrt_virt and mmrt_virt to enable the real interconenct devices.
This will allow consumers to get their path and set bandwidth
constraints on them.

Change-Id: Idc66b9971f9065d3fb0a990b1a8ebd2b15d108ba
---
 qcom/monaco.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index 3e9883ccbcad..83c6ad9cbbe5 100644
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -980,31 +980,60 @@
 	clk_virt: interconnect {
 		compatible = "qcom,monaco-clk_virt";
 		#interconnect-cells = <1>;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_QUP_CLK>,
+			<&rpmcc RPM_SMD_QUP_A_CLK>;
 	};
 
 	mmnrt_virt: interconnect@0 {
 		compatible = "qcom,monaco-mmnrt_virt";
 		#interconnect-cells = <1>;
+		qcom,util-factor = <142>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
+			<&rpmcc RPM_SMD_MMNRT_A_CLK>;
 	};
 
 	mmrt_virt: interconnect@1 {
 		compatible = "qcom,monaco-mmrt_virt";
 		#interconnect-cells = <1>;
+		qcom,util-factor = <142>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
+			<&rpmcc RPM_SMD_MMRT_A_CLK>;
 	};
 
 	system_noc: interconnect@1880000 {
+		reg = <0x01880000 0x5e200>;
 		compatible = "qcom,monaco-system_noc";
 		#interconnect-cells = <1>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+			<&rpmcc RPM_SMD_SNOC_A_CLK>;
 	};
 
 	config_noc: interconnect@1900000 {
+		reg = <0x01900000 0x1000>;
 		compatible = "qcom,monaco-config_noc";
 		#interconnect-cells = <1>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+			<&rpmcc RPM_SMD_CNOC_A_CLK>;
 	};
 
 	bimc: interconnect@4480000 {
+		reg = <0x04480000 0x80000>;
 		compatible = "qcom,monaco-bimc";
 		#interconnect-cells = <1>;
+		qcom,util-factor = <151>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+			<&rpmcc RPM_SMD_BIMC_A_CLK>;
 	};
 
 	rpm_bus: qcom,rpm-smd {