From bdcff7e7b9f22e66af8268c7d2ae16bd3d4ab63d Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Wed, 1 Jul 2020 10:49:17 -0700 Subject: [PATCH] ARM: dts: msm: Disable L1SS sleep for Lahaina Remove the software workaround to manually manage the phy PLL. Keep the phy PLL on all the time by disabling L1SS sleep. This is required to prevent PCIe link down issue upon exiting the L1SS sleep. Change-Id: I6251f05d1ae0572b958740460606e3eeb51c59ed --- qcom/lahaina-pcie.dtsi | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index fceeb83905f9..32f0dcd37949 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -101,6 +101,7 @@ qcom,boot-option = <0x1>; qcom,drv-supported; + qcom,l1ss-sleep-disable = <0x1>; qcom,drv-l1ss-timeout-us = <10000>; qcom,use-19p2mhz-aux-clk; qcom,no-l0s-supported; @@ -109,11 +110,6 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; - qcom,phy-manage-pll = <1>; - qcom,phy-resetsm-cntrl2 = <0xa0>; - qcom,phy-core-pll-en-mux = <7>; - qcom,phy-c-ready-status = <0x178>; - qcom,pcie-phy-ver = <10099>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>;