diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 906f11685d96..93709ab8e29b 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -56,6 +56,9 @@ SoCs: - SHIMA compatible = "qcom,shima" +- YUPIK + compatible = "qcom,yupik" + - LITO compatible = "qcom,lito" @@ -206,6 +209,7 @@ compatible = "qcom,shima-rumi" compatible = "qcom,shima-idp" compatible = "qcom,shima-atp" compatible = "qcom,shima-qrd" +compatible = "qcom,yupik-rumi" compatible = "qcom,lito-rumi" compatible = "qcom,lito-mtp" compatible = "qcom,lito-cdp" diff --git a/qcom/Makefile b/qcom/Makefile index 431e168ae8a3..1a1c6f058bd8 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -122,6 +122,15 @@ dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \ shima-idps-digital-mics.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_YUPIK) += \ + yupik-rumi-overlay.dtbo + +yupik-rumi-overlay.dtbo-base := yupik.dtb +else +dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SM8150) += \ sm8150-cdp-overlay.dtbo \ diff --git a/qcom/yupik-rumi-overlay.dts b/qcom/yupik-rumi-overlay.dts new file mode 100644 index 000000000000..45ef5d896d3f --- /dev/null +++ b/qcom/yupik-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik RUMI"; + compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi"; + qcom,msm-id = <475 0x10000>; + qcom,board-id = <0x1000f 0>; +}; diff --git a/qcom/yupik-rumi.dts b/qcom/yupik-rumi.dts new file mode 100644 index 000000000000..2085858de82d --- /dev/null +++ b/qcom/yupik-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "yupik.dtsi" +#include "yupik-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik RUMI"; + compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi"; + qcom,board-id = <0x1000f 0>; +}; diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi new file mode 100644 index 000000000000..0987448b8be5 --- /dev/null +++ b/qcom/yupik-rumi.dtsi @@ -0,0 +1,13 @@ +&soc { + timer { + clock-frequency = <5000000>; + }; + + timer@17c20000 { + clock-frequency = <5000000>; + }; + + wdog: qcom,wdt@17c10000 { + status = "disabled"; + }; +}; diff --git a/qcom/yupik.dts b/qcom/yupik.dts new file mode 100644 index 000000000000..07edde8dc0a5 --- /dev/null +++ b/qcom/yupik.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "yupik.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik SoC"; + compatible = "qcom,yupik"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi new file mode 100644 index 000000000000..835fff7b0b00 --- /dev/null +++ b/qcom/yupik.dtsi @@ -0,0 +1,266 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Yupik"; + compatible = "qcom,yupik"; + qcom,msm-id = <475 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + aliases { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + }; + + cluster2 { + + core0 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; + + chosen { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; +};