mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
x86/mce/AMD, EDAC: Enable error decoding of Scalable MCA errors
For Scalable MCA enabled processors, errors are listed per IP block. And since it is not required for an IP to map to a particular bank, we need to use HWID and McaType values from the MCx_IPID register to figure out which IP a given bank represents. We also have a new bit (TCC) in the MCx_STATUS register to indicate Task context is corrupt. Add logic here to decode errors from all known IP blocks for Fam17h Model 00-0fh and to print TCC errors. [ Minor fixups. ] Signed-off-by: Aravind Gopalakrishnan <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Tony Luck <[email protected]> Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
This commit is contained in:
Aravind Gopalakrishnan
Ingo Molnar
parent
adc53f2e0a
commit
be0aec23bf
3 changed files with 420 additions and 3 deletions
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@ -147,6 +147,135 @@ static const char * const mc6_mce_desc[] = {
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"Status Register File",
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};
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/* Scalable MCA error strings */
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static const char * const f17h_ls_mce_desc[] = {
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"Load queue parity",
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"Store queue parity",
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"Miss address buffer payload parity",
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"L1 TLB parity",
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"", /* reserved */
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"DC tag error type 6",
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"DC tag error type 1",
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"Internal error type 1",
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"Internal error type 2",
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"Sys Read data error thread 0",
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"Sys read data error thread 1",
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"DC tag error type 2",
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"DC data error type 1 (poison comsumption)",
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"DC data error type 2",
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"DC data error type 3",
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"DC tag error type 4",
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"L2 TLB parity",
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"PDC parity error",
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"DC tag error type 3",
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"DC tag error type 5",
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"L2 fill data error",
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};
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static const char * const f17h_if_mce_desc[] = {
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"microtag probe port parity error",
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"IC microtag or full tag multi-hit error",
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"IC full tag parity",
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"IC data array parity",
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"Decoupling queue phys addr parity error",
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"L0 ITLB parity error",
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"L1 ITLB parity error",
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"L2 ITLB parity error",
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"BPQ snoop parity on Thread 0",
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"BPQ snoop parity on Thread 1",
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"L1 BTB multi-match error",
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"L2 BTB multi-match error",
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};
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static const char * const f17h_l2_mce_desc[] = {
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"L2M tag multi-way-hit error",
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"L2M tag ECC error",
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"L2M data ECC error",
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"HW assert",
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};
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static const char * const f17h_de_mce_desc[] = {
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"uop cache tag parity error",
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"uop cache data parity error",
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"Insn buffer parity error",
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"Insn dispatch queue parity error",
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"Fetch address FIFO parity",
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"Patch RAM data parity",
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"Patch RAM sequencer parity",
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"uop buffer parity"
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};
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static const char * const f17h_ex_mce_desc[] = {
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"Watchdog timeout error",
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"Phy register file parity",
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"Flag register file parity",
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"Immediate displacement register file parity",
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"Address generator payload parity",
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"EX payload parity",
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"Checkpoint queue parity",
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"Retire dispatch queue parity",
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};
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static const char * const f17h_fp_mce_desc[] = {
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"Physical register file parity",
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"Freelist parity error",
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"Schedule queue parity",
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"NSQ parity error",
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"Retire queue parity",
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"Status register file parity",
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};
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static const char * const f17h_l3_mce_desc[] = {
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"Shadow tag macro ECC error",
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"Shadow tag macro multi-way-hit error",
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"L3M tag ECC error",
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"L3M tag multi-way-hit error",
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"L3M data ECC error",
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"XI parity, L3 fill done channel error",
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"L3 victim queue parity",
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"L3 HW assert",
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};
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static const char * const f17h_cs_mce_desc[] = {
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"Illegal request from transport layer",
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"Address violation",
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"Security violation",
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"Illegal response from transport layer",
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"Unexpected response",
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"Parity error on incoming request or probe response data",
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"Parity error on incoming read response data",
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"Atomic request parity",
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"ECC error on probe filter access",
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};
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static const char * const f17h_pie_mce_desc[] = {
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"HW assert",
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"Internal PIE register security violation",
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"Error on GMI link",
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"Poison data written to internal PIE register",
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};
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static const char * const f17h_umc_mce_desc[] = {
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"DRAM ECC error",
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"Data poison error on DRAM",
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"SDP parity error",
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"Advanced peripheral bus error",
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"Command/address parity error",
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"Write data CRC error",
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};
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static const char * const f17h_pb_mce_desc[] = {
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"Parameter Block RAM ECC error",
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};
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static const char * const f17h_psp_mce_desc[] = {
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"PSP RAM ECC or parity error",
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};
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static const char * const f17h_smu_mce_desc[] = {
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"SMU RAM ECC or parity error",
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};
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static bool f12h_mc0_mce(u16 ec, u8 xec)
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{
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bool ret = false;
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@ -691,6 +820,177 @@ static void decode_mc6_mce(struct mce *m)
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pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
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}
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static void decode_f17h_core_errors(const char *ip_name, u8 xec,
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unsigned int mca_type)
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{
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const char * const *error_desc_array;
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size_t len;
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pr_emerg(HW_ERR "%s Error: ", ip_name);
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switch (mca_type) {
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case SMCA_LS:
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error_desc_array = f17h_ls_mce_desc;
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len = ARRAY_SIZE(f17h_ls_mce_desc) - 1;
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if (xec == 0x4) {
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pr_cont("Unrecognized LS MCA error code.\n");
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return;
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}
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break;
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case SMCA_IF:
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error_desc_array = f17h_if_mce_desc;
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len = ARRAY_SIZE(f17h_if_mce_desc) - 1;
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break;
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case SMCA_L2_CACHE:
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error_desc_array = f17h_l2_mce_desc;
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len = ARRAY_SIZE(f17h_l2_mce_desc) - 1;
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break;
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case SMCA_DE:
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error_desc_array = f17h_de_mce_desc;
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len = ARRAY_SIZE(f17h_de_mce_desc) - 1;
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break;
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case SMCA_EX:
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error_desc_array = f17h_ex_mce_desc;
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len = ARRAY_SIZE(f17h_ex_mce_desc) - 1;
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break;
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case SMCA_FP:
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error_desc_array = f17h_fp_mce_desc;
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len = ARRAY_SIZE(f17h_fp_mce_desc) - 1;
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break;
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case SMCA_L3_CACHE:
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error_desc_array = f17h_l3_mce_desc;
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len = ARRAY_SIZE(f17h_l3_mce_desc) - 1;
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break;
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default:
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pr_cont("Corrupted MCA core error info.\n");
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return;
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}
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if (xec > len) {
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pr_cont("Unrecognized %s MCA bank error code.\n",
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amd_core_mcablock_names[mca_type]);
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return;
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}
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pr_cont("%s.\n", error_desc_array[xec]);
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}
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static void decode_df_errors(u8 xec, unsigned int mca_type)
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{
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const char * const *error_desc_array;
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size_t len;
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pr_emerg(HW_ERR "Data Fabric Error: ");
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switch (mca_type) {
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case SMCA_CS:
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error_desc_array = f17h_cs_mce_desc;
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len = ARRAY_SIZE(f17h_cs_mce_desc) - 1;
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break;
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case SMCA_PIE:
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error_desc_array = f17h_pie_mce_desc;
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len = ARRAY_SIZE(f17h_pie_mce_desc) - 1;
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break;
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default:
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pr_cont("Corrupted MCA Data Fabric info.\n");
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return;
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}
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if (xec > len) {
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pr_cont("Unrecognized %s MCA bank error code.\n",
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amd_df_mcablock_names[mca_type]);
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return;
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}
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pr_cont("%s.\n", error_desc_array[xec]);
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}
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/* Decode errors according to Scalable MCA specification */
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static void decode_smca_errors(struct mce *m)
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{
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u32 addr = MSR_AMD64_SMCA_MCx_IPID(m->bank);
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unsigned int hwid, mca_type, i;
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u8 xec = XEC(m->status, xec_mask);
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const char * const *error_desc_array;
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const char *ip_name;
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u32 low, high;
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size_t len;
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if (rdmsr_safe(addr, &low, &high)) {
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pr_emerg("Invalid IP block specified, error information is unreliable.\n");
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return;
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}
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hwid = high & MCI_IPID_HWID;
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mca_type = (high & MCI_IPID_MCATYPE) >> 16;
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pr_emerg(HW_ERR "MC%d IPID value: 0x%08x%08x\n", m->bank, high, low);
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/*
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* Based on hwid and mca_type values, decode errors from respective IPs.
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* Note: mca_type values make sense only in the context of an hwid.
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*/
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for (i = 0; i < ARRAY_SIZE(amd_hwids); i++)
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if (amd_hwids[i].hwid == hwid)
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break;
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switch (i) {
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case SMCA_F17H_CORE:
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ip_name = (mca_type == SMCA_L3_CACHE) ?
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"L3 Cache" : "F17h Core";
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return decode_f17h_core_errors(ip_name, xec, mca_type);
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break;
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case SMCA_DF:
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return decode_df_errors(xec, mca_type);
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break;
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case SMCA_UMC:
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error_desc_array = f17h_umc_mce_desc;
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len = ARRAY_SIZE(f17h_umc_mce_desc) - 1;
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break;
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case SMCA_PB:
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error_desc_array = f17h_pb_mce_desc;
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len = ARRAY_SIZE(f17h_pb_mce_desc) - 1;
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break;
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case SMCA_PSP:
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error_desc_array = f17h_psp_mce_desc;
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len = ARRAY_SIZE(f17h_psp_mce_desc) - 1;
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break;
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case SMCA_SMU:
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error_desc_array = f17h_smu_mce_desc;
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len = ARRAY_SIZE(f17h_smu_mce_desc) - 1;
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break;
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default:
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pr_emerg(HW_ERR "HWID:%d does not match any existing IPs.\n", hwid);
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return;
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}
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ip_name = amd_hwids[i].name;
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pr_emerg(HW_ERR "%s Error: ", ip_name);
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if (xec > len) {
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pr_cont("Unrecognized %s MCA bank error code.\n", ip_name);
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return;
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}
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pr_cont("%s.\n", error_desc_array[xec]);
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}
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static inline void amd_decode_err_code(u16 ec)
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{
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if (INT_ERROR(ec)) {
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@ -752,6 +1052,7 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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struct mce *m = (struct mce *)data;
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struct cpuinfo_x86 *c = &cpu_data(m->extcpu);
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int ecc;
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u32 ebx = cpuid_ebx(0x80000007);
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if (amd_filter_mce(m))
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return NOTIFY_STOP;
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@ -769,11 +1070,20 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
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((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
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if (c->x86 == 0x15 || c->x86 == 0x16)
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if (c->x86 >= 0x15)
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pr_cont("|%s|%s",
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((m->status & MCI_STATUS_DEFERRED) ? "Deferred" : "-"),
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((m->status & MCI_STATUS_POISON) ? "Poison" : "-"));
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if (!!(ebx & BIT(3))) {
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u32 low, high;
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u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
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if (!rdmsr_safe(addr, &low, &high) &&
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(low & MCI_CONFIG_MCAX))
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pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
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}
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/* do the two bits[14:13] together */
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ecc = (m->status >> 45) & 0x3;
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if (ecc)
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@ -784,6 +1094,11 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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if (m->status & MCI_STATUS_ADDRV)
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pr_emerg(HW_ERR "MC%d Error Address: 0x%016llx\n", m->bank, m->addr);
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if (!!(ebx & BIT(3))) {
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decode_smca_errors(m);
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goto err_code;
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}
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if (!fam_ops)
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goto err_code;
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@ -834,6 +1149,7 @@ static struct notifier_block amd_mce_dec_nb = {
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static int __init mce_amd_init(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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u32 ebx;
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if (c->x86_vendor != X86_VENDOR_AMD)
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return -ENODEV;
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@ -888,10 +1204,18 @@ static int __init mce_amd_init(void)
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fam_ops->mc2_mce = f16h_mc2_mce;
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break;
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case 0x17:
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ebx = cpuid_ebx(0x80000007);
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xec_mask = 0x3f;
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if (!(ebx & BIT(3))) {
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printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
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goto err_out;
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}
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break;
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default:
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printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
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kfree(fam_ops);
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fam_ops = NULL;
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goto err_out;
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}
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pr_info("MCE: In-kernel MCE decoding enabled.\n");
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@ -899,6 +1223,11 @@ static int __init mce_amd_init(void)
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mce_register_decode_chain(&amd_mce_dec_nb);
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return 0;
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err_out:
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kfree(fam_ops);
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fam_ops = NULL;
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return -EINVAL;
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}
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early_initcall(mce_amd_init);
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