mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 13:44:26 -04:00
drm main pull request for v5.3-rc1 (sans mm changes)
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdLMSbAAoJEAx081l5xIa+udkP/iWr8mw44tWYb8Wuzc/aR91v 02X/J4S9XTQttNn/1Gpq9ItTLMf0Gc08tk1wEBBHAWi/qGaGZS2al+rv0afeuuQa aFhQzioDi7K/YZt92iEJhdx7wVMyydICTg3INmYlSP7/FyzLp6gBQRGSJ1kX5mHZ qWsFZgUOH9V5evyB6fDMleDaqFOKfcwrD7XYwbOheL/HeYQSv5AYn3VBupBFQ76L 0hclI5VzZQ5V0nnqRTNDQVA9Yl6NTl+2eXTn5vuBtwKXEI6JJw8eihZp2oZDXqfS L441w7wGbkRPzN5kjMZjs1ToPMTlMveR5kL6Sc+o3DT/HmIr1odeaSDXR/93UOLd z0CRJ6xMC8h1ThLNHp8UgbxCKqIwYPsY2wVqjsJt7lDY5jma7Yv2YJ9ocYGHN/sO DVHcU6ugbwvuC5wZZtVZl5J4hjnBZwNRGSVK+iM0tkjalgdEuSFehXT7eQ8SphF/ yI5gD1xNEwGfZ4bvZ3u/QrDCcpUAgPIUYmxEa2tPJILQWOJ9O87yc0y9Z21k9Ef1 9yDqrFV3sPqC2xj/0ufZG/18+Yt99Ykg1jQE3RGDwD/59KAeqPbOvqTKyVODV9jE qje6ScSIc2G0713uss2bcaD3k+rCB5YL2JkKrk5OWW/T2+n9T+JFaiNh7dnSFFcU gBKyeY24OyCDMwXrby0K =SI+Y -----END PGP SIGNATURE----- Merge tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "The biggest thing in this is the AMD Navi GPU support, this again contains a bunch of header files that are large. These are the new AMD RX5700 GPUs that just recently became available. New drivers: - ST-Ericsson MCDE driver - Ingenic JZ47xx SoC UAPI change: - HDR source metadata property Core: - HDR inforframes and EDID parsing - drm hdmi infoframe unpacking - remove prime sg_table caching into dma-buf - New gem vram helpers to reduce driver code - Lots of drmP.h removal - reservation fencing fix - documentation updates - drm_fb_helper_connector removed - mode name command handler rewrite fbcon: - Remove the fbcon notifiers ttm: - forward progress fixes dma-buf: - make mmap call optional - debugfs refcount fixes - dma-fence free with pending signals fix - each dma-buf gets an inode Panels: - Lots of additional panel bindings amdgpu: - initial navi10 support - avoid hw reset - HDR metadata support - new thermal sensors for vega asics - RAS fixes - use HMM rather than MMU notifier - xgmi topology via kfd - SR-IOV fixes - driver reload fixes - DC use a core bpc attribute - Aux fixes for DC - Bandwidth calc updates for DC - Clock handling refactor - kfd VEGAM support vmwgfx: - Coherent memory support changes i915: - HDR Support - HDMI i2c link - Icelake multi-segmented gamma support - GuC firmware update - Mule Creek Canyon PCH support for EHL - EHL platform updtes - move i915.alpha_support to i915.force_probe - runtime PM refactoring - VBT parsing refactoring - DSI fixes - struct mutex dependency reduction - GEM code reorg mali-dp: - Komeda driver features msm: - dsi vs EPROBE_DEFER fixes - msm8998 snapdragon 835 support - a540 gpu support - mdp5 and dpu interconnect support exynos: - drmP.h removal tegra: - misc fixes tda998x: - audio support improvements - pixel repeated mode support - quantisation range handling corrections - HDMI vendor info fix armada: - interlace support fix - overlay/video plane register handling refactor - add gamma support rockchip: - RX3328 support panfrost: - expose perf counters via hidden ioctls vkms: - enumerate CRC sources list ast: - rework BO handling mgag200: - rework BO handling dw-hdmi: - suspend/resume support rcar-du: - R8A774A1 Soc Support - LVDS dual-link mode support - Additional formats - Misc fixes omapdrm: - DSI command mode display support stm - fb modifier support - runtime PM support sun4i: - use vmap ops vc4: - binner bo binding rework v3d: - compute shader support - resync/sync fixes - job management refactoring lima: - NULL pointer in irq handler fix - scheduler default timeout virtio: - fence seqno support - trace events bochs: - misc fixes tc458767: - IRQ/HDP handling sii902x: - HDMI audio support atmel-hlcdc: - misc fixes meson: - zpos support" * tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm: (1815 commits) Revert "Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-next" Revert "mm: adjust apply_to_pfn_range interface for dropped token." mm: adjust apply_to_pfn_range interface for dropped token. drm/amdgpu/navi10: add uclk activity sensor drm/amdgpu: properly guard the generic discovery code drm/amdgpu: add missing documentation on new module parameters drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback drm/amd/display: avoid 64-bit division drm/amdgpu/psp11: simplify the ucode register logic drm/amdgpu: properly guard DC support in navi code drm/amd/powerplay: vega20: fix uninitialized variable use drm/amd/display: dcn20: include linux/delay.h amdgpu: make pmu support optional drm/amd/powerplay: Zero initialize current_rpm in vega20_get_fan_speed_percent drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freq drm/amd/powerplay: Use memset to initialize metrics structs drm/amdgpu/mes10.1: Fix header guard drm/amd/powerplay: add temperature sensor support for navi10 drm/amdgpu: fix scheduler timeout calc drm/amdgpu: Prepare for hmm_range_register API change (v2) ...
This commit is contained in:
Linus Torvalds
commit
be8454afc5
1567 changed files with 475671 additions and 34502 deletions
|
|
@ -912,6 +912,7 @@ struct drm_amdgpu_info_firmware {
|
|||
#define AMDGPU_VRAM_TYPE_HBM 6
|
||||
#define AMDGPU_VRAM_TYPE_DDR3 7
|
||||
#define AMDGPU_VRAM_TYPE_DDR4 8
|
||||
#define AMDGPU_VRAM_TYPE_GDDR6 9
|
||||
|
||||
struct drm_amdgpu_info_device {
|
||||
/** PCI Device ID */
|
||||
|
|
@ -991,6 +992,8 @@ struct drm_amdgpu_info_device {
|
|||
__u64 high_va_offset;
|
||||
/** The maximum high virtual address */
|
||||
__u64 high_va_max;
|
||||
/* gfx10 pa_sc_tile_steering_override */
|
||||
__u32 pa_sc_tile_steering_override;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_hw_ip {
|
||||
|
|
@ -1044,6 +1047,7 @@ struct drm_amdgpu_info_vce_clock_table {
|
|||
#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
|
||||
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
|
||||
#define AMDGPU_FAMILY_RV 142 /* Raven */
|
||||
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ typedef unsigned int drm_handle_t;
|
|||
|
||||
#else /* One of the BSDs */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <sys/ioccom.h>
|
||||
#include <sys/types.h>
|
||||
typedef int8_t __s8;
|
||||
|
|
|
|||
|
|
@ -33,6 +33,15 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* DOC: overview
|
||||
*
|
||||
* DRM exposes many UAPI and structure definition to have a consistent
|
||||
* and standardized interface with user.
|
||||
* Userspace can refer to these structure definitions and UAPI formats
|
||||
* to communicate to driver
|
||||
*/
|
||||
|
||||
#define DRM_CONNECTOR_NAME_LEN 32
|
||||
#define DRM_DISPLAY_MODE_LEN 32
|
||||
#define DRM_PROP_NAME_LEN 32
|
||||
|
|
@ -630,6 +639,92 @@ struct drm_color_lut {
|
|||
__u16 reserved;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hdr_metadata_infoframe - HDR Metadata Infoframe Data.
|
||||
*
|
||||
* HDR Metadata Infoframe as per CTA 861.G spec. This is expected
|
||||
* to match exactly with the spec.
|
||||
*
|
||||
* Userspace is expected to pass the metadata information as per
|
||||
* the format described in this structure.
|
||||
*/
|
||||
struct hdr_metadata_infoframe {
|
||||
/**
|
||||
* @eotf: Electro-Optical Transfer Function (EOTF)
|
||||
* used in the stream.
|
||||
*/
|
||||
__u8 eotf;
|
||||
/**
|
||||
* @metadata_type: Static_Metadata_Descriptor_ID.
|
||||
*/
|
||||
__u8 metadata_type;
|
||||
/**
|
||||
* @display_primaries: Color Primaries of the Data.
|
||||
* These are coded as unsigned 16-bit values in units of
|
||||
* 0.00002, where 0x0000 represents zero and 0xC350
|
||||
* represents 1.0000.
|
||||
* @display_primaries.x: X cordinate of color primary.
|
||||
* @display_primaries.y: Y cordinate of color primary.
|
||||
*/
|
||||
struct {
|
||||
__u16 x, y;
|
||||
} display_primaries[3];
|
||||
/**
|
||||
* @white_point: White Point of Colorspace Data.
|
||||
* These are coded as unsigned 16-bit values in units of
|
||||
* 0.00002, where 0x0000 represents zero and 0xC350
|
||||
* represents 1.0000.
|
||||
* @white_point.x: X cordinate of whitepoint of color primary.
|
||||
* @white_point.y: Y cordinate of whitepoint of color primary.
|
||||
*/
|
||||
struct {
|
||||
__u16 x, y;
|
||||
} white_point;
|
||||
/**
|
||||
* @max_display_mastering_luminance: Max Mastering Display Luminance.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
__u16 max_display_mastering_luminance;
|
||||
/**
|
||||
* @min_display_mastering_luminance: Min Mastering Display Luminance.
|
||||
* This value is coded as an unsigned 16-bit value in units of
|
||||
* 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF
|
||||
* represents 6.5535 cd/m2.
|
||||
*/
|
||||
__u16 min_display_mastering_luminance;
|
||||
/**
|
||||
* @max_cll: Max Content Light Level.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
__u16 max_cll;
|
||||
/**
|
||||
* @max_fall: Max Frame Average Light Level.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
__u16 max_fall;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hdr_output_metadata - HDR output metadata
|
||||
*
|
||||
* Metadata Information to be passed from userspace
|
||||
*/
|
||||
struct hdr_output_metadata {
|
||||
/**
|
||||
* @metadata_type: Static_Metadata_Descriptor_ID.
|
||||
*/
|
||||
__u32 metadata_type;
|
||||
/**
|
||||
* @hdmi_metadata_type1: HDR Metadata Infoframe.
|
||||
*/
|
||||
union {
|
||||
struct hdr_metadata_infoframe hdmi_metadata_type1;
|
||||
};
|
||||
};
|
||||
|
||||
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
|
||||
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
|
||||
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
|
||||
|
|
@ -803,6 +898,10 @@ struct drm_format_modifier {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_create_blob - Create New block property
|
||||
* @data: Pointer to data to copy.
|
||||
* @length: Length of data to copy.
|
||||
* @blob_id: new property ID.
|
||||
* Create a new 'blob' data property, copying length bytes from data pointer,
|
||||
* and returning new blob ID.
|
||||
*/
|
||||
|
|
@ -816,6 +915,8 @@ struct drm_mode_create_blob {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_destroy_blob - Destroy user blob
|
||||
* @blob_id: blob_id to destroy
|
||||
* Destroy a user-created blob property.
|
||||
*/
|
||||
struct drm_mode_destroy_blob {
|
||||
|
|
@ -823,6 +924,12 @@ struct drm_mode_destroy_blob {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_create_lease - Create lease
|
||||
* @object_ids: Pointer to array of object ids.
|
||||
* @object_count: Number of object ids.
|
||||
* @flags: flags for new FD.
|
||||
* @lessee_id: unique identifier for lessee.
|
||||
* @fd: file descriptor to new drm_master file.
|
||||
* Lease mode resources, creating another drm_master.
|
||||
*/
|
||||
struct drm_mode_create_lease {
|
||||
|
|
@ -840,6 +947,10 @@ struct drm_mode_create_lease {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_list_lessees - List lessees
|
||||
* @count_lessees: Number of lessees.
|
||||
* @pad: pad.
|
||||
* @lessees_ptr: Pointer to lessess.
|
||||
* List lesses from a drm_master
|
||||
*/
|
||||
struct drm_mode_list_lessees {
|
||||
|
|
@ -860,6 +971,10 @@ struct drm_mode_list_lessees {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_get_lease - Get Lease
|
||||
* @count_objects: Number of leased objects.
|
||||
* @pad: pad.
|
||||
* @objects_ptr: Pointer to objects.
|
||||
* Get leased objects
|
||||
*/
|
||||
struct drm_mode_get_lease {
|
||||
|
|
@ -880,6 +995,8 @@ struct drm_mode_get_lease {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_revoke_lease - Revoke lease
|
||||
* @lessee_id: Unique ID of lessee.
|
||||
* Revoke lease
|
||||
*/
|
||||
struct drm_mode_revoke_lease {
|
||||
|
|
|
|||
|
|
@ -136,6 +136,8 @@ enum drm_i915_gem_engine_class {
|
|||
struct i915_engine_class_instance {
|
||||
__u16 engine_class; /* see enum drm_i915_gem_engine_class */
|
||||
__u16 engine_instance;
|
||||
#define I915_ENGINE_CLASS_INVALID_NONE -1
|
||||
#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -355,6 +357,8 @@ typedef struct _drm_i915_sarea {
|
|||
#define DRM_I915_PERF_ADD_CONFIG 0x37
|
||||
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
|
||||
#define DRM_I915_QUERY 0x39
|
||||
#define DRM_I915_GEM_VM_CREATE 0x3a
|
||||
#define DRM_I915_GEM_VM_DESTROY 0x3b
|
||||
/* Must be kept compact -- no holes */
|
||||
|
||||
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
|
||||
|
|
@ -415,6 +419,8 @@ typedef struct _drm_i915_sarea {
|
|||
#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
|
||||
#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
|
||||
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
|
||||
#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
|
||||
#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
|
||||
|
||||
/* Allow drivers to submit batchbuffers directly to hardware, relying
|
||||
* on the security mechanisms provided by hardware.
|
||||
|
|
@ -598,6 +604,12 @@ typedef struct drm_i915_irq_wait {
|
|||
*/
|
||||
#define I915_PARAM_MMAP_GTT_COHERENT 52
|
||||
|
||||
/*
|
||||
* Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
|
||||
* execution through use of explicit fence support.
|
||||
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
|
||||
*/
|
||||
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
|
|
@ -1120,7 +1132,16 @@ struct drm_i915_gem_execbuffer2 {
|
|||
*/
|
||||
#define I915_EXEC_FENCE_ARRAY (1<<19)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
|
||||
/*
|
||||
* Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
|
||||
* a sync_file fd to wait upon (in a nonblocking manner) prior to executing
|
||||
* the batch.
|
||||
*
|
||||
* Returns -EINVAL if the sync_file fd cannot be found.
|
||||
*/
|
||||
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
|
||||
|
||||
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
|
||||
#define i915_execbuffer2_set_context_id(eb2, context) \
|
||||
|
|
@ -1464,8 +1485,9 @@ struct drm_i915_gem_context_create_ext {
|
|||
__u32 ctx_id; /* output: id of new context*/
|
||||
__u32 flags;
|
||||
#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
|
||||
#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
|
||||
#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
|
||||
(-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
|
||||
(-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
|
||||
__u64 extensions;
|
||||
};
|
||||
|
||||
|
|
@ -1507,6 +1529,41 @@ struct drm_i915_gem_context_param {
|
|||
* On creation, all new contexts are marked as recoverable.
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
|
||||
|
||||
/*
|
||||
* The id of the associated virtual memory address space (ppGTT) of
|
||||
* this context. Can be retrieved and passed to another context
|
||||
* (on the same fd) for both to use the same ppGTT and so share
|
||||
* address layouts, and avoid reloading the page tables on context
|
||||
* switches between themselves.
|
||||
*
|
||||
* See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_VM 0x9
|
||||
|
||||
/*
|
||||
* I915_CONTEXT_PARAM_ENGINES:
|
||||
*
|
||||
* Bind this context to operate on this subset of available engines. Henceforth,
|
||||
* the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
|
||||
* an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
|
||||
* and upwards. Slots 0...N are filled in using the specified (class, instance).
|
||||
* Use
|
||||
* engine_class: I915_ENGINE_CLASS_INVALID,
|
||||
* engine_instance: I915_ENGINE_CLASS_INVALID_NONE
|
||||
* to specify a gap in the array that can be filled in later, e.g. by a
|
||||
* virtual engine used for load balancing.
|
||||
*
|
||||
* Setting the number of engines bound to the context to 0, by passing a zero
|
||||
* sized argument, will revert back to default settings.
|
||||
*
|
||||
* See struct i915_context_param_engines.
|
||||
*
|
||||
* Extensions:
|
||||
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
|
||||
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_ENGINES 0xa
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
__u64 value;
|
||||
|
|
@ -1540,9 +1597,10 @@ struct drm_i915_gem_context_param_sseu {
|
|||
struct i915_engine_class_instance engine;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
* Unknown flags must be cleared to zero.
|
||||
*/
|
||||
__u32 flags;
|
||||
#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
|
||||
|
||||
/*
|
||||
* Mask of slices to enable for the context. Valid values are a subset
|
||||
|
|
@ -1570,12 +1628,115 @@ struct drm_i915_gem_context_param_sseu {
|
|||
__u32 rsvd;
|
||||
};
|
||||
|
||||
/*
|
||||
* i915_context_engines_load_balance:
|
||||
*
|
||||
* Enable load balancing across this set of engines.
|
||||
*
|
||||
* Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
|
||||
* used will proxy the execbuffer request onto one of the set of engines
|
||||
* in such a way as to distribute the load evenly across the set.
|
||||
*
|
||||
* The set of engines must be compatible (e.g. the same HW class) as they
|
||||
* will share the same logical GPU context and ring.
|
||||
*
|
||||
* To intermix rendering with the virtual engine and direct rendering onto
|
||||
* the backing engines (bypassing the load balancing proxy), the context must
|
||||
* be defined to use a single timeline for all engines.
|
||||
*/
|
||||
struct i915_context_engines_load_balance {
|
||||
struct i915_user_extension base;
|
||||
|
||||
__u16 engine_index;
|
||||
__u16 num_siblings;
|
||||
__u32 flags; /* all undefined flags must be zero */
|
||||
|
||||
__u64 mbz64; /* reserved for future use; must be zero */
|
||||
|
||||
struct i915_engine_class_instance engines[0];
|
||||
} __attribute__((packed));
|
||||
|
||||
#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
|
||||
struct i915_user_extension base; \
|
||||
__u16 engine_index; \
|
||||
__u16 num_siblings; \
|
||||
__u32 flags; \
|
||||
__u64 mbz64; \
|
||||
struct i915_engine_class_instance engines[N__]; \
|
||||
} __attribute__((packed)) name__
|
||||
|
||||
/*
|
||||
* i915_context_engines_bond:
|
||||
*
|
||||
* Constructed bonded pairs for execution within a virtual engine.
|
||||
*
|
||||
* All engines are equal, but some are more equal than others. Given
|
||||
* the distribution of resources in the HW, it may be preferable to run
|
||||
* a request on a given subset of engines in parallel to a request on a
|
||||
* specific engine. We enable this selection of engines within a virtual
|
||||
* engine by specifying bonding pairs, for any given master engine we will
|
||||
* only execute on one of the corresponding siblings within the virtual engine.
|
||||
*
|
||||
* To execute a request in parallel on the master engine and a sibling requires
|
||||
* coordination with a I915_EXEC_FENCE_SUBMIT.
|
||||
*/
|
||||
struct i915_context_engines_bond {
|
||||
struct i915_user_extension base;
|
||||
|
||||
struct i915_engine_class_instance master;
|
||||
|
||||
__u16 virtual_index; /* index of virtual engine in ctx->engines[] */
|
||||
__u16 num_bonds;
|
||||
|
||||
__u64 flags; /* all undefined flags must be zero */
|
||||
__u64 mbz64[4]; /* reserved for future use; must be zero */
|
||||
|
||||
struct i915_engine_class_instance engines[0];
|
||||
} __attribute__((packed));
|
||||
|
||||
#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
|
||||
struct i915_user_extension base; \
|
||||
struct i915_engine_class_instance master; \
|
||||
__u16 virtual_index; \
|
||||
__u16 num_bonds; \
|
||||
__u64 flags; \
|
||||
__u64 mbz64[4]; \
|
||||
struct i915_engine_class_instance engines[N__]; \
|
||||
} __attribute__((packed)) name__
|
||||
|
||||
struct i915_context_param_engines {
|
||||
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
|
||||
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
|
||||
#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
|
||||
struct i915_engine_class_instance engines[0];
|
||||
} __attribute__((packed));
|
||||
|
||||
#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
|
||||
__u64 extensions; \
|
||||
struct i915_engine_class_instance engines[N__]; \
|
||||
} __attribute__((packed)) name__
|
||||
|
||||
struct drm_i915_gem_context_create_ext_setparam {
|
||||
#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
|
||||
struct i915_user_extension base;
|
||||
struct drm_i915_gem_context_param param;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_create_ext_clone {
|
||||
#define I915_CONTEXT_CREATE_EXT_CLONE 1
|
||||
struct i915_user_extension base;
|
||||
__u32 clone_id;
|
||||
__u32 flags;
|
||||
#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
|
||||
#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
|
||||
#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
|
||||
#define I915_CONTEXT_CLONE_SSEU (1u << 3)
|
||||
#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
|
||||
#define I915_CONTEXT_CLONE_VM (1u << 5)
|
||||
#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
|
||||
__u64 rsvd;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_destroy {
|
||||
__u32 ctx_id;
|
||||
__u32 pad;
|
||||
|
|
@ -1821,6 +1982,7 @@ struct drm_i915_perf_oa_config {
|
|||
struct drm_i915_query_item {
|
||||
__u64 query_id;
|
||||
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
|
||||
#define DRM_I915_QUERY_ENGINE_INFO 2
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
/*
|
||||
|
|
@ -1919,6 +2081,47 @@ struct drm_i915_query_topology_info {
|
|||
__u8 data[];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_i915_engine_info
|
||||
*
|
||||
* Describes one engine and it's capabilities as known to the driver.
|
||||
*/
|
||||
struct drm_i915_engine_info {
|
||||
/** Engine class and instance. */
|
||||
struct i915_engine_class_instance engine;
|
||||
|
||||
/** Reserved field. */
|
||||
__u32 rsvd0;
|
||||
|
||||
/** Engine flags. */
|
||||
__u64 flags;
|
||||
|
||||
/** Capabilities of this engine. */
|
||||
__u64 capabilities;
|
||||
#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
|
||||
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
|
||||
|
||||
/** Reserved fields. */
|
||||
__u64 rsvd1[4];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_i915_query_engine_info
|
||||
*
|
||||
* Engine info query enumerates all engines known to the driver by filling in
|
||||
* an array of struct drm_i915_engine_info structures.
|
||||
*/
|
||||
struct drm_i915_query_engine_info {
|
||||
/** Number of struct drm_i915_engine_info structs following. */
|
||||
__u32 num_engines;
|
||||
|
||||
/** MBZ */
|
||||
__u32 rsvd[3];
|
||||
|
||||
/** Marker for drm_i915_engine_info structures. */
|
||||
struct drm_i915_engine_info engines[];
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@ extern "C" {
|
|||
#define DRM_PANFROST_MMAP_BO 0x03
|
||||
#define DRM_PANFROST_GET_PARAM 0x04
|
||||
#define DRM_PANFROST_GET_BO_OFFSET 0x05
|
||||
#define DRM_PANFROST_PERFCNT_ENABLE 0x06
|
||||
#define DRM_PANFROST_PERFCNT_DUMP 0x07
|
||||
|
||||
#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
|
||||
#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
|
||||
|
|
@ -26,6 +28,15 @@ extern "C" {
|
|||
#define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param)
|
||||
#define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset)
|
||||
|
||||
/*
|
||||
* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module
|
||||
* param is set to true.
|
||||
* All these ioctl(s) are subject to deprecation, so please don't rely on
|
||||
* them for anything but debugging purpose.
|
||||
*/
|
||||
#define DRM_IOCTL_PANFROST_PERFCNT_ENABLE DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable)
|
||||
#define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, struct drm_panfrost_perfcnt_dump)
|
||||
|
||||
#define PANFROST_JD_REQ_FS (1 << 0)
|
||||
/**
|
||||
* struct drm_panfrost_submit - ioctl argument for submitting commands to the 3D
|
||||
|
|
@ -135,6 +146,19 @@ struct drm_panfrost_get_bo_offset {
|
|||
__u64 offset;
|
||||
};
|
||||
|
||||
struct drm_panfrost_perfcnt_enable {
|
||||
__u32 enable;
|
||||
/*
|
||||
* On bifrost we have 2 sets of counters, this parameter defines the
|
||||
* one to track.
|
||||
*/
|
||||
__u32 counterset;
|
||||
};
|
||||
|
||||
struct drm_panfrost_perfcnt_dump {
|
||||
__u64 buf_ptr;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@ extern "C" {
|
|||
#define DRM_V3D_GET_PARAM 0x04
|
||||
#define DRM_V3D_GET_BO_OFFSET 0x05
|
||||
#define DRM_V3D_SUBMIT_TFU 0x06
|
||||
#define DRM_V3D_SUBMIT_CSD 0x07
|
||||
|
||||
#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
|
||||
#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
|
||||
|
|
@ -45,6 +46,7 @@ extern "C" {
|
|||
#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
|
||||
#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
|
||||
#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
|
||||
#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
|
||||
|
||||
/**
|
||||
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
|
||||
|
|
@ -190,6 +192,7 @@ enum drm_v3d_param {
|
|||
DRM_V3D_PARAM_V3D_CORE0_IDENT1,
|
||||
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
|
||||
DRM_V3D_PARAM_SUPPORTS_TFU,
|
||||
DRM_V3D_PARAM_SUPPORTS_CSD,
|
||||
};
|
||||
|
||||
struct drm_v3d_get_param {
|
||||
|
|
@ -230,6 +233,31 @@ struct drm_v3d_submit_tfu {
|
|||
__u32 out_sync;
|
||||
};
|
||||
|
||||
/* Submits a compute shader for dispatch. This job will block on any
|
||||
* previous compute shaders submitted on this fd, and any other
|
||||
* synchronization must be performed with in_sync/out_sync.
|
||||
*/
|
||||
struct drm_v3d_submit_csd {
|
||||
__u32 cfg[7];
|
||||
__u32 coef[4];
|
||||
|
||||
/* Pointer to a u32 array of the BOs that are referenced by the job.
|
||||
*/
|
||||
__u64 bo_handles;
|
||||
|
||||
/* Number of BO handles passed in (size is that times 4). */
|
||||
__u32 bo_handle_count;
|
||||
|
||||
/* sync object to block on before running the CSD job. Each
|
||||
* CSD job will execute in the order submitted to its FD.
|
||||
* Synchronization against rendering/TFU jobs or CSD from
|
||||
* other fds requires using sync objects.
|
||||
*/
|
||||
__u32 in_sync;
|
||||
/* Sync object to signal when the CSD job is done. */
|
||||
__u32 out_sync;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -35,7 +35,10 @@ struct dma_buf_sync {
|
|||
#define DMA_BUF_SYNC_VALID_FLAGS_MASK \
|
||||
(DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END)
|
||||
|
||||
#define DMA_BUF_NAME_LEN 32
|
||||
|
||||
#define DMA_BUF_BASE 'b'
|
||||
#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync)
|
||||
#define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -35,9 +35,10 @@ struct kfd_ioctl_get_version_args {
|
|||
};
|
||||
|
||||
/* For kfd_ioctl_create_queue_args.queue_type. */
|
||||
#define KFD_IOC_QUEUE_TYPE_COMPUTE 0
|
||||
#define KFD_IOC_QUEUE_TYPE_SDMA 1
|
||||
#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2
|
||||
#define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0
|
||||
#define KFD_IOC_QUEUE_TYPE_SDMA 0x1
|
||||
#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2
|
||||
#define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3
|
||||
|
||||
#define KFD_MAX_QUEUE_PERCENTAGE 100
|
||||
#define KFD_MAX_QUEUE_PRIORITY 15
|
||||
|
|
@ -338,6 +339,7 @@ struct kfd_ioctl_acquire_vm_args {
|
|||
#define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
|
||||
#define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
|
||||
#define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
|
||||
#define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4)
|
||||
/* Allocation flags: attributes/access options */
|
||||
#define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
|
||||
#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
|
||||
|
|
@ -408,6 +410,21 @@ struct kfd_ioctl_unmap_memory_from_gpu_args {
|
|||
__u32 n_success; /* to/from KFD */
|
||||
};
|
||||
|
||||
/* Allocate GWS for specific queue
|
||||
*
|
||||
* @gpu_id: device identifier
|
||||
* @queue_id: queue's id that GWS is allocated for
|
||||
* @num_gws: how many GWS to allocate
|
||||
* @first_gws: index of the first GWS allocated.
|
||||
* only support contiguous GWS allocation
|
||||
*/
|
||||
struct kfd_ioctl_alloc_queue_gws_args {
|
||||
__u32 gpu_id; /* to KFD */
|
||||
__u32 queue_id; /* to KFD */
|
||||
__u32 num_gws; /* to KFD */
|
||||
__u32 first_gws; /* from KFD */
|
||||
};
|
||||
|
||||
struct kfd_ioctl_get_dmabuf_info_args {
|
||||
__u64 size; /* from KFD */
|
||||
__u64 metadata_ptr; /* to KFD */
|
||||
|
|
@ -426,6 +443,13 @@ struct kfd_ioctl_import_dmabuf_args {
|
|||
__u32 dmabuf_fd; /* to KFD */
|
||||
};
|
||||
|
||||
/* Register offset inside the remapped mmio page
|
||||
*/
|
||||
enum kfd_mmio_remap {
|
||||
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
|
||||
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
|
||||
};
|
||||
|
||||
#define AMDKFD_IOCTL_BASE 'K'
|
||||
#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
|
||||
#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
|
||||
|
|
@ -520,7 +544,10 @@ struct kfd_ioctl_import_dmabuf_args {
|
|||
#define AMDKFD_IOC_IMPORT_DMABUF \
|
||||
AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
|
||||
|
||||
#define AMDKFD_IOC_ALLOC_QUEUE_GWS \
|
||||
AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
|
||||
|
||||
#define AMDKFD_COMMAND_START 0x01
|
||||
#define AMDKFD_COMMAND_END 0x1E
|
||||
#define AMDKFD_COMMAND_END 0x1F
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -91,5 +91,6 @@
|
|||
#define UDF_SUPER_MAGIC 0x15013346
|
||||
#define BALLOON_KVM_MAGIC 0x13661366
|
||||
#define ZSMALLOC_MAGIC 0x58295829
|
||||
#define DMA_BUF_MAGIC 0x444d4142 /* "DMAB" */
|
||||
|
||||
#endif /* __LINUX_MAGIC_H__ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue