From bedd876b6f1459495c3620a900876fbfc49b2a4a Mon Sep 17 00:00:00 2001 From: Yuanyuan Liu Date: Wed, 31 Jul 2019 11:53:34 -0700 Subject: [PATCH] net: cnss2: Add snapshot of CNSS2 driver This is a snapshot of the CNSS2 driver and associated files as of msm-4.19 commit a1c93228c0bb ("cnss2: Fix synchronization issues related to idle shutdown"). Remove obsolete cnss_utils.c and add Kconfig dependency. Replace bus scaling APIs with interconnect APIs due to msm_bus migration. CRs-Fixed: 2500800 Change-Id: I4f0af08c3d0f2982a0f9605dcc56bfeb0145a3fa Signed-off-by: Yuanyuan Liu --- drivers/net/wireless/Kconfig | 2 + drivers/net/wireless/Makefile | 2 + drivers/net/wireless/cnss2/Kconfig | 88 + drivers/net/wireless/cnss2/Makefile | 11 + drivers/net/wireless/cnss2/bus.c | 374 ++ drivers/net/wireless/cnss2/bus.h | 49 + .../wireless/cnss2/coexistence_service_v01.c | 95 + .../wireless/cnss2/coexistence_service_v01.h | 52 + drivers/net/wireless/cnss2/debug.c | 795 ++++ drivers/net/wireless/cnss2/debug.h | 77 + drivers/net/wireless/cnss2/genl.c | 203 + drivers/net/wireless/cnss2/genl.h | 34 + ...multimedia_subsystem_private_service_v01.c | 93 + ...multimedia_subsystem_private_service_v01.h | 43 + drivers/net/wireless/cnss2/main.c | 2131 ++++++++++ drivers/net/wireless/cnss2/main.h | 408 ++ drivers/net/wireless/cnss2/pci.c | 3526 ++++++++++++++++ drivers/net/wireless/cnss2/pci.h | 187 + drivers/net/wireless/cnss2/power.c | 957 +++++ drivers/net/wireless/cnss2/qmi.c | 2299 +++++++++++ drivers/net/wireless/cnss2/qmi.h | 211 + .../cnss2/wlan_firmware_service_v01.c | 3610 +++++++++++++++++ .../cnss2/wlan_firmware_service_v01.h | 952 +++++ include/net/cnss2.h | 216 + 24 files changed, 16415 insertions(+) create mode 100644 drivers/net/wireless/cnss2/Kconfig create mode 100644 drivers/net/wireless/cnss2/Makefile create mode 100644 drivers/net/wireless/cnss2/bus.c create mode 100644 drivers/net/wireless/cnss2/bus.h create mode 100644 drivers/net/wireless/cnss2/coexistence_service_v01.c create mode 100644 drivers/net/wireless/cnss2/coexistence_service_v01.h create mode 100644 drivers/net/wireless/cnss2/debug.c create mode 100644 drivers/net/wireless/cnss2/debug.h create mode 100644 drivers/net/wireless/cnss2/genl.c create mode 100644 drivers/net/wireless/cnss2/genl.h create mode 100644 drivers/net/wireless/cnss2/ip_multimedia_subsystem_private_service_v01.c create mode 100644 drivers/net/wireless/cnss2/ip_multimedia_subsystem_private_service_v01.h create mode 100644 drivers/net/wireless/cnss2/main.c create mode 100644 drivers/net/wireless/cnss2/main.h create mode 100644 drivers/net/wireless/cnss2/pci.c create mode 100644 drivers/net/wireless/cnss2/pci.h create mode 100644 drivers/net/wireless/cnss2/power.c create mode 100644 drivers/net/wireless/cnss2/qmi.c create mode 100644 drivers/net/wireless/cnss2/qmi.h create mode 100644 drivers/net/wireless/cnss2/wlan_firmware_service_v01.c create mode 100644 drivers/net/wireless/cnss2/wlan_firmware_service_v01.h create mode 100644 include/net/cnss2.h diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig index 1c98d781ae49..9f405dc2e782 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig @@ -122,4 +122,6 @@ config VIRT_WIFI This option adds support for ethernet connections to appear as if they are wifi connections through a special rtnetlink device. +source "drivers/net/wireless/cnss2/Kconfig" + endif # WLAN diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile index 6cfe74515c95..14bbe9a2fd15 100644 --- a/drivers/net/wireless/Makefile +++ b/drivers/net/wireless/Makefile @@ -29,3 +29,5 @@ obj-$(CONFIG_USB_NET_RNDIS_WLAN) += rndis_wlan.o obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o obj-$(CONFIG_VIRT_WIFI) += virt_wifi.o + +obj-$(CONFIG_CNSS2) += cnss2/ diff --git a/drivers/net/wireless/cnss2/Kconfig b/drivers/net/wireless/cnss2/Kconfig new file mode 100644 index 000000000000..406ef18e62a4 --- /dev/null +++ b/drivers/net/wireless/cnss2/Kconfig @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CNSS2 + tristate "CNSS2 Platform Driver for Wi-Fi Module" + depends on !CNSS && PCI_MSM + help + This module adds the support for Connectivity Subsystem (CNSS) used + for PCIe based Wi-Fi devices with QCA6174/QCA6290 chipsets. + This driver also adds support to integrate WLAN module to subsystem + restart framework. + +config CNSS2_DEBUG + bool "CNSS2 Platform Driver Debug Support" + depends on CNSS2 + help + This option is to enable CNSS2 platform driver debug support which + primarily includes providing additional verbose logs for certain + features, enabling kernel panic for certain cases to aid the + debugging, and enabling any other debug mechanisms. + +config CNSS2_QMI + bool "CNSS2 Platform Driver QMI support" + depends on CNSS2 + help + CNSS2 platform driver uses QMI framework to communicate with WLAN + firmware. It sends and receives boot handshake messages to WLAN + firmware, which includes hardware and software capabilities and + configurations. It also sends WLAN on/off control message to + firmware over QMI channel. + +config CNSS_ASYNC + bool "Enable/disable CNSS platform driver asynchronous probe" + depends on CNSS2 + help + If enabled, CNSS platform driver would do asynchronous probe. + Using asynchronous probe will allow CNSS platform driver to + probe in parallel with other device drivers and will help to + reduce kernel boot time. + +config BUS_AUTO_SUSPEND + bool "Enable/Disable Runtime PM support for PCIe based WLAN Drivers" + depends on CNSS2 + depends on PCI + help + Runtime Power Management is supported for PCIe based WLAN Drivers. + The features enable cld wlan driver to suspend pcie bus when APPS + is awake based on the driver inactivity with the Firmware. + The Feature uses runtime power management framework from kernel to + track bus access clients and to synchronize the driver activity + during system pm. + This config flag controls the feature per target based. The feature + requires CNSS driver support. + +config CNSS_QCA6290 + bool "Enable CNSS QCA6290 chipset specific changes" + depends on CNSS2 + help + This enables the changes from WLAN host driver that are specific to + CNSS QCA6290 chipset. + These changes are needed to support the new hardware architecture + for CNSS QCA6290 chipset. + +config CNSS_QCA6390 + bool "Enable CNSS QCA6390 chipset specific changes" + depends on CNSS2 + help + This enables the changes from WLAN host driver that are specific to + CNSS QCA6390 chipset. + These changes are needed to support the new hardware architecture + for CNSS QCA6390 chipset. + +config CNSS_EMULATION + bool "Enable specific changes for emulation hardware" + depends on CNSS2 + help + This enables the changes from WLAN drivers that are specific to + emulation hardware. + These changes are needed for WLAN drivers to support and meet the + requirement of emulation hardware. + +config CNSS_QCA6490 + bool "Enable CNSS QCA6490 chipset specific changes" + depends on CNSS2 + help + This enables the changes from WLAN host driver that are specific to + CNSS QCA6490 chipset. + These changes are needed to support the new hardware architecture + for CNSS QCA6490 chipset. \ No newline at end of file diff --git a/drivers/net/wireless/cnss2/Makefile b/drivers/net/wireless/cnss2/Makefile new file mode 100644 index 000000000000..023cefce9399 --- /dev/null +++ b/drivers/net/wireless/cnss2/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_CNSS2) += cnss2.o + +cnss2-y := main.o +cnss2-y += bus.o +cnss2-y += debug.o +cnss2-y += pci.o +cnss2-y += power.o +cnss2-$(CONFIG_CNSS2_DEBUG) += genl.o +cnss2-$(CONFIG_CNSS2_QMI) += qmi.o wlan_firmware_service_v01.o coexistence_service_v01.o ip_multimedia_subsystem_private_service_v01.o diff --git a/drivers/net/wireless/cnss2/bus.c b/drivers/net/wireless/cnss2/bus.c new file mode 100644 index 000000000000..4c56ec5f0480 --- /dev/null +++ b/drivers/net/wireless/cnss2/bus.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ + +#include "bus.h" +#include "debug.h" +#include "pci.h" + +enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev) +{ + if (!dev) + return CNSS_BUS_NONE; + + if (!dev->bus) + return CNSS_BUS_NONE; + + if (memcmp(dev->bus->name, "pci", 3) == 0) + return CNSS_BUS_PCI; + else + return CNSS_BUS_NONE; +} + +enum cnss_dev_bus_type cnss_get_bus_type(unsigned long device_id) +{ + switch (device_id) { + case QCA6174_DEVICE_ID: + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + return CNSS_BUS_PCI; + default: + cnss_pr_err("Unknown device_id: 0x%lx\n", device_id); + return CNSS_BUS_NONE; + } +} + +void *cnss_bus_dev_to_bus_priv(struct device *dev) +{ + if (!dev) + return NULL; + + switch (cnss_get_dev_bus_type(dev)) { + case CNSS_BUS_PCI: + return cnss_get_pci_priv(to_pci_dev(dev)); + default: + return NULL; + } +} + +struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev) +{ + void *bus_priv; + + if (!dev) + return cnss_get_plat_priv(NULL); + + bus_priv = cnss_bus_dev_to_bus_priv(dev); + if (!bus_priv) + return NULL; + + switch (cnss_get_dev_bus_type(dev)) { + case CNSS_BUS_PCI: + return cnss_pci_priv_to_plat_priv(bus_priv); + default: + return NULL; + } +} + +int cnss_bus_init(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_init(plat_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +void cnss_bus_deinit(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + cnss_pci_deinit(plat_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return; + } +} + +int cnss_bus_load_m3(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_load_m3(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_alloc_fw_mem(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_alloc_fw_mem(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_alloc_qdss_mem(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + cnss_pci_free_qdss_mem(plat_priv->bus_priv); + return; + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return; + } +} + +u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_get_wake_msi(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_force_fw_assert_hdlr(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t) +{ + struct cnss_plat_data *plat_priv = + from_timer(plat_priv, t, fw_boot_timer); + + if (!plat_priv) + return; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_fw_boot_timeout_hdlr(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return; + } +} + +void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv, bool in_panic) +{ + if (!plat_priv) + return; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_collect_dump_info(plat_priv->bus_priv, + in_panic); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return; + } +} + +int cnss_bus_call_driver_probe(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_call_driver_probe(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_call_driver_remove(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_call_driver_remove(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_dev_powerup(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_dev_powerup(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_dev_shutdown(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_dev_shutdown(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_dev_crash_shutdown(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_dev_crash_shutdown(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_dev_ramdump(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_dev_ramdump(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_register_driver_hdlr(struct cnss_plat_data *plat_priv, void *data) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_register_driver_hdlr(plat_priv->bus_priv, data); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_unregister_driver_hdlr(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_unregister_driver_hdlr(plat_priv->bus_priv); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv, + int modem_current_status) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_call_driver_modem_status(plat_priv->bus_priv, + modem_current_status); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} + +int cnss_bus_update_status(struct cnss_plat_data *plat_priv, + enum cnss_driver_status status) +{ + if (!plat_priv) + return -ENODEV; + + switch (plat_priv->bus_type) { + case CNSS_BUS_PCI: + return cnss_pci_update_status(plat_priv->bus_priv, status); + default: + cnss_pr_err("Unsupported bus type: %d\n", + plat_priv->bus_type); + return -EINVAL; + } +} diff --git a/drivers/net/wireless/cnss2/bus.h b/drivers/net/wireless/cnss2/bus.h new file mode 100644 index 000000000000..8190e8b52e34 --- /dev/null +++ b/drivers/net/wireless/cnss2/bus.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ + +#ifndef _CNSS_BUS_H +#define _CNSS_BUS_H + +#include "main.h" + +#define QCA6174_VENDOR_ID 0x168C +#define QCA6174_DEVICE_ID 0x003E +#define QCA6174_REV_ID_OFFSET 0x08 +#define QCA6174_REV3_VERSION 0x5020000 +#define QCA6174_REV3_2_VERSION 0x5030000 +#define QCA6290_VENDOR_ID 0x17CB +#define QCA6290_DEVICE_ID 0x1100 +#define QCA6390_VENDOR_ID 0x17CB +#define QCA6390_DEVICE_ID 0x1101 +#define QCA6490_VENDOR_ID 0x17CB +#define QCA6490_DEVICE_ID 0x1103 + +enum cnss_dev_bus_type cnss_get_dev_bus_type(struct device *dev); +enum cnss_dev_bus_type cnss_get_bus_type(unsigned long device_id); +void *cnss_bus_dev_to_bus_priv(struct device *dev); +struct cnss_plat_data *cnss_bus_dev_to_plat_priv(struct device *dev); +int cnss_bus_init(struct cnss_plat_data *plat_priv); +void cnss_bus_deinit(struct cnss_plat_data *plat_priv); +int cnss_bus_load_m3(struct cnss_plat_data *plat_priv); +int cnss_bus_alloc_fw_mem(struct cnss_plat_data *plat_priv); +int cnss_bus_alloc_qdss_mem(struct cnss_plat_data *plat_priv); +void cnss_bus_free_qdss_mem(struct cnss_plat_data *plat_priv); +u32 cnss_bus_get_wake_irq(struct cnss_plat_data *plat_priv); +int cnss_bus_force_fw_assert_hdlr(struct cnss_plat_data *plat_priv); +void cnss_bus_fw_boot_timeout_hdlr(struct timer_list *t); +void cnss_bus_collect_dump_info(struct cnss_plat_data *plat_priv, + bool in_panic); +int cnss_bus_call_driver_probe(struct cnss_plat_data *plat_priv); +int cnss_bus_call_driver_remove(struct cnss_plat_data *plat_priv); +int cnss_bus_dev_powerup(struct cnss_plat_data *plat_priv); +int cnss_bus_dev_shutdown(struct cnss_plat_data *plat_priv); +int cnss_bus_dev_crash_shutdown(struct cnss_plat_data *plat_priv); +int cnss_bus_dev_ramdump(struct cnss_plat_data *plat_priv); +int cnss_bus_register_driver_hdlr(struct cnss_plat_data *plat_priv, void *data); +int cnss_bus_unregister_driver_hdlr(struct cnss_plat_data *plat_priv); +int cnss_bus_call_driver_modem_status(struct cnss_plat_data *plat_priv, + int modem_current_status); +int cnss_bus_update_status(struct cnss_plat_data *plat_priv, + enum cnss_driver_status status); + +#endif /* _CNSS_BUS_H */ diff --git a/drivers/net/wireless/cnss2/coexistence_service_v01.c b/drivers/net/wireless/cnss2/coexistence_service_v01.c new file mode 100644 index 000000000000..1016226179c9 --- /dev/null +++ b/drivers/net/wireless/cnss2/coexistence_service_v01.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */ + +#include + +#include "coexistence_service_v01.h" + +struct qmi_elem_info coex_antenna_switch_to_wlan_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + coex_antenna_switch_to_wlan_req_msg_v01, + antenna), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info coex_antenna_switch_to_wlan_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + coex_antenna_switch_to_wlan_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + coex_antenna_switch_to_wlan_resp_msg_v01, + grant_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + coex_antenna_switch_to_wlan_resp_msg_v01, + grant), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info coex_antenna_switch_to_mdm_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + coex_antenna_switch_to_mdm_req_msg_v01, + antenna), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info coex_antenna_switch_to_mdm_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + coex_antenna_switch_to_mdm_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, +}; diff --git a/drivers/net/wireless/cnss2/coexistence_service_v01.h b/drivers/net/wireless/cnss2/coexistence_service_v01.h new file mode 100644 index 000000000000..03ee7e98d1da --- /dev/null +++ b/drivers/net/wireless/cnss2/coexistence_service_v01.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */ + +#ifndef COEXISTENCE_SERVICE_V01_H +#define COEXISTENCE_SERVICE_V01_H + +#define COEX_SERVICE_ID_V01 0x22 +#define COEX_SERVICE_VERS_V01 0x01 + +#define COEX_SERVICE_MAX_MSG_LEN 8204 + +#define QMI_COEX_SWITCH_ANTENNA_TO_WLAN_RESP_V01 0x0042 +#define QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01 0x0042 +#define QMI_COEX_SWITCH_ANTENNA_TO_MDM_RESP_V01 0x0042 +#define QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01 0x0042 + +#define COEX_ANTENNA_BAND_2GHZ_CHAIN0_V01 ((u64)0x0000000000000001ULL) +#define COEX_ANTENNA_BAND_2GHZ_CHAIN1_V01 ((u64)0x0000000000000002ULL) +#define COEX_ANTENNA_BAND_5GHZ_CHAIN0_V01 ((u64)0x0000000000000004ULL) +#define COEX_ANTENNA_BAND_5GHZ_CHAIN1_V01 ((u64)0x0000000000000008ULL) + +struct coex_antenna_switch_to_wlan_req_msg_v01 { + u64 antenna; +}; + +#define COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN 11 +extern struct qmi_elem_info coex_antenna_switch_to_wlan_req_msg_v01_ei[]; + +struct coex_antenna_switch_to_wlan_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 grant_valid; + u64 grant; +}; + +#define COEX_ANTENNA_SWITCH_TO_WLAN_RESP_MSG_V01_MAX_MSG_LEN 18 +extern struct qmi_elem_info coex_antenna_switch_to_wlan_resp_msg_v01_ei[]; + +struct coex_antenna_switch_to_mdm_req_msg_v01 { + u64 antenna; +}; + +#define COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN 11 +extern struct qmi_elem_info coex_antenna_switch_to_mdm_req_msg_v01_ei[]; + +struct coex_antenna_switch_to_mdm_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define COEX_ANTENNA_SWITCH_TO_MDM_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info coex_antenna_switch_to_mdm_resp_msg_v01_ei[]; + +#endif diff --git a/drivers/net/wireless/cnss2/debug.c b/drivers/net/wireless/cnss2/debug.c new file mode 100644 index 000000000000..cc1e1f6efb2c --- /dev/null +++ b/drivers/net/wireless/cnss2/debug.c @@ -0,0 +1,795 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include "main.h" +#include "debug.h" +#include "pci.h" + +void *cnss_ipc_log_context; +void *cnss_ipc_log_long_context; + +static int cnss_pin_connect_show(struct seq_file *s, void *data) +{ + struct cnss_plat_data *cnss_priv = s->private; + + seq_puts(s, "Pin connect results\n"); + seq_printf(s, "FW power pin result: %04x\n", + cnss_priv->pin_result.fw_pwr_pin_result); + seq_printf(s, "FW PHY IO pin result: %04x\n", + cnss_priv->pin_result.fw_phy_io_pin_result); + seq_printf(s, "FW RF pin result: %04x\n", + cnss_priv->pin_result.fw_rf_pin_result); + seq_printf(s, "Host pin result: %04x\n", + cnss_priv->pin_result.host_pin_result); + seq_puts(s, "\n"); + + return 0; +} + +static int cnss_pin_connect_open(struct inode *inode, struct file *file) +{ + return single_open(file, cnss_pin_connect_show, inode->i_private); +} + +static const struct file_operations cnss_pin_connect_fops = { + .read = seq_read, + .release = single_release, + .open = cnss_pin_connect_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + +static int cnss_stats_show_state(struct seq_file *s, + struct cnss_plat_data *plat_priv) +{ + enum cnss_driver_state i; + int skip = 0; + unsigned long state; + + seq_printf(s, "\nState: 0x%lx(", plat_priv->driver_state); + for (i = 0, state = plat_priv->driver_state; state != 0; + state >>= 1, i++) { + if (!(state & 0x1)) + continue; + + if (skip++) + seq_puts(s, " | "); + + switch (i) { + case CNSS_QMI_WLFW_CONNECTED: + seq_puts(s, "QMI_WLFW_CONNECTED"); + continue; + case CNSS_FW_MEM_READY: + seq_puts(s, "FW_MEM_READY"); + continue; + case CNSS_FW_READY: + seq_puts(s, "FW_READY"); + continue; + case CNSS_COLD_BOOT_CAL: + seq_puts(s, "COLD_BOOT_CAL"); + continue; + case CNSS_DRIVER_LOADING: + seq_puts(s, "DRIVER_LOADING"); + continue; + case CNSS_DRIVER_UNLOADING: + seq_puts(s, "DRIVER_UNLOADING"); + continue; + case CNSS_DRIVER_IDLE_RESTART: + seq_puts(s, "IDLE_RESTART"); + continue; + case CNSS_DRIVER_IDLE_SHUTDOWN: + seq_puts(s, "IDLE_SHUTDOWN"); + continue; + case CNSS_DRIVER_PROBED: + seq_puts(s, "DRIVER_PROBED"); + continue; + case CNSS_DRIVER_RECOVERY: + seq_puts(s, "DRIVER_RECOVERY"); + continue; + case CNSS_FW_BOOT_RECOVERY: + seq_puts(s, "FW_BOOT_RECOVERY"); + continue; + case CNSS_DEV_ERR_NOTIFY: + seq_puts(s, "DEV_ERR"); + continue; + case CNSS_DRIVER_DEBUG: + seq_puts(s, "DRIVER_DEBUG"); + continue; + case CNSS_COEX_CONNECTED: + seq_puts(s, "COEX_CONNECTED"); + continue; + case CNSS_IMS_CONNECTED: + seq_puts(s, "IMS_CONNECTED"); + continue; + case CNSS_IN_SUSPEND_RESUME: + seq_puts(s, "IN_SUSPEND_RESUME"); + continue; + } + + seq_printf(s, "UNKNOWN-%d", i); + } + seq_puts(s, ")\n"); + + return 0; +} + +static int cnss_stats_show(struct seq_file *s, void *data) +{ + struct cnss_plat_data *plat_priv = s->private; + + cnss_stats_show_state(s, plat_priv); + + return 0; +} + +static int cnss_stats_open(struct inode *inode, struct file *file) +{ + return single_open(file, cnss_stats_show, inode->i_private); +} + +static const struct file_operations cnss_stats_fops = { + .read = seq_read, + .release = single_release, + .open = cnss_stats_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + +static ssize_t cnss_dev_boot_debug_write(struct file *fp, + const char __user *user_buf, + size_t count, loff_t *off) +{ + struct cnss_plat_data *plat_priv = + ((struct seq_file *)fp->private_data)->private; + struct cnss_pci_data *pci_priv; + char buf[64]; + char *cmd; + unsigned int len = 0; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + pci_priv = plat_priv->bus_priv; + if (!pci_priv) + return -ENODEV; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + cmd = buf; + + if (sysfs_streq(cmd, "on")) { + ret = cnss_power_on_device(plat_priv); + } else if (sysfs_streq(cmd, "off")) { + cnss_power_off_device(plat_priv); + } else if (sysfs_streq(cmd, "enumerate")) { + ret = cnss_pci_init(plat_priv); + } else if (sysfs_streq(cmd, "download")) { + set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state); + ret = cnss_pci_start_mhi(pci_priv); + } else if (sysfs_streq(cmd, "linkup")) { + ret = cnss_resume_pci_link(pci_priv); + } else if (sysfs_streq(cmd, "linkdown")) { + ret = cnss_suspend_pci_link(pci_priv); + } else if (sysfs_streq(cmd, "powerup")) { + set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state); + ret = cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_POWER_UP, + CNSS_EVENT_SYNC, NULL); + } else if (sysfs_streq(cmd, "shutdown")) { + ret = cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_POWER_DOWN, + 0, NULL); + clear_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state); + } else if (sysfs_streq(cmd, "assert")) { + ret = cnss_force_fw_assert(&pci_priv->pci_dev->dev); + } else { + cnss_pr_err("Device boot debugfs command is invalid\n"); + ret = -EINVAL; + } + + if (ret) + return ret; + + return count; +} + +static int cnss_dev_boot_debug_show(struct seq_file *s, void *data) +{ + seq_puts(s, "\nUsage: echo > /cnss/dev_boot\n"); + seq_puts(s, " can be one of below:\n"); + seq_puts(s, "on: turn on device power, assert WLAN_EN\n"); + seq_puts(s, "off: de-assert WLAN_EN, turn off device power\n"); + seq_puts(s, "enumerate: de-assert PERST, enumerate PCIe\n"); + seq_puts(s, "download: download FW and do QMI handshake with FW\n"); + seq_puts(s, "linkup: bring up PCIe link\n"); + seq_puts(s, "linkdown: bring down PCIe link\n"); + seq_puts(s, "powerup: full power on sequence to boot device, download FW and do QMI handshake with FW\n"); + seq_puts(s, "shutdown: full power off sequence to shutdown device\n"); + seq_puts(s, "assert: trigger firmware assert\n"); + + return 0; +} + +static int cnss_dev_boot_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, cnss_dev_boot_debug_show, inode->i_private); +} + +static const struct file_operations cnss_dev_boot_debug_fops = { + .read = seq_read, + .write = cnss_dev_boot_debug_write, + .release = single_release, + .open = cnss_dev_boot_debug_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + +static int cnss_reg_read_debug_show(struct seq_file *s, void *data) +{ + struct cnss_plat_data *plat_priv = s->private; + + mutex_lock(&plat_priv->dev_lock); + if (!plat_priv->diag_reg_read_buf) { + seq_puts(s, "\nUsage: echo > /cnss/reg_read\n"); + mutex_unlock(&plat_priv->dev_lock); + return 0; + } + + seq_printf(s, "\nRegister read, address: 0x%x memory type: 0x%x length: 0x%x\n\n", + plat_priv->diag_reg_read_addr, + plat_priv->diag_reg_read_mem_type, + plat_priv->diag_reg_read_len); + + seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 32, 4, + plat_priv->diag_reg_read_buf, + plat_priv->diag_reg_read_len, false); + + plat_priv->diag_reg_read_len = 0; + kfree(plat_priv->diag_reg_read_buf); + plat_priv->diag_reg_read_buf = NULL; + mutex_unlock(&plat_priv->dev_lock); + + return 0; +} + +static ssize_t cnss_reg_read_debug_write(struct file *fp, + const char __user *user_buf, + size_t count, loff_t *off) +{ + struct cnss_plat_data *plat_priv = + ((struct seq_file *)fp->private_data)->private; + char buf[64]; + char *sptr, *token; + unsigned int len = 0; + u32 reg_offset, mem_type; + u32 data_len = 0; + u8 *reg_buf = NULL; + const char *delim = " "; + int ret = 0; + + if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) { + cnss_pr_err("Firmware is not ready yet\n"); + return -EINVAL; + } + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + sptr = buf; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + + if (!sptr) + return -EINVAL; + + if (kstrtou32(token, 0, &mem_type)) + return -EINVAL; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + + if (!sptr) + return -EINVAL; + + if (kstrtou32(token, 0, ®_offset)) + return -EINVAL; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + + if (kstrtou32(token, 0, &data_len)) + return -EINVAL; + + mutex_lock(&plat_priv->dev_lock); + kfree(plat_priv->diag_reg_read_buf); + plat_priv->diag_reg_read_buf = NULL; + + reg_buf = kzalloc(data_len, GFP_KERNEL); + if (!reg_buf) { + mutex_unlock(&plat_priv->dev_lock); + return -ENOMEM; + } + + ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, reg_offset, + mem_type, data_len, + reg_buf); + if (ret) { + kfree(reg_buf); + mutex_unlock(&plat_priv->dev_lock); + return ret; + } + + plat_priv->diag_reg_read_addr = reg_offset; + plat_priv->diag_reg_read_mem_type = mem_type; + plat_priv->diag_reg_read_len = data_len; + plat_priv->diag_reg_read_buf = reg_buf; + mutex_unlock(&plat_priv->dev_lock); + + return count; +} + +static int cnss_reg_read_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, cnss_reg_read_debug_show, inode->i_private); +} + +static const struct file_operations cnss_reg_read_debug_fops = { + .read = seq_read, + .write = cnss_reg_read_debug_write, + .open = cnss_reg_read_debug_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + +static int cnss_reg_write_debug_show(struct seq_file *s, void *data) +{ + seq_puts(s, "\nUsage: echo > /cnss/reg_write\n"); + + return 0; +} + +static ssize_t cnss_reg_write_debug_write(struct file *fp, + const char __user *user_buf, + size_t count, loff_t *off) +{ + struct cnss_plat_data *plat_priv = + ((struct seq_file *)fp->private_data)->private; + char buf[64]; + char *sptr, *token; + unsigned int len = 0; + u32 reg_offset, mem_type, reg_val; + const char *delim = " "; + int ret = 0; + + if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) { + cnss_pr_err("Firmware is not ready yet\n"); + return -EINVAL; + } + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + sptr = buf; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + + if (!sptr) + return -EINVAL; + + if (kstrtou32(token, 0, &mem_type)) + return -EINVAL; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + + if (!sptr) + return -EINVAL; + + if (kstrtou32(token, 0, ®_offset)) + return -EINVAL; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + + if (kstrtou32(token, 0, ®_val)) + return -EINVAL; + + ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type, + sizeof(u32), + (u8 *)®_val); + if (ret) + return ret; + + return count; +} + +static int cnss_reg_write_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, cnss_reg_write_debug_show, inode->i_private); +} + +static const struct file_operations cnss_reg_write_debug_fops = { + .read = seq_read, + .write = cnss_reg_write_debug_write, + .open = cnss_reg_write_debug_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + +static ssize_t cnss_runtime_pm_debug_write(struct file *fp, + const char __user *user_buf, + size_t count, loff_t *off) +{ + struct cnss_plat_data *plat_priv = + ((struct seq_file *)fp->private_data)->private; + struct cnss_pci_data *pci_priv; + char buf[64]; + char *cmd; + unsigned int len = 0; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + pci_priv = plat_priv->bus_priv; + if (!pci_priv) + return -ENODEV; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + cmd = buf; + + if (sysfs_streq(cmd, "usage_count")) { + cnss_pci_pm_runtime_show_usage_count(pci_priv); + } else if (sysfs_streq(cmd, "request_resume")) { + ret = cnss_pci_pm_request_resume(pci_priv); + } else if (sysfs_streq(cmd, "resume")) { + ret = cnss_pci_pm_runtime_resume(pci_priv); + } else if (sysfs_streq(cmd, "get")) { + ret = cnss_pci_pm_runtime_get(pci_priv); + } else if (sysfs_streq(cmd, "get_noresume")) { + cnss_pci_pm_runtime_get_noresume(pci_priv); + } else if (sysfs_streq(cmd, "put_autosuspend")) { + ret = cnss_pci_pm_runtime_put_autosuspend(pci_priv); + } else if (sysfs_streq(cmd, "put_noidle")) { + cnss_pci_pm_runtime_put_noidle(pci_priv); + } else if (sysfs_streq(cmd, "mark_last_busy")) { + cnss_pci_pm_runtime_mark_last_busy(pci_priv); + } else { + cnss_pr_err("Runtime PM debugfs command is invalid\n"); + ret = -EINVAL; + } + + if (ret) + return ret; + + return count; +} + +static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data) +{ + seq_puts(s, "\nUsage: echo > /cnss/runtime_pm\n"); + seq_puts(s, " can be one of below:\n"); + seq_puts(s, "usage_count: get runtime PM usage count\n"); + seq_puts(s, "get: do runtime PM get\n"); + seq_puts(s, "get_noresume: do runtime PM get noresume\n"); + seq_puts(s, "put_noidle: do runtime PM put noidle\n"); + seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n"); + seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n"); + + return 0; +} + +static int cnss_runtime_pm_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, cnss_runtime_pm_debug_show, inode->i_private); +} + +static const struct file_operations cnss_runtime_pm_debug_fops = { + .read = seq_read, + .write = cnss_runtime_pm_debug_write, + .open = cnss_runtime_pm_debug_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + +static ssize_t cnss_control_params_debug_write(struct file *fp, + const char __user *user_buf, + size_t count, loff_t *off) +{ + struct cnss_plat_data *plat_priv = + ((struct seq_file *)fp->private_data)->private; + char buf[64]; + char *sptr, *token; + char *cmd; + u32 val; + unsigned int len = 0; + const char *delim = " "; + + if (!plat_priv) + return -ENODEV; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + sptr = buf; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + if (!sptr) + return -EINVAL; + cmd = token; + + token = strsep(&sptr, delim); + if (!token) + return -EINVAL; + if (kstrtou32(token, 0, &val)) + return -EINVAL; + + if (strcmp(cmd, "quirks") == 0) + plat_priv->ctrl_params.quirks = val; + else if (strcmp(cmd, "mhi_timeout") == 0) + plat_priv->ctrl_params.mhi_timeout = val; + else if (strcmp(cmd, "qmi_timeout") == 0) + plat_priv->ctrl_params.qmi_timeout = val; + else if (strcmp(cmd, "bdf_type") == 0) + plat_priv->ctrl_params.bdf_type = val; + else if (strcmp(cmd, "time_sync_period") == 0) + plat_priv->ctrl_params.time_sync_period = val; + else + return -EINVAL; + + return count; +} + +static int cnss_show_quirks_state(struct seq_file *s, + struct cnss_plat_data *plat_priv) +{ + enum cnss_debug_quirks i; + int skip = 0; + unsigned long state; + + seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks); + for (i = 0, state = plat_priv->ctrl_params.quirks; + state != 0; state >>= 1, i++) { + if (!(state & 0x1)) + continue; + if (skip++) + seq_puts(s, " | "); + + switch (i) { + case LINK_DOWN_SELF_RECOVERY: + seq_puts(s, "LINK_DOWN_SELF_RECOVERY"); + continue; + case SKIP_DEVICE_BOOT: + seq_puts(s, "SKIP_DEVICE_BOOT"); + continue; + case USE_CORE_ONLY_FW: + seq_puts(s, "USE_CORE_ONLY_FW"); + continue; + case SKIP_RECOVERY: + seq_puts(s, "SKIP_RECOVERY"); + continue; + case QMI_BYPASS: + seq_puts(s, "QMI_BYPASS"); + continue; + case ENABLE_WALTEST: + seq_puts(s, "WALTEST"); + continue; + case ENABLE_PCI_LINK_DOWN_PANIC: + seq_puts(s, "PCI_LINK_DOWN_PANIC"); + continue; + case FBC_BYPASS: + seq_puts(s, "FBC_BYPASS"); + continue; + case ENABLE_DAEMON_SUPPORT: + seq_puts(s, "DAEMON_SUPPORT"); + continue; + case DISABLE_DRV: + seq_puts(s, "DISABLE_DRV"); + continue; + } + + seq_printf(s, "UNKNOWN-%d", i); + } + seq_puts(s, ")\n"); + return 0; +} + +static int cnss_control_params_debug_show(struct seq_file *s, void *data) +{ + struct cnss_plat_data *cnss_priv = s->private; + + seq_puts(s, "\nUsage: echo > /cnss/control_params\n"); + seq_puts(s, " can be one of below:\n"); + seq_puts(s, "quirks: Debug quirks for driver\n"); + seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n"); + seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n"); + seq_puts(s, "bdf_type: Type of board data file to be downloaded\n"); + seq_puts(s, "time_sync_period: Time period to do time sync with device in milliseconds\n"); + + seq_puts(s, "\nCurrent value:\n"); + cnss_show_quirks_state(s, cnss_priv); + seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout); + seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout); + seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type); + seq_printf(s, "time_sync_period: %u\n", + cnss_priv->ctrl_params.time_sync_period); + + return 0; +} + +static int cnss_control_params_debug_open(struct inode *inode, + struct file *file) +{ + return single_open(file, cnss_control_params_debug_show, + inode->i_private); +} + +static const struct file_operations cnss_control_params_debug_fops = { + .read = seq_read, + .write = cnss_control_params_debug_write, + .open = cnss_control_params_debug_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + +static ssize_t cnss_dynamic_feature_write(struct file *fp, + const char __user *user_buf, + size_t count, loff_t *off) +{ + struct cnss_plat_data *plat_priv = + ((struct seq_file *)fp->private_data)->private; + int ret = 0; + u64 val; + + ret = kstrtou64_from_user(user_buf, count, 0, &val); + if (ret) + return ret; + + plat_priv->dynamic_feature = val; + ret = cnss_wlfw_dynamic_feature_mask_send_sync(plat_priv); + if (ret < 0) + return ret; + + return count; +} + +static int cnss_dynamic_feature_show(struct seq_file *s, void *data) +{ + struct cnss_plat_data *cnss_priv = s->private; + + seq_printf(s, "dynamic_feature: 0x%llx\n", cnss_priv->dynamic_feature); + + return 0; +} + +static int cnss_dynamic_feature_open(struct inode *inode, + struct file *file) +{ + return single_open(file, cnss_dynamic_feature_show, + inode->i_private); +} + +static const struct file_operations cnss_dynamic_feature_fops = { + .read = seq_read, + .write = cnss_dynamic_feature_write, + .open = cnss_dynamic_feature_open, + .owner = THIS_MODULE, + .llseek = seq_lseek, +}; + +#ifdef CONFIG_CNSS2_DEBUG +static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv) +{ + struct dentry *root_dentry = plat_priv->root_dentry; + + debugfs_create_file("dev_boot", 0600, root_dentry, plat_priv, + &cnss_dev_boot_debug_fops); + debugfs_create_file("reg_read", 0600, root_dentry, plat_priv, + &cnss_reg_read_debug_fops); + debugfs_create_file("reg_write", 0600, root_dentry, plat_priv, + &cnss_reg_write_debug_fops); + debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv, + &cnss_runtime_pm_debug_fops); + debugfs_create_file("control_params", 0600, root_dentry, plat_priv, + &cnss_control_params_debug_fops); + debugfs_create_file("dynamic_feature", 0600, root_dentry, plat_priv, + &cnss_dynamic_feature_fops); + + return 0; +} +#else +static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv) +{ + return 0; +} +#endif + +int cnss_debugfs_create(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + struct dentry *root_dentry; + + root_dentry = debugfs_create_dir("cnss", 0); + if (IS_ERR(root_dentry)) { + ret = PTR_ERR(root_dentry); + cnss_pr_err("Unable to create debugfs %d\n", ret); + goto out; + } + + plat_priv->root_dentry = root_dentry; + + debugfs_create_file("pin_connect_result", 0644, root_dentry, plat_priv, + &cnss_pin_connect_fops); + debugfs_create_file("stats", 0644, root_dentry, plat_priv, + &cnss_stats_fops); + + cnss_create_debug_only_node(plat_priv); + +out: + return ret; +} + +void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv) +{ + debugfs_remove_recursive(plat_priv->root_dentry); +} + +int cnss_debug_init(void) +{ + cnss_ipc_log_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES, + "cnss", 0); + if (!cnss_ipc_log_context) { + cnss_pr_err("Unable to create IPC log context\n"); + return -EINVAL; + } + + cnss_ipc_log_long_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES, + "cnss-long", 0); + if (!cnss_ipc_log_long_context) { + cnss_pr_err("Unable to create IPC long log context\n"); + ipc_log_context_destroy(cnss_ipc_log_context); + return -EINVAL; + } + + return 0; +} + +void cnss_debug_deinit(void) +{ + if (cnss_ipc_log_long_context) { + ipc_log_context_destroy(cnss_ipc_log_long_context); + cnss_ipc_log_long_context = NULL; + } + + if (cnss_ipc_log_context) { + ipc_log_context_destroy(cnss_ipc_log_context); + cnss_ipc_log_context = NULL; + } +} diff --git a/drivers/net/wireless/cnss2/debug.h b/drivers/net/wireless/cnss2/debug.h new file mode 100644 index 000000000000..1d7b488d2963 --- /dev/null +++ b/drivers/net/wireless/cnss2/debug.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ + +#ifndef _CNSS_DEBUG_H +#define _CNSS_DEBUG_H + +#include +#include + +#define CNSS_IPC_LOG_PAGES 32 + +extern void *cnss_ipc_log_context; +extern void *cnss_ipc_log_long_context; + +#define cnss_ipc_log_string(_x...) do { \ + if (cnss_ipc_log_context) \ + ipc_log_string(cnss_ipc_log_context, _x); \ + } while (0) + +#define cnss_ipc_log_long_string(_x...) do { \ + if (cnss_ipc_log_long_context) \ + ipc_log_string(cnss_ipc_log_long_context, _x); \ + } while (0) + +#define cnss_pr_err(_fmt, ...) do { \ + printk("%scnss: " _fmt, KERN_ERR, ##__VA_ARGS__); \ + cnss_ipc_log_string("%scnss: " _fmt, "", ##__VA_ARGS__);\ + } while (0) + +#define cnss_pr_warn(_fmt, ...) do { \ + printk("%scnss: " _fmt, KERN_WARNING, ##__VA_ARGS__); \ + cnss_ipc_log_string("%scnss: " _fmt, "", ##__VA_ARGS__);\ + } while (0) + +#define cnss_pr_info(_fmt, ...) do { \ + printk("%scnss: " _fmt, KERN_INFO, ##__VA_ARGS__); \ + cnss_ipc_log_string("%scnss: " _fmt, "", ##__VA_ARGS__);\ + } while (0) + +#define cnss_pr_dbg(_fmt, ...) do { \ + printk("%scnss: " _fmt, KERN_DEBUG, ##__VA_ARGS__); \ + cnss_ipc_log_string("%scnss: " _fmt, "", ##__VA_ARGS__);\ + } while (0) + +#define cnss_pr_vdbg(_fmt, ...) do { \ + printk("%scnss: " _fmt, KERN_DEBUG, ##__VA_ARGS__); \ + cnss_ipc_log_long_string("%scnss: " _fmt, "", \ + ##__VA_ARGS__); \ + } while (0) + +#ifdef CONFIG_CNSS2_DEBUG +#define CNSS_ASSERT(_condition) do { \ + if (!(_condition)) { \ + cnss_pr_err("ASSERT at line %d\n", \ + __LINE__); \ + BUG(); \ + } \ + } while (0) +#else +#define CNSS_ASSERT(_condition) do { \ + if (!(_condition)) { \ + cnss_pr_err("ASSERT at line %d\n", \ + __LINE__); \ + WARN_ON(1); \ + } \ + } while (0) +#endif + +#define cnss_fatal_err(_fmt, ...) \ + cnss_pr_err("fatal: " _fmt, ##__VA_ARGS__) + +int cnss_debug_init(void); +void cnss_debug_deinit(void); +int cnss_debugfs_create(struct cnss_plat_data *plat_priv); +void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv); + +#endif /* _CNSS_DEBUG_H */ diff --git a/drivers/net/wireless/cnss2/genl.c b/drivers/net/wireless/cnss2/genl.c new file mode 100644 index 000000000000..5a7fb1f50307 --- /dev/null +++ b/drivers/net/wireless/cnss2/genl.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */ + +#define pr_fmt(fmt) "cnss_genl: " fmt + +#include +#include +#include +#include + +#include "main.h" +#include "debug.h" + +#define CNSS_GENL_FAMILY_NAME "cnss-genl" +#define CNSS_GENL_MCAST_GROUP_NAME "cnss-genl-grp" +#define CNSS_GENL_VERSION 1 +#define CNSS_GENL_DATA_LEN_MAX (15 * 1024) +#define CNSS_GENL_STR_LEN_MAX 16 + +enum { + CNSS_GENL_ATTR_MSG_UNSPEC, + CNSS_GENL_ATTR_MSG_TYPE, + CNSS_GENL_ATTR_MSG_FILE_NAME, + CNSS_GENL_ATTR_MSG_TOTAL_SIZE, + CNSS_GENL_ATTR_MSG_SEG_ID, + CNSS_GENL_ATTR_MSG_END, + CNSS_GENL_ATTR_MSG_DATA_LEN, + CNSS_GENL_ATTR_MSG_DATA, + __CNSS_GENL_ATTR_MAX, +}; + +#define CNSS_GENL_ATTR_MAX (__CNSS_GENL_ATTR_MAX - 1) + +enum { + CNSS_GENL_CMD_UNSPEC, + CNSS_GENL_CMD_MSG, + __CNSS_GENL_CMD_MAX, +}; + +#define CNSS_GENL_CMD_MAX (__CNSS_GENL_CMD_MAX - 1) + +static struct nla_policy cnss_genl_msg_policy[CNSS_GENL_ATTR_MAX + 1] = { + [CNSS_GENL_ATTR_MSG_TYPE] = { .type = NLA_U8 }, + [CNSS_GENL_ATTR_MSG_FILE_NAME] = { .type = NLA_NUL_STRING, + .len = CNSS_GENL_STR_LEN_MAX }, + [CNSS_GENL_ATTR_MSG_TOTAL_SIZE] = { .type = NLA_U32 }, + [CNSS_GENL_ATTR_MSG_SEG_ID] = { .type = NLA_U32 }, + [CNSS_GENL_ATTR_MSG_END] = { .type = NLA_U8 }, + [CNSS_GENL_ATTR_MSG_DATA_LEN] = { .type = NLA_U32 }, + [CNSS_GENL_ATTR_MSG_DATA] = { .type = NLA_BINARY, + .len = CNSS_GENL_DATA_LEN_MAX }, +}; + +static int cnss_genl_process_msg(struct sk_buff *skb, struct genl_info *info) +{ + return 0; +} + +static struct genl_ops cnss_genl_ops[] = { + { + .cmd = CNSS_GENL_CMD_MSG, + .policy = cnss_genl_msg_policy, + .doit = cnss_genl_process_msg, + }, +}; + +static struct genl_multicast_group cnss_genl_mcast_grp[] = { + { + .name = CNSS_GENL_MCAST_GROUP_NAME, + }, +}; + +static struct genl_family cnss_genl_family = { + .id = 0, + .hdrsize = 0, + .name = CNSS_GENL_FAMILY_NAME, + .version = CNSS_GENL_VERSION, + .maxattr = CNSS_GENL_ATTR_MAX, + .module = THIS_MODULE, + .ops = cnss_genl_ops, + .n_ops = ARRAY_SIZE(cnss_genl_ops), + .mcgrps = cnss_genl_mcast_grp, + .n_mcgrps = ARRAY_SIZE(cnss_genl_mcast_grp), +}; + +static int cnss_genl_send_data(u8 type, char *file_name, u32 total_size, + u32 seg_id, u8 end, u32 data_len, u8 *msg_buff) +{ + struct sk_buff *skb = NULL; + void *msg_header = NULL; + int ret = 0; + char filename[CNSS_GENL_STR_LEN_MAX + 1]; + + cnss_pr_dbg("type: %u, file_name %s, total_size: %x, seg_id %u, end %u, data_len %u\n", + type, file_name, total_size, seg_id, end, data_len); + + if (!file_name) + strlcpy(filename, "default", sizeof(filename)); + else + strlcpy(filename, file_name, sizeof(filename)); + + skb = genlmsg_new(NLMSG_HDRLEN + + nla_total_size(sizeof(type)) + + nla_total_size(strlen(filename) + 1) + + nla_total_size(sizeof(total_size)) + + nla_total_size(sizeof(seg_id)) + + nla_total_size(sizeof(end)) + + nla_total_size(sizeof(data_len)) + + nla_total_size(data_len), GFP_KERNEL); + if (!skb) + return -ENOMEM; + + msg_header = genlmsg_put(skb, 0, 0, + &cnss_genl_family, 0, + CNSS_GENL_CMD_MSG); + if (!msg_header) { + ret = -ENOMEM; + goto fail; + } + + ret = nla_put_u8(skb, CNSS_GENL_ATTR_MSG_TYPE, type); + if (ret < 0) + goto fail; + ret = nla_put_string(skb, CNSS_GENL_ATTR_MSG_FILE_NAME, filename); + if (ret < 0) + goto fail; + ret = nla_put_u32(skb, CNSS_GENL_ATTR_MSG_TOTAL_SIZE, total_size); + if (ret < 0) + goto fail; + ret = nla_put_u32(skb, CNSS_GENL_ATTR_MSG_SEG_ID, seg_id); + if (ret < 0) + goto fail; + ret = nla_put_u8(skb, CNSS_GENL_ATTR_MSG_END, end); + if (ret < 0) + goto fail; + ret = nla_put_u32(skb, CNSS_GENL_ATTR_MSG_DATA_LEN, data_len); + if (ret < 0) + goto fail; + ret = nla_put(skb, CNSS_GENL_ATTR_MSG_DATA, data_len, msg_buff); + if (ret < 0) + goto fail; + + genlmsg_end(skb, msg_header); + ret = genlmsg_multicast(&cnss_genl_family, skb, 0, 0, GFP_KERNEL); + if (ret < 0) + cnss_pr_err("Fail to send genl msg: %d\n", ret); + + return ret; +fail: + cnss_pr_err("Fail to generate genl msg: %d\n", ret); + if (skb) + nlmsg_free(skb); + return ret; +} + +int cnss_genl_send_msg(void *buff, u8 type, char *file_name, u32 total_size) +{ + int ret = 0; + u8 *msg_buff = buff; + u32 remaining = total_size; + u32 seg_id = 0; + u32 data_len = 0; + u8 end = 0; + + cnss_pr_dbg("type: %u, total_size: %x\n", type, total_size); + + while (remaining) { + if (remaining > CNSS_GENL_DATA_LEN_MAX) { + data_len = CNSS_GENL_DATA_LEN_MAX; + } else { + data_len = remaining; + end = 1; + } + ret = cnss_genl_send_data(type, file_name, total_size, + seg_id, end, data_len, msg_buff); + if (ret < 0) { + cnss_pr_err("fail to send genl data, ret %d\n", ret); + return ret; + } + + remaining -= data_len; + msg_buff += data_len; + seg_id++; + } + + return ret; +} + +int cnss_genl_init(void) +{ + int ret = 0; + + ret = genl_register_family(&cnss_genl_family); + if (ret != 0) + cnss_pr_err("genl_register_family fail: %d\n", ret); + + return ret; +} + +void cnss_genl_exit(void) +{ + genl_unregister_family(&cnss_genl_family); +} diff --git a/drivers/net/wireless/cnss2/genl.h b/drivers/net/wireless/cnss2/genl.h new file mode 100644 index 000000000000..33ca30a9ac06 --- /dev/null +++ b/drivers/net/wireless/cnss2/genl.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */ + +#ifndef __CNSS_GENL_H__ +#define __CNSS_GENL_H__ + +enum cnss_genl_msg_type { + CNSS_GENL_MSG_TYPE_UNSPEC, + CNSS_GENL_MSG_TYPE_QDSS, +}; + +#ifdef CONFIG_CNSS2_DEBUG +int cnss_genl_init(void); +void cnss_genl_exit(void); +int cnss_genl_send_msg(void *buff, u8 type, + char *file_name, u32 total_size); +#else +static inline int cnss_genl_init(void) +{ + return 0; +} + +static inline void cnss_genl_exit(void) +{ +} + +static inline int cnss_genl_send_msg(void *buff, u8 type, + char *file_name, u32 total_size) +{ + return 0; +} +#endif + +#endif diff --git a/drivers/net/wireless/cnss2/ip_multimedia_subsystem_private_service_v01.c b/drivers/net/wireless/cnss2/ip_multimedia_subsystem_private_service_v01.c new file mode 100644 index 000000000000..5b958e9323eb --- /dev/null +++ b/drivers/net/wireless/cnss2/ip_multimedia_subsystem_private_service_v01.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */ + +#include + +#include "ip_multimedia_subsystem_private_service_v01.h" + +struct qmi_elem_info +ims_private_service_subscribe_for_indications_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + ims_private_service_subscribe_for_indications_req_msg_v01, + mt_invite_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + ims_private_service_subscribe_for_indications_req_msg_v01, + mt_invite), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + ims_private_service_subscribe_for_indications_req_msg_v01, + wfc_call_status_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + ims_private_service_subscribe_for_indications_req_msg_v01, + wfc_call_status), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info +ims_private_service_subscribe_for_indications_rsp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + ims_private_service_subscribe_for_indications_rsp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info ims_private_service_wfc_call_status_ind_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + ims_private_service_wfc_call_status_ind_msg_v01, + wfc_call_active), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; diff --git a/drivers/net/wireless/cnss2/ip_multimedia_subsystem_private_service_v01.h b/drivers/net/wireless/cnss2/ip_multimedia_subsystem_private_service_v01.h new file mode 100644 index 000000000000..582c4ff96880 --- /dev/null +++ b/drivers/net/wireless/cnss2/ip_multimedia_subsystem_private_service_v01.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */ + +#ifndef IP_MULTIMEDIA_SUBSYSTEM_PRIVATE_SERVICE_V01_H +#define IP_MULTIMEDIA_SUBSYSTEM_PRIVATE_SERVICE_V01_H + +#define IMSPRIVATE_SERVICE_ID_V01 0x4D +#define IMSPRIVATE_SERVICE_VERS_V01 0x01 + +#define IMSPRIVATE_SERVICE_MAX_MSG_LEN 8 + +#define QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_RSP_V01 0x003E +#define QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01 0x003E +#define QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01 0x0040 + +struct ims_private_service_subscribe_for_indications_req_msg_v01 { + u8 mt_invite_valid; + u8 mt_invite; + u8 wfc_call_status_valid; + u8 wfc_call_status; +}; + +#define IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN 8 +extern struct +qmi_elem_info ims_private_service_subscribe_for_indications_req_msg_v01_ei[]; + +struct ims_private_service_subscribe_for_indications_rsp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_RSP_MSG_V01_MAX_MSG_LEN 7 +extern struct +qmi_elem_info ims_private_service_subscribe_for_indications_rsp_msg_v01_ei[]; + +struct ims_private_service_wfc_call_status_ind_msg_v01 { + u8 wfc_call_active; +}; + +#define IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_MSG_V01_MAX_MSG_LEN 4 +extern struct +qmi_elem_info ims_private_service_wfc_call_status_ind_msg_v01_ei[]; + +#endif diff --git a/drivers/net/wireless/cnss2/main.c b/drivers/net/wireless/cnss2/main.c new file mode 100644 index 000000000000..2c8e6f6d760a --- /dev/null +++ b/drivers/net/wireless/cnss2/main.c @@ -0,0 +1,2131 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "main.h" +#include "bus.h" +#include "debug.h" +#include "genl.h" + +#define CNSS_DUMP_FORMAT_VER 0x11 +#define CNSS_DUMP_FORMAT_VER_V2 0x22 +#define CNSS_DUMP_MAGIC_VER_V2 0x42445953 +#define CNSS_DUMP_NAME "CNSS_WLAN" +#define CNSS_DUMP_DESC_SIZE 0x1000 +#define CNSS_DUMP_SEG_VER 0x1 +#define WLAN_RECOVERY_DELAY 1000 +#define FILE_SYSTEM_READY 1 +#define FW_READY_TIMEOUT 20000 +#define FW_ASSERT_TIMEOUT 5000 +#define CNSS_EVENT_PENDING 2989 + +#define CNSS_QUIRKS_DEFAULT 0 +#ifdef CONFIG_CNSS_EMULATION +#define CNSS_MHI_TIMEOUT_DEFAULT 90000 +#else +#define CNSS_MHI_TIMEOUT_DEFAULT 0 +#endif +#define CNSS_QMI_TIMEOUT_DEFAULT 10000 +#define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF +#define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000 + +static struct cnss_plat_data *plat_env; + +static DECLARE_RWSEM(cnss_pm_sem); + +static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = { + "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin", + "utfbd30.bin", "epping30.bin", "evicted30.bin" +}; + +static struct cnss_fw_files FW_FILES_DEFAULT = { + "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin", + "utfbd.bin", "epping.bin", "evicted.bin" +}; + +static struct cnss_bus_bw_cfg cnss_bus_bw_table[] = { + /* no vote */ + {0, 0}, + /* idle: 0-18 Mbps, ddr freq: 100 MHz */ + {2250, 400000}, + /* low: 18-60 Mbps, ddr freq: 200 MHz*/ + {7500, 800000}, + /* medium: 60-240 Mbps, ddr freq: 451.2 MHz */ + {30000, 1804800}, + /* high: 240 - 800 Mbps, ddr freq: 451.2 MHz */ + {100000, 1804800}, + /* very high: 800 - 1400 Mbps, ddr freq: 1555.2 MHz */ + {175000, 6220800}, +}; + +struct cnss_driver_event { + struct list_head list; + enum cnss_driver_event_type type; + bool sync; + struct completion complete; + int ret; + void *data; +}; + +static void cnss_set_plat_priv(struct platform_device *plat_dev, + struct cnss_plat_data *plat_priv) +{ + plat_env = plat_priv; +} + +struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev) +{ + return plat_env; +} + +static int cnss_pm_notify(struct notifier_block *b, + unsigned long event, void *p) +{ + switch (event) { + case PM_SUSPEND_PREPARE: + down_write(&cnss_pm_sem); + break; + case PM_POST_SUSPEND: + up_write(&cnss_pm_sem); + break; + } + + return NOTIFY_DONE; +} + +static struct notifier_block cnss_pm_notifier = { + .notifier_call = cnss_pm_notify, +}; + +static void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv) +{ + if (atomic_inc_return(&plat_priv->pm_count) != 1) + return; + + cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n", + plat_priv->driver_state, + atomic_read(&plat_priv->pm_count)); + pm_stay_awake(&plat_priv->plat_dev->dev); +} + +static void cnss_pm_relax(struct cnss_plat_data *plat_priv) +{ + int r = atomic_dec_return(&plat_priv->pm_count); + + WARN_ON(r < 0); + + if (r != 0) + return; + + cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n", + plat_priv->driver_state, + atomic_read(&plat_priv->pm_count)); + pm_relax(&plat_priv->plat_dev->dev); +} + +void cnss_lock_pm_sem(struct device *dev) +{ + down_read(&cnss_pm_sem); +} +EXPORT_SYMBOL(cnss_lock_pm_sem); + +void cnss_release_pm_sem(struct device *dev) +{ + up_read(&cnss_pm_sem); +} +EXPORT_SYMBOL(cnss_release_pm_sem); + +int cnss_get_fw_files_for_target(struct device *dev, + struct cnss_fw_files *pfw_files, + u32 target_type, u32 target_version) +{ + if (!pfw_files) + return -ENODEV; + + switch (target_version) { + case QCA6174_REV3_VERSION: + case QCA6174_REV3_2_VERSION: + memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files)); + break; + default: + memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files)); + cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X", + target_type, target_version); + break; + } + + return 0; +} +EXPORT_SYMBOL(cnss_get_fw_files_for_target); + +int cnss_request_bus_bandwidth(struct device *dev, int bandwidth) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + struct cnss_bus_bw_info *bus_bw_info; + + if (!plat_priv) + return -ENODEV; + + bus_bw_info = &plat_priv->bus_bw_info; + if (!bus_bw_info->cnss_path) + return -EINVAL; + + switch (bandwidth) { + case CNSS_BUS_WIDTH_NONE: + case CNSS_BUS_WIDTH_IDLE: + case CNSS_BUS_WIDTH_LOW: + case CNSS_BUS_WIDTH_MEDIUM: + case CNSS_BUS_WIDTH_HIGH: + case CNSS_BUS_WIDTH_VERY_HIGH: + ret = icc_set_bw(bus_bw_info->cnss_path, + bus_bw_table[bandwidth].ab, + bus_bw_table[bandwidth].ib); + if (!ret) + bus_bw_info->current_bw_vote = bandwidth; + else + cnss_pr_err("Could not set bus bandwidth: %d, err = %d\n", + bandwidth, ret); + break; + default: + cnss_pr_err("Invalid bus bandwidth: %d", bandwidth); + ret = -EINVAL; + } + + return ret; +} +EXPORT_SYMBOL(cnss_request_bus_bandwidth); + +int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (!plat_priv) + return -ENODEV; + + if (cap) + *cap = plat_priv->cap; + + return 0; +} +EXPORT_SYMBOL(cnss_get_platform_cap); + +void cnss_request_pm_qos(struct device *dev, u32 qos_val) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (!plat_priv) + return; + + pm_qos_add_request(&plat_priv->qos_request, PM_QOS_CPU_DMA_LATENCY, + qos_val); +} +EXPORT_SYMBOL(cnss_request_pm_qos); + +void cnss_remove_pm_qos(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (!plat_priv) + return; + + pm_qos_remove_request(&plat_priv->qos_request); +} +EXPORT_SYMBOL(cnss_remove_pm_qos); + +int cnss_wlan_enable(struct device *dev, + struct cnss_wlan_enable_cfg *config, + enum cnss_driver_mode mode, + const char *host_version) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + int ret = 0; + + if (plat_priv->device_id == QCA6174_DEVICE_ID) + return 0; + + if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) + return 0; + + if (!config || !host_version) { + cnss_pr_err("Invalid config or host_version pointer\n"); + return -EINVAL; + } + + cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n", + mode, config, host_version); + + if (mode == CNSS_WALTEST || mode == CNSS_CCPM) + goto skip_cfg; + + ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version); + if (ret) + goto out; + +skip_cfg: + ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode); +out: + return ret; +} +EXPORT_SYMBOL(cnss_wlan_enable); + +int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (plat_priv->device_id == QCA6174_DEVICE_ID) + return 0; + + if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) + return 0; + + return cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF); +} +EXPORT_SYMBOL(cnss_wlan_disable); + +int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type, + u32 data_len, u8 *output) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + int ret = 0; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL!\n"); + return -EINVAL; + } + + if (plat_priv->device_id == QCA6174_DEVICE_ID) + return 0; + + if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) { + cnss_pr_err("Invalid state for athdiag read: 0x%lx\n", + plat_priv->driver_state); + ret = -EINVAL; + goto out; + } + + ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type, + data_len, output); + +out: + return ret; +} +EXPORT_SYMBOL(cnss_athdiag_read); + +int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type, + u32 data_len, u8 *input) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + int ret = 0; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL!\n"); + return -EINVAL; + } + + if (plat_priv->device_id == QCA6174_DEVICE_ID) + return 0; + + if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) { + cnss_pr_err("Invalid state for athdiag write: 0x%lx\n", + plat_priv->driver_state); + ret = -EINVAL; + goto out; + } + + ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type, + data_len, input); + +out: + return ret; +} +EXPORT_SYMBOL(cnss_athdiag_write); + +int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (plat_priv->device_id == QCA6174_DEVICE_ID) + return 0; + + return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode); +} +EXPORT_SYMBOL(cnss_set_fw_log_mode); + +static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state); + + ret = cnss_wlfw_tgt_cap_send_sync(plat_priv); + if (ret) + goto out; + + cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB); + + ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv, + plat_priv->ctrl_params.bdf_type); + if (ret) + goto out; + + ret = cnss_bus_load_m3(plat_priv); + if (ret) + goto out; + + ret = cnss_wlfw_m3_dnld_send_sync(plat_priv); + if (ret) + goto out; + + return 0; +out: + return ret; +} + +static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + if (!plat_priv->antenna) { + ret = cnss_wlfw_antenna_switch_send_sync(plat_priv); + if (ret) + goto out; + } + + if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) { + ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv); + if (ret) + goto out; + } + + ret = cnss_wlfw_antenna_grant_send_sync(plat_priv); + if (ret) + goto out; + + return 0; + +out: + return ret; +} + +static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv) +{ + if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) + coex_antenna_switch_to_mdm_send_sync_msg(plat_priv); +} + +static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + del_timer(&plat_priv->fw_boot_timer); + set_bit(CNSS_FW_READY, &plat_priv->driver_state); + clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); + + if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) { + clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state); + clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); + } + + if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) { + ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, + CNSS_WALTEST); + } else if (test_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state)) { + cnss_request_antenna_sharing(plat_priv); + ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, + CNSS_CALIBRATION); + } else { + ret = cnss_bus_call_driver_probe(plat_priv); + } + + if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) + goto out; + else if (ret) + goto shutdown; + + cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM); + + return 0; + +shutdown: + cnss_bus_dev_shutdown(plat_priv); + + clear_bit(CNSS_FW_READY, &plat_priv->driver_state); + clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state); + +out: + return ret; +} + +static char *cnss_driver_event_to_str(enum cnss_driver_event_type type) +{ + switch (type) { + case CNSS_DRIVER_EVENT_SERVER_ARRIVE: + return "SERVER_ARRIVE"; + case CNSS_DRIVER_EVENT_SERVER_EXIT: + return "SERVER_EXIT"; + case CNSS_DRIVER_EVENT_REQUEST_MEM: + return "REQUEST_MEM"; + case CNSS_DRIVER_EVENT_FW_MEM_READY: + return "FW_MEM_READY"; + case CNSS_DRIVER_EVENT_FW_READY: + return "FW_READY"; + case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START: + return "COLD_BOOT_CAL_START"; + case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE: + return "COLD_BOOT_CAL_DONE"; + case CNSS_DRIVER_EVENT_REGISTER_DRIVER: + return "REGISTER_DRIVER"; + case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER: + return "UNREGISTER_DRIVER"; + case CNSS_DRIVER_EVENT_RECOVERY: + return "RECOVERY"; + case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT: + return "FORCE_FW_ASSERT"; + case CNSS_DRIVER_EVENT_POWER_UP: + return "POWER_UP"; + case CNSS_DRIVER_EVENT_POWER_DOWN: + return "POWER_DOWN"; + case CNSS_DRIVER_EVENT_IDLE_RESTART: + return "IDLE_RESTART"; + case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN: + return "IDLE_SHUTDOWN"; + case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM: + return "QDSS_TRACE_REQ_MEM"; + case CNSS_DRIVER_EVENT_QDSS_TRACE_SAVE: + return "QDSS_TRACE_SAVE"; + case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE: + return "QDSS_TRACE_FREE"; + case CNSS_DRIVER_EVENT_MAX: + return "EVENT_MAX"; + } + + return "UNKNOWN"; +}; + +int cnss_driver_event_post(struct cnss_plat_data *plat_priv, + enum cnss_driver_event_type type, + u32 flags, void *data) +{ + struct cnss_driver_event *event; + unsigned long irq_flags; + int gfp = GFP_KERNEL; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n", + cnss_driver_event_to_str(type), type, + flags ? "-sync" : "", plat_priv->driver_state, flags); + + if (type >= CNSS_DRIVER_EVENT_MAX) { + cnss_pr_err("Invalid Event type: %d, can't post", type); + return -EINVAL; + } + + if (in_interrupt() || irqs_disabled()) + gfp = GFP_ATOMIC; + + event = kzalloc(sizeof(*event), gfp); + if (!event) + return -ENOMEM; + + cnss_pm_stay_awake(plat_priv); + + event->type = type; + event->data = data; + init_completion(&event->complete); + event->ret = CNSS_EVENT_PENDING; + event->sync = !!(flags & CNSS_EVENT_SYNC); + + spin_lock_irqsave(&plat_priv->event_lock, irq_flags); + list_add_tail(&event->list, &plat_priv->event_list); + spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags); + + queue_work(plat_priv->event_wq, &plat_priv->event_work); + + if (!(flags & CNSS_EVENT_SYNC)) + goto out; + + if (flags & CNSS_EVENT_UNINTERRUPTIBLE) + wait_for_completion(&event->complete); + else + ret = wait_for_completion_interruptible(&event->complete); + + cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n", + cnss_driver_event_to_str(type), type, + plat_priv->driver_state, ret, event->ret); + spin_lock_irqsave(&plat_priv->event_lock, irq_flags); + if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) { + event->sync = false; + spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags); + ret = -EINTR; + goto out; + } + spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags); + + ret = event->ret; + kfree(event); + +out: + cnss_pm_relax(plat_priv); + return ret; +} + +unsigned int cnss_get_boot_timeout(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return 0; + } + + return cnss_get_qmi_timeout(plat_priv); +} +EXPORT_SYMBOL(cnss_get_boot_timeout); + +int cnss_power_up(struct device *dev) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + unsigned int timeout; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + cnss_pr_dbg("Powering up device\n"); + + ret = cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_POWER_UP, + CNSS_EVENT_SYNC, NULL); + if (ret) + goto out; + + if (plat_priv->device_id == QCA6174_DEVICE_ID) + goto out; + + timeout = cnss_get_boot_timeout(dev); + + reinit_completion(&plat_priv->power_up_complete); + ret = wait_for_completion_timeout(&plat_priv->power_up_complete, + msecs_to_jiffies(timeout) << 2); + if (!ret) { + cnss_pr_err("Timeout waiting for power up to complete\n"); + ret = -EAGAIN; + goto out; + } + + return 0; + +out: + return ret; +} +EXPORT_SYMBOL(cnss_power_up); + +int cnss_power_down(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + cnss_pr_dbg("Powering down device\n"); + + return cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_POWER_DOWN, + CNSS_EVENT_SYNC, NULL); +} +EXPORT_SYMBOL(cnss_power_down); + +int cnss_idle_restart(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + unsigned int timeout; + int ret = 0; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + cnss_pr_dbg("Doing idle restart\n"); + + ret = cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_IDLE_RESTART, + CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL); + if (ret) + goto out; + + if (plat_priv->device_id == QCA6174_DEVICE_ID) { + ret = cnss_bus_call_driver_probe(plat_priv); + goto out; + } + + timeout = cnss_get_boot_timeout(dev); + + reinit_completion(&plat_priv->power_up_complete); + ret = wait_for_completion_timeout(&plat_priv->power_up_complete, + msecs_to_jiffies(timeout) << 2); + if (!ret) { + cnss_pr_err("Timeout waiting for idle restart to complete\n"); + ret = -EAGAIN; + goto out; + } + + return 0; + +out: + return ret; +} +EXPORT_SYMBOL(cnss_idle_restart); + +int cnss_idle_shutdown(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + int ret; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) { + cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n"); + return -EAGAIN; + } + + cnss_pr_dbg("Doing idle shutdown\n"); + + if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) && + !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) + goto skip_wait; + + reinit_completion(&plat_priv->recovery_complete); + ret = wait_for_completion_timeout(&plat_priv->recovery_complete, + RECOVERY_TIMEOUT); + if (!ret) { + cnss_pr_err("Timeout waiting for recovery to complete\n"); + CNSS_ASSERT(0); + } + +skip_wait: + return cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_IDLE_SHUTDOWN, + CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL); +} +EXPORT_SYMBOL(cnss_idle_shutdown); + +static int cnss_get_resources(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM); + if (ret) { + cnss_pr_err("Failed to get vreg, err = %d\n", ret); + goto out; + } + + ret = cnss_get_clk(plat_priv); + if (ret) { + cnss_pr_err("Failed to get clocks, err = %d\n", ret); + goto put_vreg; + } + + ret = cnss_get_pinctrl(plat_priv); + if (ret) { + cnss_pr_err("Failed to get pinctrl, err = %d\n", ret); + goto put_clk; + } + + return 0; + +put_clk: + cnss_put_clk(plat_priv); +put_vreg: + cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM); +out: + return ret; +} + +static void cnss_put_resources(struct cnss_plat_data *plat_priv) +{ + cnss_put_clk(plat_priv); + cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM); +} + +static int cnss_modem_notifier_nb(struct notifier_block *nb, + unsigned long code, + void *ss_handle) +{ + struct cnss_plat_data *plat_priv = + container_of(nb, struct cnss_plat_data, modem_nb); + struct cnss_esoc_info *esoc_info; + + cnss_pr_dbg("Modem notifier: event %lu\n", code); + + if (!plat_priv) + return NOTIFY_DONE; + + esoc_info = &plat_priv->esoc_info; + + if (code == SUBSYS_AFTER_POWERUP) + esoc_info->modem_current_status = 1; + else if (code == SUBSYS_BEFORE_SHUTDOWN) + esoc_info->modem_current_status = 0; + else + return NOTIFY_DONE; + + if (!cnss_bus_call_driver_modem_status(plat_priv, + esoc_info->modem_current_status)) + return NOTIFY_DONE; + + return NOTIFY_OK; +} + +static int cnss_register_esoc(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + struct device *dev; + struct cnss_esoc_info *esoc_info; + struct esoc_desc *esoc_desc; + const char *client_desc; + + dev = &plat_priv->plat_dev->dev; + esoc_info = &plat_priv->esoc_info; + + esoc_info->notify_modem_status = + of_property_read_bool(dev->of_node, + "qcom,notify-modem-status"); + + if (!esoc_info->notify_modem_status) + goto out; + + ret = of_property_read_string_index(dev->of_node, "esoc-names", 0, + &client_desc); + if (ret) { + cnss_pr_dbg("esoc-names is not defined in DT, skip!\n"); + } else { + esoc_desc = devm_register_esoc_client(dev, client_desc); + if (IS_ERR_OR_NULL(esoc_desc)) { + ret = PTR_RET(esoc_desc); + cnss_pr_err("Failed to register esoc_desc, err = %d\n", + ret); + goto out; + } + esoc_info->esoc_desc = esoc_desc; + } + + plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb; + esoc_info->modem_current_status = 0; + esoc_info->modem_notify_handler = + subsys_notif_register_notifier(esoc_info->esoc_desc ? + esoc_info->esoc_desc->name : + "modem", &plat_priv->modem_nb); + if (IS_ERR(esoc_info->modem_notify_handler)) { + ret = PTR_ERR(esoc_info->modem_notify_handler); + cnss_pr_err("Failed to register esoc notifier, err = %d\n", + ret); + goto unreg_esoc; + } + + return 0; +unreg_esoc: + if (esoc_info->esoc_desc) + devm_unregister_esoc_client(dev, esoc_info->esoc_desc); +out: + return ret; +} + +static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) +{ + struct device *dev; + struct cnss_esoc_info *esoc_info; + + dev = &plat_priv->plat_dev->dev; + esoc_info = &plat_priv->esoc_info; + + if (esoc_info->notify_modem_status) + subsys_notif_unregister_notifier + (esoc_info->modem_notify_handler, + &plat_priv->modem_nb); + if (esoc_info->esoc_desc) + devm_unregister_esoc_client(dev, esoc_info->esoc_desc); +} + +static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc) +{ + struct cnss_plat_data *plat_priv; + + if (!subsys_desc->dev) { + cnss_pr_err("dev from subsys_desc is NULL\n"); + return -ENODEV; + } + + plat_priv = dev_get_drvdata(subsys_desc->dev); + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + if (!plat_priv->driver_state) { + cnss_pr_dbg("Powerup is ignored\n"); + return 0; + } + + return cnss_bus_dev_powerup(plat_priv); +} + +static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc, + bool force_stop) +{ + struct cnss_plat_data *plat_priv; + + if (!subsys_desc->dev) { + cnss_pr_err("dev from subsys_desc is NULL\n"); + return -ENODEV; + } + + plat_priv = dev_get_drvdata(subsys_desc->dev); + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + if (!plat_priv->driver_state) { + cnss_pr_dbg("shutdown is ignored\n"); + return 0; + } + + return cnss_bus_dev_shutdown(plat_priv); +} + +void cnss_device_crashed(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + struct cnss_subsys_info *subsys_info; + + if (!plat_priv) + return; + + subsys_info = &plat_priv->subsys_info; + if (subsys_info->subsys_device) { + set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); + subsys_set_crash_status(subsys_info->subsys_device, true); + subsystem_restart_dev(subsys_info->subsys_device); + } +} +EXPORT_SYMBOL(cnss_device_crashed); + +static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc) +{ + struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev); + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return; + } + + cnss_bus_dev_crash_shutdown(plat_priv); +} + +static int cnss_subsys_ramdump(int enable, + const struct subsys_desc *subsys_desc) +{ + struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev); + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + if (!enable) + return 0; + + return cnss_bus_dev_ramdump(plat_priv); +} + +void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + struct cnss_ramdump_info *ramdump_info; + + if (!plat_priv) + return NULL; + + ramdump_info = &plat_priv->ramdump_info; + *size = ramdump_info->ramdump_size; + + return ramdump_info->ramdump_va; +} +EXPORT_SYMBOL(cnss_get_virt_ramdump_mem); + +static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason) +{ + switch (reason) { + case CNSS_REASON_DEFAULT: + return "DEFAULT"; + case CNSS_REASON_LINK_DOWN: + return "LINK_DOWN"; + case CNSS_REASON_RDDM: + return "RDDM"; + case CNSS_REASON_TIMEOUT: + return "TIMEOUT"; + } + + return "UNKNOWN"; +}; + +static int cnss_do_recovery(struct cnss_plat_data *plat_priv, + enum cnss_recovery_reason reason) +{ + struct cnss_subsys_info *subsys_info = + &plat_priv->subsys_info; + + plat_priv->recovery_count++; + + if (plat_priv->device_id == QCA6174_DEVICE_ID) + goto self_recovery; + + if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) { + cnss_pr_dbg("Skip device recovery\n"); + return 0; + } + + switch (reason) { + case CNSS_REASON_LINK_DOWN: + if (test_bit(LINK_DOWN_SELF_RECOVERY, + &plat_priv->ctrl_params.quirks)) + goto self_recovery; + break; + case CNSS_REASON_RDDM: + cnss_bus_collect_dump_info(plat_priv, false); + break; + case CNSS_REASON_DEFAULT: + case CNSS_REASON_TIMEOUT: + break; + default: + cnss_pr_err("Unsupported recovery reason: %s(%d)\n", + cnss_recovery_reason_to_str(reason), reason); + break; + } + + if (!subsys_info->subsys_device) + return 0; + + subsys_set_crash_status(subsys_info->subsys_device, true); + subsystem_restart_dev(subsys_info->subsys_device); + + return 0; + +self_recovery: + cnss_bus_dev_shutdown(plat_priv); + cnss_bus_dev_powerup(plat_priv); + + return 0; +} + +static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv, + void *data) +{ + struct cnss_recovery_data *recovery_data = data; + int ret = 0; + + cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n", + cnss_recovery_reason_to_str(recovery_data->reason), + recovery_data->reason); + + if (!plat_priv->driver_state) { + cnss_pr_err("Improper driver state, ignore recovery\n"); + ret = -EINVAL; + goto out; + } + + if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) { + cnss_pr_err("Recovery is already in progress\n"); + ret = -EINVAL; + goto out; + } + + if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) { + cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n"); + ret = -EINVAL; + goto out; + } + + switch (plat_priv->device_id) { + case QCA6174_DEVICE_ID: + if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_IDLE_RESTART, + &plat_priv->driver_state)) { + cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n"); + ret = -EINVAL; + goto out; + } + break; + default: + if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) { + set_bit(CNSS_FW_BOOT_RECOVERY, + &plat_priv->driver_state); + } + break; + } + + set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); + ret = cnss_do_recovery(plat_priv, recovery_data->reason); + +out: + kfree(data); + return ret; +} + +int cnss_self_recovery(struct device *dev, + enum cnss_recovery_reason reason) +{ + cnss_schedule_recovery(dev, reason); + return 0; +} +EXPORT_SYMBOL(cnss_self_recovery); + +void cnss_schedule_recovery(struct device *dev, + enum cnss_recovery_reason reason) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + struct cnss_recovery_data *data; + int gfp = GFP_KERNEL; + + cnss_bus_update_status(plat_priv, CNSS_FW_DOWN); + + if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) { + cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n"); + return; + } + + if (in_interrupt() || irqs_disabled()) + gfp = GFP_ATOMIC; + + data = kzalloc(sizeof(*data), gfp); + if (!data) + return; + + data->reason = reason; + cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_RECOVERY, + 0, data); +} +EXPORT_SYMBOL(cnss_schedule_recovery); + +int cnss_force_fw_assert(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + if (plat_priv->device_id == QCA6174_DEVICE_ID) { + cnss_pr_info("Forced FW assert is not supported\n"); + return -EOPNOTSUPP; + } + + if (cnss_pci_is_device_down(dev)) { + cnss_pr_info("Device is already in bad state, ignore force assert\n"); + return 0; + } + + if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) { + cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n"); + return 0; + } + + if (in_interrupt() || irqs_disabled()) + cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_FORCE_FW_ASSERT, + 0, NULL); + else + cnss_bus_force_fw_assert_hdlr(plat_priv); + + return 0; +} +EXPORT_SYMBOL(cnss_force_fw_assert); + +int cnss_force_collect_rddm(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + int ret = 0; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + if (plat_priv->device_id == QCA6174_DEVICE_ID) { + cnss_pr_info("Force collect rddm is not supported\n"); + return -EOPNOTSUPP; + } + + if (cnss_pci_is_device_down(dev)) { + cnss_pr_info("Device is already in bad state, ignore force collect rddm\n"); + return 0; + } + + if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) { + cnss_pr_info("Recovery is already in progress, ignore forced collect rddm\n"); + return 0; + } + + if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) { + cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n"); + return 0; + } + + ret = cnss_bus_force_fw_assert_hdlr(plat_priv); + if (ret) + return ret; + + reinit_completion(&plat_priv->rddm_complete); + ret = wait_for_completion_timeout + (&plat_priv->rddm_complete, + msecs_to_jiffies(CNSS_RDDM_TIMEOUT_MS)); + if (!ret) + ret = -ETIMEDOUT; + + return ret; +} +EXPORT_SYMBOL(cnss_force_collect_rddm); + +static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + if (test_bit(CNSS_FW_READY, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state)) { + cnss_pr_dbg("Device is already active, ignore calibration\n"); + goto out; + } + + set_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state); + reinit_completion(&plat_priv->cal_complete); + ret = cnss_bus_dev_powerup(plat_priv); + if (ret) { + complete(&plat_priv->cal_complete); + clear_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state); + } + +out: + return ret; +} + +static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv, + void *data) +{ + struct cnss_cal_info *cal_info = data; + + if (!test_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state)) + goto out; + + switch (cal_info->cal_status) { + case CNSS_CAL_DONE: + cnss_pr_dbg("Calibration completed successfully\n"); + plat_priv->cal_done = true; + break; + case CNSS_CAL_TIMEOUT: + cnss_pr_dbg("Calibration timed out, force shutdown\n"); + break; + default: + cnss_pr_err("Unknown calibration status: %u\n", + cal_info->cal_status); + break; + } + + cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF); + cnss_release_antenna_sharing(plat_priv); + cnss_bus_dev_shutdown(plat_priv); + complete(&plat_priv->cal_complete); + clear_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state); + +out: + kfree(data); + return 0; +} + +static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv) +{ + int ret; + + ret = cnss_bus_dev_powerup(plat_priv); + if (ret) + clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state); + + return ret; +} + +static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv) +{ + cnss_bus_dev_shutdown(plat_priv); + + return 0; +} + +static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + ret = cnss_bus_alloc_qdss_mem(plat_priv); + if (ret < 0) + return ret; + + return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv); +} + +static void *cnss_qdss_trace_pa_to_va(struct cnss_plat_data *plat_priv, + u64 pa, u32 size, int *seg_id) +{ + int i = 0; + struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem; + u64 offset = 0; + void *va = NULL; + u64 local_pa; + u32 local_size; + + for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) { + local_pa = (u64)qdss_mem[i].pa; + local_size = (u32)qdss_mem[i].size; + if (pa == local_pa && size <= local_size) { + va = qdss_mem[i].va; + break; + } + if (pa > local_pa && + pa < local_pa + local_size && + pa + size <= local_pa + local_size) { + offset = pa - local_pa; + va = qdss_mem[i].va + offset; + break; + } + } + + *seg_id = i; + return va; +} + +static int cnss_qdss_trace_save_hdlr(struct cnss_plat_data *plat_priv, + void *data) +{ + struct cnss_qmi_event_qdss_trace_save_data *event_data = data; + struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem; + int ret = 0; + int i; + void *va = NULL; + u64 pa; + u32 size; + int seg_id = 0; + + if (!plat_priv->qdss_mem_seg_len) { + cnss_pr_err("Memory for QDSS trace is not available\n"); + return -ENOMEM; + } + + if (event_data->mem_seg_len == 0) { + for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) { + ret = cnss_genl_send_msg(qdss_mem[i].va, + CNSS_GENL_MSG_TYPE_QDSS, + event_data->file_name, + qdss_mem[i].size); + if (ret < 0) { + cnss_pr_err("Fail to save QDSS data: %d\n", + ret); + break; + } + } + } else { + for (i = 0; i < event_data->mem_seg_len; i++) { + pa = event_data->mem_seg[i].addr; + size = event_data->mem_seg[i].size; + va = cnss_qdss_trace_pa_to_va(plat_priv, pa, + size, &seg_id); + if (!va) { + cnss_pr_err("Fail to find matching va for pa %pa\n", + &pa); + ret = -EINVAL; + break; + } + ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS, + event_data->file_name, size); + if (ret < 0) { + cnss_pr_err("Fail to save QDSS data: %d\n", + ret); + break; + } + } + } + + kfree(data); + return ret; +} + +static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv) +{ + cnss_bus_free_qdss_mem(plat_priv); + + return 0; +} + +static void cnss_driver_event_work(struct work_struct *work) +{ + struct cnss_plat_data *plat_priv = + container_of(work, struct cnss_plat_data, event_work); + struct cnss_driver_event *event; + unsigned long flags; + int ret = 0; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL!\n"); + return; + } + + cnss_pm_stay_awake(plat_priv); + + spin_lock_irqsave(&plat_priv->event_lock, flags); + + while (!list_empty(&plat_priv->event_list)) { + event = list_first_entry(&plat_priv->event_list, + struct cnss_driver_event, list); + list_del(&event->list); + spin_unlock_irqrestore(&plat_priv->event_lock, flags); + + cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n", + cnss_driver_event_to_str(event->type), + event->sync ? "-sync" : "", event->type, + plat_priv->driver_state); + + switch (event->type) { + case CNSS_DRIVER_EVENT_SERVER_ARRIVE: + ret = cnss_wlfw_server_arrive(plat_priv, event->data); + break; + case CNSS_DRIVER_EVENT_SERVER_EXIT: + ret = cnss_wlfw_server_exit(plat_priv); + break; + case CNSS_DRIVER_EVENT_REQUEST_MEM: + ret = cnss_bus_alloc_fw_mem(plat_priv); + if (ret) + break; + ret = cnss_wlfw_respond_mem_send_sync(plat_priv); + break; + case CNSS_DRIVER_EVENT_FW_MEM_READY: + ret = cnss_fw_mem_ready_hdlr(plat_priv); + break; + case CNSS_DRIVER_EVENT_FW_READY: + ret = cnss_fw_ready_hdlr(plat_priv); + break; + case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START: + ret = cnss_cold_boot_cal_start_hdlr(plat_priv); + break; + case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE: + ret = cnss_cold_boot_cal_done_hdlr(plat_priv, + event->data); + break; + case CNSS_DRIVER_EVENT_REGISTER_DRIVER: + ret = cnss_bus_register_driver_hdlr(plat_priv, + event->data); + break; + case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER: + ret = cnss_bus_unregister_driver_hdlr(plat_priv); + break; + case CNSS_DRIVER_EVENT_RECOVERY: + ret = cnss_driver_recovery_hdlr(plat_priv, + event->data); + break; + case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT: + ret = cnss_bus_force_fw_assert_hdlr(plat_priv); + break; + case CNSS_DRIVER_EVENT_IDLE_RESTART: + set_bit(CNSS_DRIVER_IDLE_RESTART, + &plat_priv->driver_state); + /* fall through */ + case CNSS_DRIVER_EVENT_POWER_UP: + ret = cnss_power_up_hdlr(plat_priv); + break; + case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN: + set_bit(CNSS_DRIVER_IDLE_SHUTDOWN, + &plat_priv->driver_state); + /* fall through */ + case CNSS_DRIVER_EVENT_POWER_DOWN: + ret = cnss_power_down_hdlr(plat_priv); + break; + case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM: + ret = cnss_qdss_trace_req_mem_hdlr(plat_priv); + break; + case CNSS_DRIVER_EVENT_QDSS_TRACE_SAVE: + ret = cnss_qdss_trace_save_hdlr(plat_priv, + event->data); + break; + case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE: + ret = cnss_qdss_trace_free_hdlr(plat_priv); + break; + default: + cnss_pr_err("Invalid driver event type: %d", + event->type); + kfree(event); + spin_lock_irqsave(&plat_priv->event_lock, flags); + continue; + } + + spin_lock_irqsave(&plat_priv->event_lock, flags); + if (event->sync) { + event->ret = ret; + complete(&event->complete); + continue; + } + spin_unlock_irqrestore(&plat_priv->event_lock, flags); + + kfree(event); + + spin_lock_irqsave(&plat_priv->event_lock, flags); + } + spin_unlock_irqrestore(&plat_priv->event_lock, flags); + + cnss_pm_relax(plat_priv); +} + +int cnss_register_subsys(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + struct cnss_subsys_info *subsys_info; + + subsys_info = &plat_priv->subsys_info; + + subsys_info->subsys_desc.name = "wlan"; + subsys_info->subsys_desc.owner = THIS_MODULE; + subsys_info->subsys_desc.powerup = cnss_subsys_powerup; + subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown; + subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump; + subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown; + subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev; + + subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc); + if (IS_ERR(subsys_info->subsys_device)) { + ret = PTR_ERR(subsys_info->subsys_device); + cnss_pr_err("Failed to register subsys, err = %d\n", ret); + goto out; + } + + subsys_info->subsys_handle = + subsystem_get(subsys_info->subsys_desc.name); + if (!subsys_info->subsys_handle) { + cnss_pr_err("Failed to get subsys_handle!\n"); + ret = -EINVAL; + goto unregister_subsys; + } else if (IS_ERR(subsys_info->subsys_handle)) { + ret = PTR_ERR(subsys_info->subsys_handle); + cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret); + goto unregister_subsys; + } + + return 0; + +unregister_subsys: + subsys_unregister(subsys_info->subsys_device); +out: + return ret; +} + +void cnss_unregister_subsys(struct cnss_plat_data *plat_priv) +{ + struct cnss_subsys_info *subsys_info; + + subsys_info = &plat_priv->subsys_info; + subsystem_put(subsys_info->subsys_handle); + subsys_unregister(subsys_info->subsys_device); +} + +static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv) +{ + struct cnss_ramdump_info *ramdump_info; + struct msm_dump_entry dump_entry; + + ramdump_info = &plat_priv->ramdump_info; + ramdump_info->dump_data.addr = ramdump_info->ramdump_pa; + ramdump_info->dump_data.len = ramdump_info->ramdump_size; + ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER; + ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2; + strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME, + sizeof(ramdump_info->dump_data.name)); + dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN; + dump_entry.addr = virt_to_phys(&ramdump_info->dump_data); + + return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS, + &dump_entry); +} + +static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + struct device *dev; + struct cnss_subsys_info *subsys_info; + struct cnss_ramdump_info *ramdump_info; + u32 ramdump_size = 0; + + dev = &plat_priv->plat_dev->dev; + subsys_info = &plat_priv->subsys_info; + ramdump_info = &plat_priv->ramdump_info; + + if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic", + &ramdump_size) == 0) { + ramdump_info->ramdump_va = + dma_alloc_coherent(dev, ramdump_size, + &ramdump_info->ramdump_pa, + GFP_KERNEL); + + if (ramdump_info->ramdump_va) + ramdump_info->ramdump_size = ramdump_size; + } + + cnss_pr_dbg("ramdump va: %pK, pa: %pa\n", + ramdump_info->ramdump_va, &ramdump_info->ramdump_pa); + + if (ramdump_info->ramdump_size == 0) { + cnss_pr_info("Ramdump will not be collected"); + goto out; + } + + ret = cnss_init_dump_entry(plat_priv); + if (ret) { + cnss_pr_err("Failed to setup dump table, err = %d\n", ret); + goto free_ramdump; + } + + ramdump_info->ramdump_dev = + create_ramdump_device(subsys_info->subsys_desc.name, + subsys_info->subsys_desc.dev); + if (!ramdump_info->ramdump_dev) { + cnss_pr_err("Failed to create ramdump device!"); + ret = -ENOMEM; + goto free_ramdump; + } + + return 0; +free_ramdump: + dma_free_coherent(dev, ramdump_info->ramdump_size, + ramdump_info->ramdump_va, ramdump_info->ramdump_pa); +out: + return ret; +} + +static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv) +{ + struct device *dev; + struct cnss_ramdump_info *ramdump_info; + + dev = &plat_priv->plat_dev->dev; + ramdump_info = &plat_priv->ramdump_info; + + if (ramdump_info->ramdump_dev) + destroy_ramdump_device(ramdump_info->ramdump_dev); + + if (ramdump_info->ramdump_va) + dma_free_coherent(dev, ramdump_info->ramdump_size, + ramdump_info->ramdump_va, + ramdump_info->ramdump_pa); +} + +static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + struct cnss_subsys_info *subsys_info; + struct cnss_ramdump_info_v2 *info_v2; + struct cnss_dump_data *dump_data; + struct msm_dump_entry dump_entry; + struct device *dev = &plat_priv->plat_dev->dev; + u32 ramdump_size = 0; + + subsys_info = &plat_priv->subsys_info; + info_v2 = &plat_priv->ramdump_info_v2; + dump_data = &info_v2->dump_data; + + if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic", + &ramdump_size) == 0) + info_v2->ramdump_size = ramdump_size; + + cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size); + + info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL); + if (!info_v2->dump_data_vaddr) + return -ENOMEM; + + dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr); + dump_data->version = CNSS_DUMP_FORMAT_VER_V2; + dump_data->magic = CNSS_DUMP_MAGIC_VER_V2; + dump_data->seg_version = CNSS_DUMP_SEG_VER; + strlcpy(dump_data->name, CNSS_DUMP_NAME, + sizeof(dump_data->name)); + dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN; + dump_entry.addr = virt_to_phys(dump_data); + + ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS, + &dump_entry); + if (ret) { + cnss_pr_err("Failed to setup dump table, err = %d\n", ret); + goto free_ramdump; + } + + info_v2->ramdump_dev = + create_ramdump_device(subsys_info->subsys_desc.name, + subsys_info->subsys_desc.dev); + if (!info_v2->ramdump_dev) { + cnss_pr_err("Failed to create ramdump device!\n"); + ret = -ENOMEM; + goto free_ramdump; + } + + return 0; + +free_ramdump: + kfree(info_v2->dump_data_vaddr); + info_v2->dump_data_vaddr = NULL; + return ret; +} + +static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv) +{ + struct cnss_ramdump_info_v2 *info_v2; + + info_v2 = &plat_priv->ramdump_info_v2; + + if (info_v2->ramdump_dev) + destroy_ramdump_device(info_v2->ramdump_dev); + + kfree(info_v2->dump_data_vaddr); + info_v2->dump_data_vaddr = NULL; + info_v2->dump_data_valid = false; +} + +int cnss_register_ramdump(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + switch (plat_priv->device_id) { + case QCA6174_DEVICE_ID: + ret = cnss_register_ramdump_v1(plat_priv); + break; + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + ret = cnss_register_ramdump_v2(plat_priv); + break; + default: + cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id); + ret = -ENODEV; + break; + } + return ret; +} + +void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv) +{ + switch (plat_priv->device_id) { + case QCA6174_DEVICE_ID: + cnss_unregister_ramdump_v1(plat_priv); + break; + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + cnss_unregister_ramdump_v2(plat_priv); + break; + default: + cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id); + break; + } +} + +static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + struct cnss_bus_bw_info *bus_bw_info; + + bus_bw_info = &plat_priv->bus_bw_info; + + bus_bw_info->cnss_path = + of_icc_get(&plat_priv->plat_dev->dev, NULL); + if (IS_ERR(bus_bw_info->cnss_path)) { + ret = PTR_ERR(bus_bw_info->cnss_path); + if (ret != -EPROBE_DEFER) { + cnss_pr_err("Failed to get bus path: %d!\n", ret); + goto out; + } + } + + return 0; +out: + return ret; +} + +static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) +{ + struct cnss_bus_bw_info *bus_bw_info; + + bus_bw_info = &plat_priv->bus_bw_info; + + if (bus_bw_info->cnss_path) + icc_put(bus_bw_info->cnss_path); +} + +static ssize_t fs_ready_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int fs_ready = 0; + struct cnss_plat_data *plat_priv = dev_get_drvdata(dev); + + if (sscanf(buf, "%du", &fs_ready) != 1) + return -EINVAL; + + cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n", + fs_ready, count); + + if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) { + cnss_pr_dbg("QMI is bypassed.\n"); + return count; + } + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL!\n"); + return count; + } + + switch (plat_priv->device_id) { + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + break; + default: + cnss_pr_err("Not supported for device ID 0x%lx\n", + plat_priv->device_id); + return count; + } + + if (fs_ready == FILE_SYSTEM_READY) { + cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START, + CNSS_EVENT_SYNC, NULL); + } + + return count; +} + +static DEVICE_ATTR_WO(fs_ready); + +static int cnss_create_sysfs(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + ret = device_create_file(&plat_priv->plat_dev->dev, &dev_attr_fs_ready); + if (ret) { + cnss_pr_err("Failed to create device file, err = %d\n", ret); + goto out; + } + + return 0; +out: + return ret; +} + +static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv) +{ + device_remove_file(&plat_priv->plat_dev->dev, &dev_attr_fs_ready); +} + +static int cnss_event_work_init(struct cnss_plat_data *plat_priv) +{ + spin_lock_init(&plat_priv->event_lock); + plat_priv->event_wq = alloc_workqueue("cnss_driver_event", + WQ_UNBOUND, 1); + if (!plat_priv->event_wq) { + cnss_pr_err("Failed to create event workqueue!\n"); + return -EFAULT; + } + + INIT_WORK(&plat_priv->event_work, cnss_driver_event_work); + INIT_LIST_HEAD(&plat_priv->event_list); + + return 0; +} + +static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv) +{ + destroy_workqueue(plat_priv->event_wq); +} + +static int cnss_misc_init(struct cnss_plat_data *plat_priv) +{ + int ret; + + timer_setup(&plat_priv->fw_boot_timer, + cnss_bus_fw_boot_timeout_hdlr, 0); + + register_pm_notifier(&cnss_pm_notifier); + + ret = device_init_wakeup(&plat_priv->plat_dev->dev, true); + if (ret) + cnss_pr_err("Failed to init platform device wakeup source, err = %d\n", + ret); + + init_completion(&plat_priv->power_up_complete); + init_completion(&plat_priv->cal_complete); + init_completion(&plat_priv->rddm_complete); + init_completion(&plat_priv->recovery_complete); + mutex_init(&plat_priv->dev_lock); + + return 0; +} + +static void cnss_misc_deinit(struct cnss_plat_data *plat_priv) +{ + complete_all(&plat_priv->recovery_complete); + complete_all(&plat_priv->rddm_complete); + complete_all(&plat_priv->cal_complete); + complete_all(&plat_priv->power_up_complete); + device_init_wakeup(&plat_priv->plat_dev->dev, false); + unregister_pm_notifier(&cnss_pm_notifier); + del_timer(&plat_priv->fw_boot_timer); +} + +static void cnss_init_control_params(struct cnss_plat_data *plat_priv) +{ + plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT; + plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT; + plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT; + plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT; + plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT; +} + +static const struct platform_device_id cnss_platform_id_table[] = { + { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, }, + { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, }, + { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, }, + { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, }, + { }, +}; + +static const struct of_device_id cnss_of_match_table[] = { + { + .compatible = "qcom,cnss", + .data = (void *)&cnss_platform_id_table[0]}, + { + .compatible = "qcom,cnss-qca6290", + .data = (void *)&cnss_platform_id_table[1]}, + { + .compatible = "qcom,cnss-qca6390", + .data = (void *)&cnss_platform_id_table[2]}, + { + .compatible = "qcom,cnss-qca6490", + .data = (void *)&cnss_platform_id_table[3]}, + { }, +}; +MODULE_DEVICE_TABLE(of, cnss_of_match_table); + +static int cnss_probe(struct platform_device *plat_dev) +{ + int ret = 0; + struct cnss_plat_data *plat_priv; + const struct of_device_id *of_id; + const struct platform_device_id *device_id; + + if (cnss_get_plat_priv(plat_dev)) { + cnss_pr_err("Driver is already initialized!\n"); + ret = -EEXIST; + goto out; + } + + of_id = of_match_device(cnss_of_match_table, &plat_dev->dev); + if (!of_id || !of_id->data) { + cnss_pr_err("Failed to find of match device!\n"); + ret = -ENODEV; + goto out; + } + + device_id = of_id->data; + + plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv), + GFP_KERNEL); + if (!plat_priv) { + ret = -ENOMEM; + goto out; + } + + plat_priv->plat_dev = plat_dev; + plat_priv->device_id = device_id->driver_data; + plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id); + cnss_set_plat_priv(plat_dev, plat_priv); + platform_set_drvdata(plat_dev, plat_priv); + INIT_LIST_HEAD(&plat_priv->vreg_list); + INIT_LIST_HEAD(&plat_priv->clk_list); + + cnss_get_cpr_info(plat_priv); + cnss_init_control_params(plat_priv); + + ret = cnss_get_resources(plat_priv); + if (ret) + goto reset_ctx; + + if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) { + ret = cnss_power_on_device(plat_priv); + if (ret) + goto free_res; + + ret = cnss_bus_init(plat_priv); + if (ret) + goto power_off; + } + + ret = cnss_register_esoc(plat_priv); + if (ret) + goto deinit_bus; + + ret = cnss_register_bus_scale(plat_priv); + if (ret) + goto unreg_esoc; + + ret = cnss_create_sysfs(plat_priv); + if (ret) + goto unreg_bus_scale; + + ret = cnss_event_work_init(plat_priv); + if (ret) + goto remove_sysfs; + + ret = cnss_qmi_init(plat_priv); + if (ret) + goto deinit_event_work; + + ret = cnss_debugfs_create(plat_priv); + if (ret) + goto deinit_qmi; + + ret = cnss_misc_init(plat_priv); + if (ret) + goto destroy_debugfs; + + cnss_register_coex_service(plat_priv); + cnss_register_ims_service(plat_priv); + + ret = cnss_genl_init(); + if (ret < 0) + cnss_pr_err("CNSS genl init failed %d\n", ret); + + cnss_pr_info("Platform driver probed successfully.\n"); + + return 0; + +destroy_debugfs: + cnss_debugfs_destroy(plat_priv); +deinit_qmi: + cnss_qmi_deinit(plat_priv); +deinit_event_work: + cnss_event_work_deinit(plat_priv); +remove_sysfs: + cnss_remove_sysfs(plat_priv); +unreg_bus_scale: + cnss_unregister_bus_scale(plat_priv); +unreg_esoc: + cnss_unregister_esoc(plat_priv); +deinit_bus: + if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) + cnss_bus_deinit(plat_priv); +power_off: + if (!test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks)) + cnss_power_off_device(plat_priv); +free_res: + cnss_put_resources(plat_priv); +reset_ctx: + platform_set_drvdata(plat_dev, NULL); + cnss_set_plat_priv(plat_dev, NULL); +out: + return ret; +} + +static int cnss_remove(struct platform_device *plat_dev) +{ + struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev); + + cnss_genl_exit(); + cnss_unregister_ims_service(plat_priv); + cnss_unregister_coex_service(plat_priv); + cnss_misc_deinit(plat_priv); + cnss_debugfs_destroy(plat_priv); + cnss_qmi_deinit(plat_priv); + cnss_event_work_deinit(plat_priv); + cnss_remove_sysfs(plat_priv); + cnss_unregister_bus_scale(plat_priv); + cnss_unregister_esoc(plat_priv); + cnss_bus_deinit(plat_priv); + cnss_put_resources(plat_priv); + platform_set_drvdata(plat_dev, NULL); + plat_env = NULL; + + return 0; +} + +static struct platform_driver cnss_platform_driver = { + .probe = cnss_probe, + .remove = cnss_remove, + .driver = { + .name = "cnss2", + .of_match_table = cnss_of_match_table, +#ifdef CONFIG_CNSS_ASYNC + .probe_type = PROBE_PREFER_ASYNCHRONOUS, +#endif + }, +}; + +static int __init cnss_initialize(void) +{ + int ret = 0; + + cnss_debug_init(); + ret = platform_driver_register(&cnss_platform_driver); + if (ret) + cnss_debug_deinit(); + + return ret; +} + +static void __exit cnss_exit(void) +{ + platform_driver_unregister(&cnss_platform_driver); + cnss_debug_deinit(); +} + +module_init(cnss_initialize); +module_exit(cnss_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("CNSS2 Platform Driver"); diff --git a/drivers/net/wireless/cnss2/main.h b/drivers/net/wireless/cnss2/main.h new file mode 100644 index 000000000000..9bd16857140f --- /dev/null +++ b/drivers/net/wireless/cnss2/main.h @@ -0,0 +1,408 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ + +#ifndef _CNSS_MAIN_H +#define _CNSS_MAIN_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qmi.h" + +#define MAX_NO_OF_MAC_ADDR 4 +#define QMI_WLFW_MAX_TIMESTAMP_LEN 32 +#define QMI_WLFW_MAX_NUM_MEM_SEG 32 +#define CNSS_RDDM_TIMEOUT_MS 20000 +#define RECOVERY_TIMEOUT 60000 +#define TIME_CLOCK_FREQ_HZ 19200000 + +#define CNSS_EVENT_SYNC BIT(0) +#define CNSS_EVENT_UNINTERRUPTIBLE BIT(1) +#define CNSS_EVENT_SYNC_UNINTERRUPTIBLE (CNSS_EVENT_SYNC | \ + CNSS_EVENT_UNINTERRUPTIBLE) + +enum cnss_dev_bus_type { + CNSS_BUS_NONE = -1, + CNSS_BUS_PCI, +}; + +struct cnss_vreg_cfg { + const char *name; + u32 min_uv; + u32 max_uv; + u32 load_ua; + u32 delay_us; + u32 need_unvote; +}; + +struct cnss_vreg_info { + struct list_head list; + struct regulator *reg; + struct cnss_vreg_cfg cfg; + u32 enabled; +}; + +enum cnss_vreg_type { + CNSS_VREG_PRIM, +}; + +struct cnss_clk_cfg { + const char *name; + u32 freq; + u32 required; +}; + +struct cnss_clk_info { + struct list_head list; + struct clk *clk; + struct cnss_clk_cfg cfg; + u32 enabled; +}; + +struct cnss_pinctrl_info { + struct pinctrl *pinctrl; + struct pinctrl_state *bootstrap_active; + struct pinctrl_state *wlan_en_active; + struct pinctrl_state *wlan_en_sleep; +}; + +struct cnss_subsys_info { + struct subsys_device *subsys_device; + struct subsys_desc subsys_desc; + void *subsys_handle; +}; + +struct cnss_ramdump_info { + struct ramdump_device *ramdump_dev; + unsigned long ramdump_size; + void *ramdump_va; + phys_addr_t ramdump_pa; + struct msm_dump_data dump_data; +}; + +struct cnss_dump_seg { + unsigned long address; + void *v_address; + unsigned long size; + u32 type; +}; + +struct cnss_dump_data { + u32 version; + u32 magic; + char name[32]; + phys_addr_t paddr; + int nentries; + u32 seg_version; +}; + +struct cnss_ramdump_info_v2 { + struct ramdump_device *ramdump_dev; + unsigned long ramdump_size; + void *dump_data_vaddr; + u8 dump_data_valid; + struct cnss_dump_data dump_data; +}; + +struct cnss_esoc_info { + struct esoc_desc *esoc_desc; + u8 notify_modem_status; + void *modem_notify_handler; + int modem_current_status; +}; + +struct cnss_bus_bw_cfg { + u32 ab; + u32 ib; +}; + +struct cnss_bus_bw_info { + struct icc_path *cnss_path; + int current_bw_vote; +}; + +struct cnss_fw_mem { + size_t size; + void *va; + phys_addr_t pa; + u8 valid; + u32 type; +}; + +struct wlfw_rf_chip_info { + u32 chip_id; + u32 chip_family; +}; + +struct wlfw_rf_board_info { + u32 board_id; +}; + +struct wlfw_soc_info { + u32 soc_id; +}; + +struct wlfw_fw_version_info { + u32 fw_version; + char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN + 1]; +}; + +enum cnss_mem_type { + CNSS_MEM_TYPE_MSA, + CNSS_MEM_TYPE_DDR, + CNSS_MEM_BDF, + CNSS_MEM_M3, + CNSS_MEM_CAL_V01, + CNSS_MEM_DPD_V01, +}; + +enum cnss_fw_dump_type { + CNSS_FW_IMAGE, + CNSS_FW_RDDM, + CNSS_FW_REMOTE_HEAP, +}; + +enum cnss_driver_event_type { + CNSS_DRIVER_EVENT_SERVER_ARRIVE, + CNSS_DRIVER_EVENT_SERVER_EXIT, + CNSS_DRIVER_EVENT_REQUEST_MEM, + CNSS_DRIVER_EVENT_FW_MEM_READY, + CNSS_DRIVER_EVENT_FW_READY, + CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START, + CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE, + CNSS_DRIVER_EVENT_REGISTER_DRIVER, + CNSS_DRIVER_EVENT_UNREGISTER_DRIVER, + CNSS_DRIVER_EVENT_RECOVERY, + CNSS_DRIVER_EVENT_FORCE_FW_ASSERT, + CNSS_DRIVER_EVENT_POWER_UP, + CNSS_DRIVER_EVENT_POWER_DOWN, + CNSS_DRIVER_EVENT_IDLE_RESTART, + CNSS_DRIVER_EVENT_IDLE_SHUTDOWN, + CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM, + CNSS_DRIVER_EVENT_QDSS_TRACE_SAVE, + CNSS_DRIVER_EVENT_QDSS_TRACE_FREE, + CNSS_DRIVER_EVENT_MAX, +}; + +enum cnss_driver_state { + CNSS_QMI_WLFW_CONNECTED, + CNSS_FW_MEM_READY, + CNSS_FW_READY, + CNSS_COLD_BOOT_CAL, + CNSS_DRIVER_LOADING, + CNSS_DRIVER_UNLOADING, + CNSS_DRIVER_IDLE_RESTART, + CNSS_DRIVER_IDLE_SHUTDOWN, + CNSS_DRIVER_PROBED, + CNSS_DRIVER_RECOVERY, + CNSS_FW_BOOT_RECOVERY, + CNSS_DEV_ERR_NOTIFY, + CNSS_DRIVER_DEBUG, + CNSS_COEX_CONNECTED, + CNSS_IMS_CONNECTED, + CNSS_IN_SUSPEND_RESUME, +}; + +struct cnss_recovery_data { + enum cnss_recovery_reason reason; +}; + +enum cnss_pins { + CNSS_WLAN_EN, + CNSS_PCIE_TXP, + CNSS_PCIE_TXN, + CNSS_PCIE_RXP, + CNSS_PCIE_RXN, + CNSS_PCIE_REFCLKP, + CNSS_PCIE_REFCLKN, + CNSS_PCIE_RST, + CNSS_PCIE_WAKE, +}; + +struct cnss_pin_connect_result { + u32 fw_pwr_pin_result; + u32 fw_phy_io_pin_result; + u32 fw_rf_pin_result; + u32 host_pin_result; +}; + +enum cnss_debug_quirks { + LINK_DOWN_SELF_RECOVERY, + SKIP_DEVICE_BOOT, + USE_CORE_ONLY_FW, + SKIP_RECOVERY, + QMI_BYPASS, + ENABLE_WALTEST, + ENABLE_PCI_LINK_DOWN_PANIC, + FBC_BYPASS, + ENABLE_DAEMON_SUPPORT, + DISABLE_DRV, +}; + +enum cnss_bdf_type { + CNSS_BDF_BIN, + CNSS_BDF_ELF, + CNSS_BDF_REGDB = 4, + CNSS_BDF_DUMMY = 255, +}; + +enum cnss_cal_status { + CNSS_CAL_DONE, + CNSS_CAL_TIMEOUT, +}; + +struct cnss_cal_info { + enum cnss_cal_status cal_status; +}; + +struct cnss_control_params { + unsigned long quirks; + unsigned int mhi_timeout; + unsigned int qmi_timeout; + unsigned int bdf_type; + unsigned int time_sync_period; +}; + +struct cnss_cpr_info { + resource_size_t tcs_cmd_base_addr; + resource_size_t tcs_cmd_data_addr; + void __iomem *tcs_cmd_base_addr_io; + void __iomem *tcs_cmd_data_addr_io; + u32 cpr_pmic_addr; + u32 voltage; +}; + +enum cnss_ce_index { + CNSS_CE_00, + CNSS_CE_01, + CNSS_CE_02, + CNSS_CE_03, + CNSS_CE_04, + CNSS_CE_05, + CNSS_CE_06, + CNSS_CE_07, + CNSS_CE_08, + CNSS_CE_09, + CNSS_CE_10, + CNSS_CE_11, + CNSS_CE_COMMON, +}; + +struct cnss_plat_data { + struct platform_device *plat_dev; + void *bus_priv; + enum cnss_dev_bus_type bus_type; + struct list_head vreg_list; + struct list_head clk_list; + struct cnss_pinctrl_info pinctrl_info; + struct cnss_subsys_info subsys_info; + struct cnss_ramdump_info ramdump_info; + struct cnss_ramdump_info_v2 ramdump_info_v2; + struct cnss_esoc_info esoc_info; + struct cnss_bus_bw_info bus_bw_info; + struct notifier_block modem_nb; + struct cnss_platform_cap cap; + struct pm_qos_request qos_request; + struct cnss_device_version device_version; + unsigned long device_id; + enum cnss_driver_status driver_status; + u32 recovery_count; + unsigned long driver_state; + struct list_head event_list; + spinlock_t event_lock; /* spinlock for driver work event handling */ + struct work_struct event_work; + struct workqueue_struct *event_wq; + struct qmi_handle qmi_wlfw; + struct wlfw_rf_chip_info chip_info; + struct wlfw_rf_board_info board_info; + struct wlfw_soc_info soc_info; + struct wlfw_fw_version_info fw_version_info; + u32 otp_version; + u32 fw_mem_seg_len; + struct cnss_fw_mem fw_mem[QMI_WLFW_MAX_NUM_MEM_SEG]; + struct cnss_fw_mem m3_mem; + u32 qdss_mem_seg_len; + struct cnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG]; + u32 *qdss_reg; + struct cnss_pin_connect_result pin_result; + struct dentry *root_dentry; + atomic_t pm_count; + struct timer_list fw_boot_timer; + struct completion power_up_complete; + struct completion cal_complete; + struct mutex dev_lock; /* mutex for register access through debugfs */ + u32 device_freq_hz; + u32 diag_reg_read_addr; + u32 diag_reg_read_mem_type; + u32 diag_reg_read_len; + u8 *diag_reg_read_buf; + u8 cal_done; + u8 powered_on; + char firmware_name[13]; + struct completion rddm_complete; + struct completion recovery_complete; + struct cnss_control_params ctrl_params; + struct cnss_cpr_info cpr_info; + u64 antenna; + u64 grant; + struct qmi_handle coex_qmi; + struct qmi_handle ims_qmi; + struct qmi_txn txn; + u64 dynamic_feature; +}; + +#ifdef CONFIG_ARCH_QCOM +static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv) +{ + u64 ticks = arch_counter_get_cntvct(); + + do_div(ticks, TIME_CLOCK_FREQ_HZ / 100000); + + return ticks * 10; +} +#else +static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv) +{ + struct timespec ts; + + ktime_get_ts(&ts); + + return ((u64)ts.tv_sec * 1000000) + (ts.tv_nsec / 1000); +} +#endif + +struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev); +int cnss_driver_event_post(struct cnss_plat_data *plat_priv, + enum cnss_driver_event_type type, + u32 flags, void *data); +int cnss_get_vreg_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type); +void cnss_put_vreg_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type); +int cnss_vreg_on_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type); +int cnss_vreg_off_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type); +int cnss_get_clk(struct cnss_plat_data *plat_priv); +void cnss_put_clk(struct cnss_plat_data *plat_priv); +int cnss_vreg_unvote_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type); +int cnss_get_pinctrl(struct cnss_plat_data *plat_priv); +int cnss_power_on_device(struct cnss_plat_data *plat_priv); +void cnss_power_off_device(struct cnss_plat_data *plat_priv); +bool cnss_is_device_powered_on(struct cnss_plat_data *plat_priv); +int cnss_register_subsys(struct cnss_plat_data *plat_priv); +void cnss_unregister_subsys(struct cnss_plat_data *plat_priv); +int cnss_register_ramdump(struct cnss_plat_data *plat_priv); +void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv); +void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv); +int cnss_get_cpr_info(struct cnss_plat_data *plat_priv); +int cnss_update_cpr_info(struct cnss_plat_data *plat_priv); + +#endif /* _CNSS_MAIN_H */ diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c new file mode 100644 index 000000000000..0c2a18365631 --- /dev/null +++ b/drivers/net/wireless/cnss2/pci.c @@ -0,0 +1,3526 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "main.h" +#include "bus.h" +#include "debug.h" +#include "pci.h" + +#define PCI_LINK_UP 1 +#define PCI_LINK_DOWN 0 + +#define SAVE_PCI_CONFIG_SPACE 1 +#define RESTORE_PCI_CONFIG_SPACE 0 + +#define PM_OPTIONS_DEFAULT 0 +#define PM_OPTIONS_LINK_DOWN \ + (MSM_PCIE_CONFIG_NO_CFG_RESTORE | MSM_PCIE_CONFIG_LINKDOWN) + +#define PCI_BAR_NUM 0 + +#define PCI_DMA_MASK_32_BIT 32 +#define PCI_DMA_MASK_64_BIT 64 + +#define MHI_NODE_NAME "qcom,mhi" +#define MHI_MSI_NAME "MHI" + +#define MAX_M3_FILE_NAME_LENGTH 13 +#define DEFAULT_M3_FILE_NAME "m3.bin" +#define DEFAULT_FW_FILE_NAME "amss.bin" +#define FW_V2_FILE_NAME "amss20.bin" +#define FW_V2_NUMBER 2 + +#define WAKE_MSI_NAME "WAKE" + +#define FW_ASSERT_TIMEOUT 5000 +#define DEV_RDDM_TIMEOUT 5000 + +#ifdef CONFIG_CNSS_EMULATION +#define EMULATION_HW 1 +#else +#define EMULATION_HW 0 +#endif + +static DEFINE_SPINLOCK(pci_link_down_lock); +static DEFINE_SPINLOCK(pci_reg_window_lock); + +#define MHI_TIMEOUT_OVERWRITE_MS (plat_priv->ctrl_params.mhi_timeout) + +#define QCA6390_PCIE_REMAP_BAR_CTRL_OFFSET 0x310C + +#define QCA6390_CE_SRC_RING_REG_BASE 0xA00000 +#define QCA6390_CE_DST_RING_REG_BASE 0xA01000 +#define QCA6390_CE_COMMON_REG_BASE 0xA18000 + +#define QCA6390_CE_SRC_RING_BASE_LSB_OFFSET 0x0 +#define QCA6390_CE_SRC_RING_BASE_MSB_OFFSET 0x4 +#define QCA6390_CE_SRC_RING_ID_OFFSET 0x8 +#define QCA6390_CE_SRC_RING_MISC_OFFSET 0x10 +#define QCA6390_CE_SRC_CTRL_OFFSET 0x58 +#define QCA6390_CE_SRC_R0_CE_CH_SRC_IS_OFFSET 0x5C +#define QCA6390_CE_SRC_RING_HP_OFFSET 0x400 +#define QCA6390_CE_SRC_RING_TP_OFFSET 0x404 + +#define QCA6390_CE_DEST_RING_BASE_LSB_OFFSET 0x0 +#define QCA6390_CE_DEST_RING_BASE_MSB_OFFSET 0x4 +#define QCA6390_CE_DEST_RING_ID_OFFSET 0x8 +#define QCA6390_CE_DEST_RING_MISC_OFFSET 0x10 +#define QCA6390_CE_DEST_CTRL_OFFSET 0xB0 +#define QCA6390_CE_CH_DST_IS_OFFSET 0xB4 +#define QCA6390_CE_CH_DEST_CTRL2_OFFSET 0xB8 +#define QCA6390_CE_DEST_RING_HP_OFFSET 0x400 +#define QCA6390_CE_DEST_RING_TP_OFFSET 0x404 + +#define QCA6390_CE_STATUS_RING_BASE_LSB_OFFSET 0x58 +#define QCA6390_CE_STATUS_RING_BASE_MSB_OFFSET 0x5C +#define QCA6390_CE_STATUS_RING_ID_OFFSET 0x60 +#define QCA6390_CE_STATUS_RING_MISC_OFFSET 0x68 +#define QCA6390_CE_STATUS_RING_HP_OFFSET 0x408 +#define QCA6390_CE_STATUS_RING_TP_OFFSET 0x40C + +#define QCA6390_CE_COMMON_GXI_ERR_INTS 0x14 +#define QCA6390_CE_COMMON_GXI_ERR_STATS 0x18 +#define QCA6390_CE_COMMON_GXI_WDOG_STATUS 0x2C +#define QCA6390_CE_COMMON_TARGET_IE_0 0x48 +#define QCA6390_CE_COMMON_TARGET_IE_1 0x4C + +#define QCA6390_CE_REG_INTERVAL 0x2000 + +#define SHADOW_REG_COUNT 36 +#define QCA6390_PCIE_SHADOW_REG_VALUE_0 0x8FC +#define QCA6390_PCIE_SHADOW_REG_VALUE_34 0x984 +#define QCA6390_PCIE_SHADOW_REG_VALUE_35 0x988 +#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118 +#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C +#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120 + +#define SHADOW_REG_INTER_COUNT 43 +#define QCA6390_PCIE_SHADOW_REG_INTER_0 0x1E05000 +#define QCA6390_PCIE_SHADOW_REG_HUNG 0x1E050A8 + +#define QDSS_APB_DEC_CSR_BASE 0x1C01000 + +#define QDSS_APB_DEC_CSR_ETRIRQCTRL_OFFSET 0x6C +#define QDSS_APB_DEC_CSR_PRESERVEETF_OFFSET 0x70 +#define QDSS_APB_DEC_CSR_PRESERVEETR0_OFFSET 0x74 +#define QDSS_APB_DEC_CSR_PRESERVEETR1_OFFSET 0x78 + +#define MAX_UNWINDOWED_ADDRESS 0x80000 +#define WINDOW_ENABLE_BIT 0x40000000 +#define WINDOW_SHIFT 19 +#define WINDOW_VALUE_MASK 0x3F +#define WINDOW_START MAX_UNWINDOWED_ADDRESS +#define WINDOW_RANGE_MASK 0x7FFFF + +#define FORCE_WAKE_DELAY_MIN_US 4000 +#define FORCE_WAKE_DELAY_MAX_US 6000 +#define FORCE_WAKE_DELAY_TIMEOUT_US 60000 + +#define QCA6390_TIME_SYNC_ENABLE 0x80000000 +#define QCA6390_TIME_SYNC_CLEAR 0x0 + +static struct cnss_pci_reg ce_src[] = { + { "SRC_RING_BASE_LSB", QCA6390_CE_SRC_RING_BASE_LSB_OFFSET }, + { "SRC_RING_BASE_MSB", QCA6390_CE_SRC_RING_BASE_MSB_OFFSET }, + { "SRC_RING_ID", QCA6390_CE_SRC_RING_ID_OFFSET }, + { "SRC_RING_MISC", QCA6390_CE_SRC_RING_MISC_OFFSET }, + { "SRC_CTRL", QCA6390_CE_SRC_CTRL_OFFSET }, + { "SRC_R0_CE_CH_SRC_IS", QCA6390_CE_SRC_R0_CE_CH_SRC_IS_OFFSET }, + { "SRC_RING_HP", QCA6390_CE_SRC_RING_HP_OFFSET }, + { "SRC_RING_TP", QCA6390_CE_SRC_RING_TP_OFFSET }, + { NULL }, +}; + +static struct cnss_pci_reg ce_dst[] = { + { "DEST_RING_BASE_LSB", QCA6390_CE_DEST_RING_BASE_LSB_OFFSET }, + { "DEST_RING_BASE_MSB", QCA6390_CE_DEST_RING_BASE_MSB_OFFSET }, + { "DEST_RING_ID", QCA6390_CE_DEST_RING_ID_OFFSET }, + { "DEST_RING_MISC", QCA6390_CE_DEST_RING_MISC_OFFSET }, + { "DEST_CTRL", QCA6390_CE_DEST_CTRL_OFFSET }, + { "CE_CH_DST_IS", QCA6390_CE_CH_DST_IS_OFFSET }, + { "CE_CH_DEST_CTRL2", QCA6390_CE_CH_DEST_CTRL2_OFFSET }, + { "DEST_RING_HP", QCA6390_CE_DEST_RING_HP_OFFSET }, + { "DEST_RING_TP", QCA6390_CE_DEST_RING_TP_OFFSET }, + { "STATUS_RING_BASE_LSB", QCA6390_CE_STATUS_RING_BASE_LSB_OFFSET }, + { "STATUS_RING_BASE_MSB", QCA6390_CE_STATUS_RING_BASE_MSB_OFFSET }, + { "STATUS_RING_ID", QCA6390_CE_STATUS_RING_ID_OFFSET }, + { "STATUS_RING_MISC", QCA6390_CE_STATUS_RING_MISC_OFFSET }, + { "STATUS_RING_HP", QCA6390_CE_STATUS_RING_HP_OFFSET }, + { "STATUS_RING_TP", QCA6390_CE_STATUS_RING_TP_OFFSET }, + { NULL }, +}; + +static struct cnss_pci_reg ce_cmn[] = { + { "GXI_ERR_INTS", QCA6390_CE_COMMON_GXI_ERR_INTS }, + { "GXI_ERR_STATS", QCA6390_CE_COMMON_GXI_ERR_STATS }, + { "GXI_WDOG_STATUS", QCA6390_CE_COMMON_GXI_WDOG_STATUS }, + { "TARGET_IE_0", QCA6390_CE_COMMON_TARGET_IE_0 }, + { "TARGET_IE_1", QCA6390_CE_COMMON_TARGET_IE_1 }, + { NULL }, +}; + +static struct cnss_pci_reg qdss_csr[] = { + { "QDSSCSR_ETRIRQCTRL", QDSS_APB_DEC_CSR_ETRIRQCTRL_OFFSET }, + { "QDSSCSR_PRESERVEETF", QDSS_APB_DEC_CSR_PRESERVEETF_OFFSET }, + { "QDSSCSR_PRESERVEETR0", QDSS_APB_DEC_CSR_PRESERVEETR0_OFFSET }, + { "QDSSCSR_PRESERVEETR1", QDSS_APB_DEC_CSR_PRESERVEETR1_OFFSET }, + { NULL }, +}; + +static int cnss_pci_check_link_status(struct cnss_pci_data *pci_priv) +{ + u16 device_id; + + if (pci_priv->pci_link_state == PCI_LINK_DOWN) { + cnss_pr_dbg("PCIe link is suspended\n"); + return -EIO; + } + + if (pci_priv->pci_link_down_ind) { + cnss_pr_err("PCIe link is down\n"); + return -EIO; + } + + pci_read_config_word(pci_priv->pci_dev, PCI_DEVICE_ID, &device_id); + if (device_id != pci_priv->device_id) { + cnss_fatal_err("PCI device ID mismatch, link possibly down, current read ID: 0x%x, record ID: 0x%x\n", + device_id, pci_priv->device_id); + return -EIO; + } + + return 0; +} + +static void cnss_pci_select_window(struct cnss_pci_data *pci_priv, u32 offset) +{ + u32 window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; + + writel_relaxed(WINDOW_ENABLE_BIT | window, + QCA6390_PCIE_REMAP_BAR_CTRL_OFFSET + + pci_priv->bar); + + if (window != pci_priv->remap_window) { + pci_priv->remap_window = window; + cnss_pr_dbg("Config PCIe remap window register to 0x%x\n", + WINDOW_ENABLE_BIT | window); + } +} + +static int cnss_pci_reg_read(struct cnss_pci_data *pci_priv, + u32 offset, u32 *val) +{ + int ret; + unsigned long flags; + + ret = cnss_pci_check_link_status(pci_priv); + if (ret) + return ret; + + if (pci_priv->pci_dev->device == QCA6174_DEVICE_ID || + offset < MAX_UNWINDOWED_ADDRESS) { + *val = readl_relaxed(pci_priv->bar + offset); + return 0; + } + + spin_lock_irqsave(&pci_reg_window_lock, flags); + cnss_pci_select_window(pci_priv, offset); + + *val = readl_relaxed(pci_priv->bar + WINDOW_START + + (offset & WINDOW_RANGE_MASK)); + spin_unlock_irqrestore(&pci_reg_window_lock, flags); + + return 0; +} + +static int cnss_pci_reg_write(struct cnss_pci_data *pci_priv, u32 offset, + u32 val) +{ + int ret; + unsigned long flags; + + ret = cnss_pci_check_link_status(pci_priv); + if (ret) + return ret; + + if (pci_priv->pci_dev->device == QCA6174_DEVICE_ID || + offset < MAX_UNWINDOWED_ADDRESS) { + writel_relaxed(val, pci_priv->bar + offset); + return 0; + } + + spin_lock_irqsave(&pci_reg_window_lock, flags); + cnss_pci_select_window(pci_priv, offset); + + writel_relaxed(val, pci_priv->bar + WINDOW_START + + (offset & WINDOW_RANGE_MASK)); + spin_unlock_irqrestore(&pci_reg_window_lock, flags); + + return 0; +} + +static int cnss_pci_force_wake_get(struct cnss_pci_data *pci_priv) +{ + struct device *dev = &pci_priv->pci_dev->dev; + u32 timeout = 0; + int ret; + + ret = cnss_pci_force_wake_request(dev); + if (ret) { + cnss_pr_err("Failed to request force wake\n"); + return ret; + } + + while (!cnss_pci_is_device_awake(dev) && + timeout <= FORCE_WAKE_DELAY_TIMEOUT_US) { + usleep_range(FORCE_WAKE_DELAY_MIN_US, FORCE_WAKE_DELAY_MAX_US); + timeout += FORCE_WAKE_DELAY_MAX_US; + } + + if (cnss_pci_is_device_awake(dev) != true) { + cnss_pr_err("Timed out to request force wake\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int cnss_pci_force_wake_put(struct cnss_pci_data *pci_priv) +{ + struct device *dev = &pci_priv->pci_dev->dev; + int ret; + + ret = cnss_pci_force_wake_release(dev); + if (ret) + cnss_pr_err("Failed to release force wake\n"); + + return ret; +} + +static int cnss_set_pci_config_space(struct cnss_pci_data *pci_priv, bool save) +{ + struct pci_dev *pci_dev = pci_priv->pci_dev; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + bool link_down_or_recovery; + + if (!plat_priv) + return -ENODEV; + + link_down_or_recovery = pci_priv->pci_link_down_ind || + (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)); + + if (save) { + if (link_down_or_recovery) { + pci_priv->saved_state = NULL; + } else { + pci_save_state(pci_dev); + pci_priv->saved_state = pci_store_saved_state(pci_dev); + } + } else { + if (link_down_or_recovery) { + pci_load_saved_state(pci_dev, pci_priv->default_state); + pci_restore_state(pci_dev); + } else if (pci_priv->saved_state) { + pci_load_and_free_saved_state(pci_dev, + &pci_priv->saved_state); + pci_restore_state(pci_dev); + } + } + + return 0; +} + +static int cnss_pci_get_link_status(struct cnss_pci_data *pci_priv) +{ + u16 link_status; + int ret; + + ret = pcie_capability_read_word(pci_priv->pci_dev, PCI_EXP_LNKSTA, + &link_status); + if (ret) + return ret; + + cnss_pr_dbg("Get PCI link status register: %u\n", link_status); + + pci_priv->def_link_speed = link_status & PCI_EXP_LNKSTA_CLS; + pci_priv->def_link_width = + (link_status & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; + + cnss_pr_dbg("Default PCI link speed is 0x%x, link width is 0x%x\n", + pci_priv->def_link_speed, pci_priv->def_link_width); + + return 0; +} + +static int cnss_set_pci_link_status(struct cnss_pci_data *pci_priv, + enum pci_link_status status) +{ + u16 link_speed, link_width; + + cnss_pr_vdbg("Set PCI link status to: %u\n", status); + + switch (status) { + case PCI_GEN1: + link_speed = PCI_EXP_LNKSTA_CLS_2_5GB; + link_width = PCI_EXP_LNKSTA_NLW_X1 >> PCI_EXP_LNKSTA_NLW_SHIFT; + break; + case PCI_GEN2: + link_speed = PCI_EXP_LNKSTA_CLS_5_0GB; + link_width = PCI_EXP_LNKSTA_NLW_X1 >> PCI_EXP_LNKSTA_NLW_SHIFT; + break; + case PCI_DEF: + link_speed = pci_priv->def_link_speed; + link_width = pci_priv->def_link_width; + if (!link_speed && !link_width) { + cnss_pr_err("PCI link speed or width is not valid\n"); + return -EINVAL; + } + break; + default: + cnss_pr_err("Unknown PCI link status config: %u\n", status); + return -EINVAL; + } + + return msm_pcie_set_link_bandwidth(pci_priv->pci_dev, + link_speed, link_width); +} + +static int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up) +{ + int ret = 0; + struct pci_dev *pci_dev = pci_priv->pci_dev; + enum msm_pcie_pm_opt pm_ops; + + cnss_pr_vdbg("%s PCI link\n", link_up ? "Resuming" : "Suspending"); + + if (link_up) { + pm_ops = MSM_PCIE_RESUME; + } else { + if (pci_priv->drv_connected_last) { + cnss_pr_vdbg("Use PCIe DRV suspend\n"); + pm_ops = MSM_PCIE_DRV_SUSPEND; + cnss_set_pci_link_status(pci_priv, PCI_GEN1); + } else { + pm_ops = MSM_PCIE_SUSPEND; + } + } + + ret = msm_pcie_pm_control(pm_ops, pci_dev->bus->number, pci_dev, + NULL, PM_OPTIONS_DEFAULT); + if (ret) + cnss_pr_err("Failed to %s PCI link with default option, err = %d\n", + link_up ? "resume" : "suspend", ret); + + if (pci_priv->drv_connected_last) { + if ((link_up && !ret) || (!link_up && ret)) + cnss_set_pci_link_status(pci_priv, PCI_DEF); + } + + return ret; +} + +int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + + if (!pci_priv) + return -ENODEV; + + if (pci_priv->pci_link_state == PCI_LINK_DOWN) { + cnss_pr_info("PCI link is already suspended\n"); + goto out; + } + + pci_clear_master(pci_priv->pci_dev); + + ret = cnss_set_pci_config_space(pci_priv, SAVE_PCI_CONFIG_SPACE); + if (ret) + goto out; + + pci_disable_device(pci_priv->pci_dev); + + if (pci_priv->pci_dev->device != QCA6174_DEVICE_ID) { + if (pci_set_power_state(pci_priv->pci_dev, PCI_D3hot)) + cnss_pr_err("Failed to set D3Hot, err = %d\n", ret); + } + + ret = cnss_set_pci_link(pci_priv, PCI_LINK_DOWN); + if (ret) + goto out; + + pci_priv->pci_link_state = PCI_LINK_DOWN; + + return 0; +out: + return ret; +} + +int cnss_resume_pci_link(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + + if (!pci_priv) + return -ENODEV; + + if (pci_priv->pci_link_state == PCI_LINK_UP) { + cnss_pr_info("PCI link is already resumed\n"); + goto out; + } + + ret = cnss_set_pci_link(pci_priv, PCI_LINK_UP); + if (ret) + goto out; + + pci_priv->pci_link_state = PCI_LINK_UP; + + if (pci_priv->pci_dev->device != QCA6174_DEVICE_ID) { + ret = pci_set_power_state(pci_priv->pci_dev, PCI_D0); + if (ret) { + cnss_pr_err("Failed to set D0, err = %d\n", ret); + goto out; + } + } + + ret = pci_enable_device(pci_priv->pci_dev); + if (ret) { + cnss_pr_err("Failed to enable PCI device, err = %d\n", ret); + goto out; + } + + ret = cnss_set_pci_config_space(pci_priv, RESTORE_PCI_CONFIG_SPACE); + if (ret) + goto out; + + pci_set_master(pci_priv->pci_dev); + + if (pci_priv->pci_link_down_ind) + pci_priv->pci_link_down_ind = false; + + return 0; +out: + return ret; +} + +int cnss_pci_link_down(struct device *dev) +{ + unsigned long flags; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -EINVAL; + } + + plat_priv = pci_priv->plat_priv; + if (test_bit(ENABLE_PCI_LINK_DOWN_PANIC, + &plat_priv->ctrl_params.quirks)) + panic("cnss: PCI link is down\n"); + + spin_lock_irqsave(&pci_link_down_lock, flags); + if (pci_priv->pci_link_down_ind) { + cnss_pr_dbg("PCI link down recovery is in progress, ignore\n"); + spin_unlock_irqrestore(&pci_link_down_lock, flags); + return -EINVAL; + } + pci_priv->pci_link_down_ind = true; + spin_unlock_irqrestore(&pci_link_down_lock, flags); + + cnss_pr_err("PCI link down is detected, schedule recovery\n"); + + cnss_schedule_recovery(dev, CNSS_REASON_LINK_DOWN); + + return 0; +} +EXPORT_SYMBOL(cnss_pci_link_down); + +int cnss_pci_is_device_down(struct device *dev) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev); + struct cnss_pci_data *pci_priv; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + pci_priv = plat_priv->bus_priv; + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -ENODEV; + } + + return test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state) | + pci_priv->pci_link_down_ind; +} +EXPORT_SYMBOL(cnss_pci_is_device_down); + +static char *cnss_mhi_state_to_str(enum cnss_mhi_state mhi_state) +{ + switch (mhi_state) { + case CNSS_MHI_INIT: + return "INIT"; + case CNSS_MHI_DEINIT: + return "DEINIT"; + case CNSS_MHI_POWER_ON: + return "POWER_ON"; + case CNSS_MHI_POWER_OFF: + return "POWER_OFF"; + case CNSS_MHI_FORCE_POWER_OFF: + return "FORCE_POWER_OFF"; + case CNSS_MHI_SUSPEND: + return "SUSPEND"; + case CNSS_MHI_RESUME: + return "RESUME"; + case CNSS_MHI_TRIGGER_RDDM: + return "TRIGGER_RDDM"; + case CNSS_MHI_RDDM_DONE: + return "RDDM_DONE"; + default: + return "UNKNOWN"; + } +}; + +static int cnss_pci_check_mhi_state_bit(struct cnss_pci_data *pci_priv, + enum cnss_mhi_state mhi_state) +{ + switch (mhi_state) { + case CNSS_MHI_INIT: + if (!test_bit(CNSS_MHI_INIT, &pci_priv->mhi_state)) + return 0; + break; + case CNSS_MHI_DEINIT: + case CNSS_MHI_POWER_ON: + if (test_bit(CNSS_MHI_INIT, &pci_priv->mhi_state) && + !test_bit(CNSS_MHI_POWER_ON, &pci_priv->mhi_state)) + return 0; + break; + case CNSS_MHI_FORCE_POWER_OFF: + if (test_bit(CNSS_MHI_POWER_ON, &pci_priv->mhi_state)) + return 0; + break; + case CNSS_MHI_POWER_OFF: + case CNSS_MHI_SUSPEND: + if (test_bit(CNSS_MHI_POWER_ON, &pci_priv->mhi_state) && + !test_bit(CNSS_MHI_SUSPEND, &pci_priv->mhi_state)) + return 0; + break; + case CNSS_MHI_RESUME: + if (test_bit(CNSS_MHI_SUSPEND, &pci_priv->mhi_state)) + return 0; + break; + case CNSS_MHI_TRIGGER_RDDM: + if (test_bit(CNSS_MHI_POWER_ON, &pci_priv->mhi_state) && + !test_bit(CNSS_MHI_TRIGGER_RDDM, &pci_priv->mhi_state)) + return 0; + break; + case CNSS_MHI_RDDM_DONE: + return 0; + default: + cnss_pr_err("Unhandled MHI state: %s(%d)\n", + cnss_mhi_state_to_str(mhi_state), mhi_state); + } + + cnss_pr_err("Cannot set MHI state %s(%d) in current MHI state (0x%lx)\n", + cnss_mhi_state_to_str(mhi_state), mhi_state, + pci_priv->mhi_state); + + return -EINVAL; +} + +static void cnss_pci_set_mhi_state_bit(struct cnss_pci_data *pci_priv, + enum cnss_mhi_state mhi_state) +{ + switch (mhi_state) { + case CNSS_MHI_INIT: + set_bit(CNSS_MHI_INIT, &pci_priv->mhi_state); + break; + case CNSS_MHI_DEINIT: + clear_bit(CNSS_MHI_INIT, &pci_priv->mhi_state); + break; + case CNSS_MHI_POWER_ON: + set_bit(CNSS_MHI_POWER_ON, &pci_priv->mhi_state); + break; + case CNSS_MHI_POWER_OFF: + case CNSS_MHI_FORCE_POWER_OFF: + clear_bit(CNSS_MHI_POWER_ON, &pci_priv->mhi_state); + clear_bit(CNSS_MHI_TRIGGER_RDDM, &pci_priv->mhi_state); + clear_bit(CNSS_MHI_RDDM_DONE, &pci_priv->mhi_state); + break; + case CNSS_MHI_SUSPEND: + set_bit(CNSS_MHI_SUSPEND, &pci_priv->mhi_state); + break; + case CNSS_MHI_RESUME: + clear_bit(CNSS_MHI_SUSPEND, &pci_priv->mhi_state); + break; + case CNSS_MHI_TRIGGER_RDDM: + set_bit(CNSS_MHI_TRIGGER_RDDM, &pci_priv->mhi_state); + break; + case CNSS_MHI_RDDM_DONE: + set_bit(CNSS_MHI_RDDM_DONE, &pci_priv->mhi_state); + break; + default: + cnss_pr_err("Unhandled MHI state (%d)\n", mhi_state); + } +} + +static int cnss_pci_set_mhi_state(struct cnss_pci_data *pci_priv, + enum cnss_mhi_state mhi_state) +{ + int ret = 0; + + if (pci_priv->device_id == QCA6174_DEVICE_ID) + return 0; + + if (mhi_state < 0) { + cnss_pr_err("Invalid MHI state (%d)\n", mhi_state); + return -EINVAL; + } + + ret = cnss_pci_check_mhi_state_bit(pci_priv, mhi_state); + if (ret) + goto out; + + cnss_pr_vdbg("Setting MHI state: %s(%d)\n", + cnss_mhi_state_to_str(mhi_state), mhi_state); + + switch (mhi_state) { + case CNSS_MHI_INIT: + ret = mhi_prepare_for_power_up(pci_priv->mhi_ctrl); + break; + case CNSS_MHI_DEINIT: + mhi_unprepare_after_power_down(pci_priv->mhi_ctrl); + ret = 0; + break; + case CNSS_MHI_POWER_ON: + ret = mhi_sync_power_up(pci_priv->mhi_ctrl); + break; + case CNSS_MHI_POWER_OFF: + mhi_power_down(pci_priv->mhi_ctrl, true); + ret = 0; + break; + case CNSS_MHI_FORCE_POWER_OFF: + mhi_power_down(pci_priv->mhi_ctrl, false); + ret = 0; + break; + case CNSS_MHI_SUSPEND: + if (pci_priv->drv_connected_last) + ret = mhi_pm_fast_suspend(pci_priv->mhi_ctrl, true); + else + ret = mhi_pm_suspend(pci_priv->mhi_ctrl); + break; + case CNSS_MHI_RESUME: + if (pci_priv->drv_connected_last) + ret = mhi_pm_fast_resume(pci_priv->mhi_ctrl, true); + else + ret = mhi_pm_resume(pci_priv->mhi_ctrl); + break; + case CNSS_MHI_TRIGGER_RDDM: + ret = mhi_force_rddm_mode(pci_priv->mhi_ctrl); + break; + case CNSS_MHI_RDDM_DONE: + break; + default: + cnss_pr_err("Unhandled MHI state (%d)\n", mhi_state); + ret = -EINVAL; + } + + if (ret) + goto out; + + cnss_pci_set_mhi_state_bit(pci_priv, mhi_state); + + return 0; + +out: + cnss_pr_err("Failed to set MHI state: %s(%d)\n", + cnss_mhi_state_to_str(mhi_state), mhi_state); + return ret; +} + +int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct cnss_plat_data *plat_priv; + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -ENODEV; + } + + plat_priv = pci_priv->plat_priv; + if (test_bit(FBC_BYPASS, &plat_priv->ctrl_params.quirks)) + return 0; + + if (MHI_TIMEOUT_OVERWRITE_MS) + pci_priv->mhi_ctrl->timeout_ms = MHI_TIMEOUT_OVERWRITE_MS; + + ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_INIT); + if (ret) + goto out; + + ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_POWER_ON); + if (ret) + goto out; + + return 0; + +out: + return ret; +} + +static void cnss_pci_power_off_mhi(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + if (test_bit(FBC_BYPASS, &plat_priv->ctrl_params.quirks)) + return; + + cnss_pci_set_mhi_state_bit(pci_priv, CNSS_MHI_RESUME); + + if (!pci_priv->pci_link_down_ind) + cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_POWER_OFF); + else + cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_FORCE_POWER_OFF); +} + +static void cnss_pci_deinit_mhi(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + if (test_bit(FBC_BYPASS, &plat_priv->ctrl_params.quirks)) + return; + + cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_DEINIT); +} + +static int cnss_pci_get_device_timestamp(struct cnss_pci_data *pci_priv, + u64 *time_us) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + u32 low, high; + u64 device_ticks; + + if (!plat_priv->device_freq_hz) { + cnss_pr_err("Device time clock frequency is not valid\n"); + return -EINVAL; + } + + cnss_pci_reg_write(pci_priv, QCA6390_WLAON_GLOBAL_COUNTER_CTRL5, + QCA6390_TIME_SYNC_CLEAR); + cnss_pci_reg_write(pci_priv, QCA6390_WLAON_GLOBAL_COUNTER_CTRL5, + QCA6390_TIME_SYNC_ENABLE); + + cnss_pci_reg_read(pci_priv, QCA6390_WLAON_GLOBAL_COUNTER_CTRL3, &low); + cnss_pci_reg_read(pci_priv, QCA6390_WLAON_GLOBAL_COUNTER_CTRL4, &high); + + device_ticks = (u64)high << 32 | low; + do_div(device_ticks, plat_priv->device_freq_hz / 100000); + *time_us = device_ticks * 10; + + return 0; +} + +static int cnss_pci_update_timestamp(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + u64 host_time_us, device_time_us, offset; + u32 low, high; + int ret; + + ret = cnss_pci_check_link_status(pci_priv); + if (ret) + return ret; + + ret = cnss_pci_force_wake_get(pci_priv); + if (ret) + return ret; + + host_time_us = cnss_get_host_timestamp(plat_priv); + ret = cnss_pci_get_device_timestamp(pci_priv, &device_time_us); + if (ret) + goto force_wake_put; + + if (host_time_us < device_time_us) { + cnss_pr_err("Host time (%llu us) is smaller than device time (%llu us), stop\n"); + ret = -EINVAL; + goto force_wake_put; + } + + offset = host_time_us - device_time_us; + cnss_pr_dbg("Host time = %llu us, device time = %llu us, offset = %llu us\n", + host_time_us, device_time_us, offset); + + low = offset & 0xFFFFFFFF; + high = offset >> 32; + + cnss_pci_reg_write(pci_priv, QCA6390_PCIE_SHADOW_REG_VALUE_34, low); + cnss_pci_reg_write(pci_priv, QCA6390_PCIE_SHADOW_REG_VALUE_35, high); + + cnss_pci_reg_read(pci_priv, QCA6390_PCIE_SHADOW_REG_VALUE_34, &low); + cnss_pci_reg_read(pci_priv, QCA6390_PCIE_SHADOW_REG_VALUE_35, &high); + + cnss_pr_dbg("Updated time sync regs [0x%x] = 0x%x, [0x%x] = 0x%x\n", + QCA6390_PCIE_SHADOW_REG_VALUE_34, low, + QCA6390_PCIE_SHADOW_REG_VALUE_35, high); + +force_wake_put: + cnss_pci_force_wake_put(pci_priv); + + return ret; +} + +static void cnss_pci_time_sync_work_hdlr(struct work_struct *work) +{ + struct cnss_pci_data *pci_priv = + container_of(work, struct cnss_pci_data, time_sync_work.work); + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + unsigned int time_sync_period_ms = + plat_priv->ctrl_params.time_sync_period; + + if (cnss_pci_is_device_down(&pci_priv->pci_dev->dev)) + return; + + if (cnss_pci_pm_runtime_get_sync(pci_priv) < 0) + goto runtime_pm_put; + + cnss_pci_update_timestamp(pci_priv); + schedule_delayed_work(&pci_priv->time_sync_work, + msecs_to_jiffies(time_sync_period_ms)); + +runtime_pm_put: + cnss_pci_pm_runtime_mark_last_busy(pci_priv); + cnss_pci_pm_runtime_put_autosuspend(pci_priv); +} + +static int cnss_pci_start_time_sync_update(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + switch (pci_priv->device_id) { + case QCA6390_DEVICE_ID: + break; + default: + return -EOPNOTSUPP; + } + + if (!plat_priv->device_freq_hz) { + cnss_pr_dbg("Device time clock frequency is not valid, skip time sync\n"); + return -EINVAL; + } + + cnss_pci_time_sync_work_hdlr(&pci_priv->time_sync_work.work); + + return 0; +} + +static void cnss_pci_stop_time_sync_update(struct cnss_pci_data *pci_priv) +{ + switch (pci_priv->device_id) { + case QCA6390_DEVICE_ID: + break; + default: + return; + } + + cancel_delayed_work_sync(&pci_priv->time_sync_work); +} + +int cnss_pci_call_driver_probe(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct cnss_plat_data *plat_priv; + + if (!pci_priv) + return -ENODEV; + + plat_priv = pci_priv->plat_priv; + + if (test_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state)) { + clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); + cnss_pr_dbg("Skip driver probe\n"); + goto out; + } + + if (!pci_priv->driver_ops) { + cnss_pr_err("driver_ops is NULL\n"); + ret = -EINVAL; + goto out; + } + + if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) && + test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state)) { + ret = pci_priv->driver_ops->reinit(pci_priv->pci_dev, + pci_priv->pci_device_id); + if (ret) { + cnss_pr_err("Failed to reinit host driver, err = %d\n", + ret); + goto out; + } + clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); + complete(&plat_priv->recovery_complete); + } else if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state)) { + ret = pci_priv->driver_ops->probe(pci_priv->pci_dev, + pci_priv->pci_device_id); + if (ret) { + cnss_pr_err("Failed to probe host driver, err = %d\n", + ret); + goto out; + } + clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); + clear_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state); + set_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state); + } else if (test_bit(CNSS_DRIVER_IDLE_RESTART, + &plat_priv->driver_state)) { + ret = pci_priv->driver_ops->idle_restart(pci_priv->pci_dev, + pci_priv->pci_device_id); + if (ret) { + cnss_pr_err("Failed to idle restart host driver, err = %d\n", + ret); + goto out; + } + clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); + clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state); + complete(&plat_priv->power_up_complete); + } else { + complete(&plat_priv->power_up_complete); + } + + cnss_pci_start_time_sync_update(pci_priv); + + return 0; + +out: + return ret; +} + +int cnss_pci_call_driver_remove(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv; + int ret; + + if (!pci_priv) + return -ENODEV; + + plat_priv = pci_priv->plat_priv; + + cnss_pci_stop_time_sync_update(pci_priv); + + if (test_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state) || + test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state)) { + cnss_pr_dbg("Skip driver remove\n"); + return 0; + } + + if (!pci_priv->driver_ops) { + cnss_pr_err("driver_ops is NULL\n"); + return -EINVAL; + } + + if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) && + test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state)) { + pci_priv->driver_ops->shutdown(pci_priv->pci_dev); + } else if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state)) { + pci_priv->driver_ops->remove(pci_priv->pci_dev); + clear_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state); + clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); + } else if (test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, + &plat_priv->driver_state)) { + ret = pci_priv->driver_ops->idle_shutdown(pci_priv->pci_dev); + if (ret == -EAGAIN) { + clear_bit(CNSS_DRIVER_IDLE_SHUTDOWN, + &plat_priv->driver_state); + return ret; + } + clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); + } + + return 0; +} + +int cnss_pci_call_driver_modem_status(struct cnss_pci_data *pci_priv, + int modem_current_status) +{ + struct cnss_wlan_driver *driver_ops; + + if (!pci_priv) + return -ENODEV; + + driver_ops = pci_priv->driver_ops; + if (!driver_ops || !driver_ops->modem_status) + return -EINVAL; + + driver_ops->modem_status(pci_priv->pci_dev, modem_current_status); + + return 0; +} + +int cnss_pci_update_status(struct cnss_pci_data *pci_priv, + enum cnss_driver_status status) +{ + struct cnss_wlan_driver *driver_ops; + + if (!pci_priv) + return -ENODEV; + + driver_ops = pci_priv->driver_ops; + if (!driver_ops || !driver_ops->update_status) + return -EINVAL; + + cnss_pr_dbg("Update driver status: %d\n", status); + + driver_ops->update_status(pci_priv->pci_dev, status); + + return 0; +} + +static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv) +{ + int i, j = 0, array_size = SHADOW_REG_COUNT + SHADOW_REG_INTER_COUNT; + u32 reg_offset; + + if (in_interrupt() || irqs_disabled()) + return; + + if (cnss_pci_check_link_status(pci_priv)) + return; + + if (!pci_priv->debug_reg) { + pci_priv->debug_reg = devm_kzalloc(&pci_priv->pci_dev->dev, + sizeof(*pci_priv->debug_reg) + * array_size, GFP_KERNEL); + if (!pci_priv->debug_reg) + return; + } + + if (cnss_pci_force_wake_get(pci_priv)) + return; + + cnss_pr_dbg("Start to dump shadow registers\n"); + + for (i = 0; i < SHADOW_REG_COUNT; i++, j++) { + reg_offset = QCA6390_PCIE_SHADOW_REG_VALUE_0 + i * 4; + pci_priv->debug_reg[j].offset = reg_offset; + if (cnss_pci_reg_read(pci_priv, reg_offset, + &pci_priv->debug_reg[j].val)) + goto force_wake_put; + } + + for (i = 0; i < SHADOW_REG_INTER_COUNT; i++, j++) { + reg_offset = QCA6390_PCIE_SHADOW_REG_INTER_0 + i * 4; + pci_priv->debug_reg[j].offset = reg_offset; + if (cnss_pci_reg_read(pci_priv, reg_offset, + &pci_priv->debug_reg[j].val)) + goto force_wake_put; + } + +force_wake_put: + cnss_pci_force_wake_put(pci_priv); +} + +#ifdef CONFIG_CNSS2_DEBUG +static void cnss_pci_collect_dump(struct cnss_pci_data *pci_priv) +{ + cnss_pci_collect_dump_info(pci_priv, false); + CNSS_ASSERT(0); +} +#else +static void cnss_pci_collect_dump(struct cnss_pci_data *pci_priv) +{ +} +#endif + +static int cnss_qca6174_powerup(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + ret = cnss_power_on_device(plat_priv); + if (ret) { + cnss_pr_err("Failed to power on device, err = %d\n", ret); + goto out; + } + + ret = cnss_resume_pci_link(pci_priv); + if (ret) { + cnss_pr_err("Failed to resume PCI link, err = %d\n", ret); + goto power_off; + } + + ret = cnss_pci_call_driver_probe(pci_priv); + if (ret) + goto suspend_link; + + return 0; +suspend_link: + cnss_suspend_pci_link(pci_priv); +power_off: + cnss_power_off_device(plat_priv); +out: + return ret; +} + +static int cnss_qca6174_shutdown(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + cnss_pci_pm_runtime_resume(pci_priv); + + ret = cnss_pci_call_driver_remove(pci_priv); + if (ret == -EAGAIN) + goto out; + + cnss_request_bus_bandwidth(&plat_priv->plat_dev->dev, + CNSS_BUS_WIDTH_NONE); + cnss_pci_set_monitor_wake_intr(pci_priv, false); + cnss_pci_set_auto_suspended(pci_priv, 0); + + ret = cnss_suspend_pci_link(pci_priv); + if (ret) + cnss_pr_err("Failed to suspend PCI link, err = %d\n", ret); + + cnss_power_off_device(plat_priv); + + clear_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state); + clear_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state); + +out: + return ret; +} + +static void cnss_qca6174_crash_shutdown(struct cnss_pci_data *pci_priv) +{ + if (pci_priv->driver_ops && pci_priv->driver_ops->crash_shutdown) + pci_priv->driver_ops->crash_shutdown(pci_priv->pci_dev); +} + +static int cnss_qca6174_ramdump(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_ramdump_info *ramdump_info; + struct ramdump_segment segment; + + ramdump_info = &plat_priv->ramdump_info; + if (!ramdump_info->ramdump_size) + return -EINVAL; + + memset(&segment, 0, sizeof(segment)); + segment.v_address = ramdump_info->ramdump_va; + segment.size = ramdump_info->ramdump_size; + ret = do_ramdump(ramdump_info->ramdump_dev, &segment, 1); + + return ret; +} + +static int cnss_qca6290_powerup(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + unsigned int timeout; + + if (plat_priv->ramdump_info_v2.dump_data_valid || + test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) { + cnss_pci_clear_dump_info(pci_priv); + cnss_pci_deinit_mhi(pci_priv); + } + + ret = cnss_power_on_device(plat_priv); + if (ret) { + cnss_pr_err("Failed to power on device, err = %d\n", ret); + goto out; + } + + ret = cnss_resume_pci_link(pci_priv); + if (ret) { + cnss_pr_err("Failed to resume PCI link, err = %d\n", ret); + goto power_off; + } + + timeout = cnss_get_boot_timeout(&pci_priv->pci_dev->dev); + + ret = cnss_pci_start_mhi(pci_priv); + if (ret) { + cnss_fatal_err("Failed to start MHI, err = %d\n", ret); + if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state) && + !pci_priv->pci_link_down_ind && timeout) + mod_timer(&plat_priv->fw_boot_timer, + jiffies + msecs_to_jiffies(timeout >> 1)); + return 0; + } + + if (test_bit(USE_CORE_ONLY_FW, &plat_priv->ctrl_params.quirks)) { + clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state); + clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state); + return 0; + } + + cnss_set_pin_connect_status(plat_priv); + + if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) { + ret = cnss_pci_call_driver_probe(pci_priv); + if (ret) + goto stop_mhi; + } else if (timeout) { + mod_timer(&plat_priv->fw_boot_timer, + jiffies + msecs_to_jiffies(timeout << 1)); + } + + return 0; + +stop_mhi: + cnss_pci_power_off_mhi(pci_priv); + cnss_suspend_pci_link(pci_priv); + cnss_pci_deinit_mhi(pci_priv); +power_off: + cnss_power_off_device(plat_priv); +out: + return ret; +} + +static int cnss_qca6290_shutdown(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + cnss_pci_pm_runtime_resume(pci_priv); + + ret = cnss_pci_call_driver_remove(pci_priv); + if (ret == -EAGAIN) + goto out; + + cnss_request_bus_bandwidth(&plat_priv->plat_dev->dev, + CNSS_BUS_WIDTH_NONE); + cnss_pci_set_monitor_wake_intr(pci_priv, false); + cnss_pci_set_auto_suspended(pci_priv, 0); + + if ((test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) || + test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) && + test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) { + del_timer(&pci_priv->dev_rddm_timer); + cnss_pci_collect_dump(pci_priv); + } + + cnss_pci_power_off_mhi(pci_priv); + ret = cnss_suspend_pci_link(pci_priv); + if (ret) + cnss_pr_err("Failed to suspend PCI link, err = %d\n", ret); + if (!plat_priv->ramdump_info_v2.dump_data_valid && + !test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) + cnss_pci_deinit_mhi(pci_priv); + + cnss_power_off_device(plat_priv); + + pci_priv->remap_window = 0; + + clear_bit(CNSS_FW_READY, &plat_priv->driver_state); + clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state); + clear_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state); + clear_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state); + +out: + return ret; +} + +static void cnss_qca6290_crash_shutdown(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + cnss_pr_dbg("Crash shutdown with driver_state 0x%lx\n", + plat_priv->driver_state); + + cnss_pci_collect_dump_info(pci_priv, true); +} + +static int cnss_qca6290_ramdump(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2; + struct cnss_dump_data *dump_data = &info_v2->dump_data; + struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr; + struct ramdump_segment *ramdump_segs, *s; + int i, ret = 0; + + if (!info_v2->dump_data_valid || + dump_data->nentries == 0) + return 0; + + ramdump_segs = kcalloc(dump_data->nentries, + sizeof(*ramdump_segs), + GFP_KERNEL); + if (!ramdump_segs) + return -ENOMEM; + + s = ramdump_segs; + for (i = 0; i < dump_data->nentries; i++) { + s->address = dump_seg->address; + s->v_address = dump_seg->v_address; + s->size = dump_seg->size; + s++; + dump_seg++; + } + + ret = do_elf_ramdump(info_v2->ramdump_dev, ramdump_segs, + dump_data->nentries); + kfree(ramdump_segs); + + cnss_pci_clear_dump_info(pci_priv); + cnss_pci_deinit_mhi(pci_priv); + + return ret; +} + +int cnss_pci_dev_powerup(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -ENODEV; + } + + switch (pci_priv->device_id) { + case QCA6174_DEVICE_ID: + ret = cnss_qca6174_powerup(pci_priv); + break; + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + ret = cnss_qca6290_powerup(pci_priv); + break; + default: + cnss_pr_err("Unknown device_id found: 0x%x\n", + pci_priv->device_id); + ret = -ENODEV; + } + + return ret; +} + +int cnss_pci_dev_shutdown(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -ENODEV; + } + + switch (pci_priv->device_id) { + case QCA6174_DEVICE_ID: + ret = cnss_qca6174_shutdown(pci_priv); + break; + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + ret = cnss_qca6290_shutdown(pci_priv); + break; + default: + cnss_pr_err("Unknown device_id found: 0x%x\n", + pci_priv->device_id); + ret = -ENODEV; + } + + return ret; +} + +int cnss_pci_dev_crash_shutdown(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -ENODEV; + } + + switch (pci_priv->device_id) { + case QCA6174_DEVICE_ID: + cnss_qca6174_crash_shutdown(pci_priv); + break; + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + cnss_qca6290_crash_shutdown(pci_priv); + break; + default: + cnss_pr_err("Unknown device_id found: 0x%x\n", + pci_priv->device_id); + ret = -ENODEV; + } + + return ret; +} + +int cnss_pci_dev_ramdump(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -ENODEV; + } + + switch (pci_priv->device_id) { + case QCA6174_DEVICE_ID: + ret = cnss_qca6174_ramdump(pci_priv); + break; + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + ret = cnss_qca6290_ramdump(pci_priv); + break; + default: + cnss_pr_err("Unknown device_id found: 0x%x\n", + pci_priv->device_id); + ret = -ENODEV; + } + + return ret; +} + +int cnss_pci_is_drv_connected(struct device *dev) +{ + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(to_pci_dev(dev)); + + if (!pci_priv) + return -ENODEV; + + return pci_priv->drv_connected_last; +} +EXPORT_SYMBOL(cnss_pci_is_drv_connected); + +int cnss_wlan_register_driver(struct cnss_wlan_driver *driver_ops) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(NULL); + struct cnss_pci_data *pci_priv; + unsigned int timeout; + struct cnss_cal_info *cal_info; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return -ENODEV; + } + + pci_priv = plat_priv->bus_priv; + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -ENODEV; + } + + if (pci_priv->driver_ops) { + cnss_pr_err("Driver has already registered\n"); + return -EEXIST; + } + + if (!test_bit(CNSS_COLD_BOOT_CAL, &plat_priv->driver_state)) + goto register_driver; + + cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL); + if (!cal_info) + return -ENOMEM; + + cnss_pr_dbg("Start to wait for calibration to complete\n"); + + timeout = cnss_get_boot_timeout(&pci_priv->pci_dev->dev); + ret = wait_for_completion_timeout(&plat_priv->cal_complete, + msecs_to_jiffies(timeout)); + if (!ret) { + cnss_pr_err("Timeout waiting for calibration to complete\n"); + cal_info->cal_status = CNSS_CAL_TIMEOUT; + cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE, + 0, cal_info); + } + +register_driver: + ret = cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_REGISTER_DRIVER, + CNSS_EVENT_SYNC_UNINTERRUPTIBLE, + driver_ops); + + return ret; +} +EXPORT_SYMBOL(cnss_wlan_register_driver); + +void cnss_wlan_unregister_driver(struct cnss_wlan_driver *driver_ops) +{ + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(NULL); + int ret = 0; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL\n"); + return; + } + + if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) && + !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) + goto skip_wait; + + reinit_completion(&plat_priv->recovery_complete); + ret = wait_for_completion_timeout(&plat_priv->recovery_complete, + RECOVERY_TIMEOUT); + if (!ret) { + cnss_pr_err("Timeout waiting for recovery to complete\n"); + CNSS_ASSERT(0); + } + +skip_wait: + cnss_driver_event_post(plat_priv, + CNSS_DRIVER_EVENT_UNREGISTER_DRIVER, + CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL); +} +EXPORT_SYMBOL(cnss_wlan_unregister_driver); + +int cnss_pci_register_driver_hdlr(struct cnss_pci_data *pci_priv, + void *data) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + set_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state); + pci_priv->driver_ops = data; + + ret = cnss_pci_dev_powerup(pci_priv); + if (ret) { + clear_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state); + pci_priv->driver_ops = NULL; + } + + return ret; +} + +int cnss_pci_unregister_driver_hdlr(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + set_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state); + cnss_pci_dev_shutdown(pci_priv); + pci_priv->driver_ops = NULL; + + return 0; +} + +static bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv) +{ + struct pci_dev *root_port = pci_find_pcie_root_port(pci_priv->pci_dev); + struct device_node *root_of_node = root_port->dev.of_node; + bool drv_supported = false; + + if (root_of_node->parent) + drv_supported = of_property_read_bool(root_of_node->parent, + "qcom,drv-supported"); + + cnss_pr_dbg("PCIe DRV is %s\n", + drv_supported ? "supported" : "not supported"); + + return drv_supported; +} + +static void cnss_pci_event_cb(struct msm_pcie_notify *notify) +{ + unsigned long flags; + struct pci_dev *pci_dev; + struct cnss_pci_data *pci_priv; + struct cnss_plat_data *plat_priv; + + if (!notify) + return; + + pci_dev = notify->user; + if (!pci_dev) + return; + + pci_priv = cnss_get_pci_priv(pci_dev); + if (!pci_priv) + return; + + plat_priv = pci_priv->plat_priv; + switch (notify->event) { + case MSM_PCIE_EVENT_LINKDOWN: + if (test_bit(ENABLE_PCI_LINK_DOWN_PANIC, + &plat_priv->ctrl_params.quirks)) + panic("cnss: PCI link is down!\n"); + + spin_lock_irqsave(&pci_link_down_lock, flags); + if (pci_priv->pci_link_down_ind) { + cnss_pr_dbg("PCI link down recovery is in progress, ignore!\n"); + spin_unlock_irqrestore(&pci_link_down_lock, flags); + return; + } + pci_priv->pci_link_down_ind = true; + spin_unlock_irqrestore(&pci_link_down_lock, flags); + + cnss_fatal_err("PCI link down, schedule recovery!\n"); + if (pci_dev->device == QCA6174_DEVICE_ID) + disable_irq(pci_dev->irq); + cnss_schedule_recovery(&pci_dev->dev, CNSS_REASON_LINK_DOWN); + break; + case MSM_PCIE_EVENT_WAKEUP: + if (cnss_pci_get_monitor_wake_intr(pci_priv) && + cnss_pci_get_auto_suspended(pci_priv)) { + cnss_pci_set_monitor_wake_intr(pci_priv, false); + cnss_pci_pm_request_resume(pci_priv); + } + break; + case MSM_PCIE_EVENT_DRV_CONNECT: + cnss_pr_dbg("DRV subsystem is connected\n"); + cnss_pci_set_drv_connected(pci_priv, 1); + break; + case MSM_PCIE_EVENT_DRV_DISCONNECT: + cnss_pr_dbg("DRV subsystem is disconnected\n"); + cnss_pci_set_drv_connected(pci_priv, 0); + break; + default: + cnss_pr_err("Received invalid PCI event: %d\n", notify->event); + } +} + +static int cnss_reg_pci_event(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct msm_pcie_register_event *pci_event; + + pci_event = &pci_priv->msm_pci_event; + pci_event->events = MSM_PCIE_EVENT_LINKDOWN | + MSM_PCIE_EVENT_WAKEUP; + + if (cnss_pci_is_drv_supported(pci_priv)) + pci_event->events = pci_event->events | + MSM_PCIE_EVENT_DRV_CONNECT | + MSM_PCIE_EVENT_DRV_DISCONNECT; + + pci_event->user = pci_priv->pci_dev; + pci_event->mode = MSM_PCIE_TRIGGER_CALLBACK; + pci_event->callback = cnss_pci_event_cb; + pci_event->options = MSM_PCIE_CONFIG_NO_RECOVERY; + + ret = msm_pcie_register_event(pci_event); + if (ret) + cnss_pr_err("Failed to register MSM PCI event, err = %d\n", + ret); + + return ret; +} + +static void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv) +{ + msm_pcie_deregister_event(&pci_priv->msm_pci_event); +} + +static int cnss_pci_suspend(struct device *dev) +{ + int ret = 0; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; + struct cnss_wlan_driver *driver_ops; + + pm_message_t state = { .event = PM_EVENT_SUSPEND }; + + if (!pci_priv) + goto out; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + goto out; + + if (!cnss_is_device_powered_on(plat_priv)) + goto out; + + set_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state); + + if (!test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) + pci_priv->drv_connected_last = + cnss_pci_get_drv_connected(pci_priv); + + driver_ops = pci_priv->driver_ops; + if (driver_ops && driver_ops->suspend) { + ret = driver_ops->suspend(pci_dev, state); + if (ret) { + cnss_pr_err("Failed to suspend host driver, err = %d\n", + ret); + ret = -EAGAIN; + goto clear_flag; + } + } + + if (pci_priv->pci_link_state == PCI_LINK_UP && !pci_priv->disable_pc) { + if (cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_SUSPEND)) { + ret = -EAGAIN; + goto resume_driver; + } + + if (pci_priv->drv_connected_last) + goto skip_disable_pci; + + pci_clear_master(pci_dev); + cnss_set_pci_config_space(pci_priv, SAVE_PCI_CONFIG_SPACE); + pci_disable_device(pci_dev); + + ret = pci_set_power_state(pci_dev, PCI_D3hot); + if (ret) + cnss_pr_err("Failed to set D3Hot, err = %d\n", ret); + +skip_disable_pci: + if (cnss_set_pci_link(pci_priv, PCI_LINK_DOWN)) { + ret = -EAGAIN; + goto resume_mhi; + } + pci_priv->pci_link_state = PCI_LINK_DOWN; + } + + cnss_pci_set_monitor_wake_intr(pci_priv, false); + + return 0; + +resume_mhi: + if (pci_enable_device(pci_dev)) + cnss_pr_err("Failed to enable PCI device\n"); + if (pci_priv->saved_state) + cnss_set_pci_config_space(pci_priv, RESTORE_PCI_CONFIG_SPACE); + pci_set_master(pci_dev); + cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_RESUME); +resume_driver: + if (driver_ops && driver_ops->resume) + driver_ops->resume(pci_dev); +clear_flag: + pci_priv->drv_connected_last = 0; + clear_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state); +out: + return ret; +} + +static int cnss_pci_resume(struct device *dev) +{ + int ret = 0; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; + struct cnss_wlan_driver *driver_ops; + + if (!pci_priv) + goto out; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + goto out; + + if (pci_priv->pci_link_down_ind) + goto out; + + if (!cnss_is_device_powered_on(pci_priv->plat_priv)) + goto out; + + if (pci_priv->pci_link_state == PCI_LINK_DOWN && + !pci_priv->disable_pc) { + if (cnss_set_pci_link(pci_priv, PCI_LINK_UP)) { + cnss_fatal_err("Failed to resume PCI link from suspend\n"); + cnss_pci_link_down(dev); + ret = -EAGAIN; + goto out; + } + pci_priv->pci_link_state = PCI_LINK_UP; + + if (pci_priv->drv_connected_last) + goto skip_enable_pci; + + ret = pci_enable_device(pci_dev); + if (ret) + cnss_pr_err("Failed to enable PCI device, err = %d\n", + ret); + + if (pci_priv->saved_state) + cnss_set_pci_config_space(pci_priv, + RESTORE_PCI_CONFIG_SPACE); + pci_set_master(pci_dev); + +skip_enable_pci: + cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_RESUME); + } + + driver_ops = pci_priv->driver_ops; + if (driver_ops && driver_ops->resume) { + ret = driver_ops->resume(pci_dev); + if (ret) + cnss_pr_err("Failed to resume host driver, err = %d\n", + ret); + } + + pci_priv->drv_connected_last = 0; + clear_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state); + +out: + return ret; +} + +static int cnss_pci_suspend_noirq(struct device *dev) +{ + int ret = 0; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_wlan_driver *driver_ops; + + if (!pci_priv) + goto out; + + driver_ops = pci_priv->driver_ops; + if (driver_ops && driver_ops->suspend_noirq) + ret = driver_ops->suspend_noirq(pci_dev); + +out: + return ret; +} + +static int cnss_pci_resume_noirq(struct device *dev) +{ + int ret = 0; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_wlan_driver *driver_ops; + + if (!pci_priv) + goto out; + + driver_ops = pci_priv->driver_ops; + if (driver_ops && driver_ops->resume_noirq && + !pci_priv->pci_link_down_ind) + ret = driver_ops->resume_noirq(pci_dev); + +out: + return ret; +} + +static int cnss_pci_runtime_suspend(struct device *dev) +{ + int ret = 0; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; + struct cnss_wlan_driver *driver_ops; + + if (!pci_priv) + return -EAGAIN; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + return -EAGAIN; + + if (!cnss_is_device_powered_on(pci_priv->plat_priv)) + return -EAGAIN; + + if (pci_priv->pci_link_down_ind) { + cnss_pr_dbg("PCI link down recovery is in progress!\n"); + return -EAGAIN; + } + + cnss_pr_vdbg("Runtime suspend start\n"); + + if (!test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) + pci_priv->drv_connected_last = + cnss_pci_get_drv_connected(pci_priv); + + driver_ops = pci_priv->driver_ops; + if (driver_ops && driver_ops->runtime_ops && + driver_ops->runtime_ops->runtime_suspend) + ret = driver_ops->runtime_ops->runtime_suspend(pci_dev); + else + ret = cnss_auto_suspend(dev); + + if (ret) + pci_priv->drv_connected_last = 0; + + cnss_pr_vdbg("Runtime suspend status: %d\n", ret); + + return ret; +} + +static int cnss_pci_runtime_resume(struct device *dev) +{ + int ret = 0; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_wlan_driver *driver_ops; + + if (!pci_priv) + return -EAGAIN; + + if (!cnss_is_device_powered_on(pci_priv->plat_priv)) + return -EAGAIN; + + if (pci_priv->pci_link_down_ind) { + cnss_pr_dbg("PCI link down recovery is in progress!\n"); + return -EAGAIN; + } + + cnss_pr_vdbg("Runtime resume start\n"); + + driver_ops = pci_priv->driver_ops; + if (driver_ops && driver_ops->runtime_ops && + driver_ops->runtime_ops->runtime_resume) + ret = driver_ops->runtime_ops->runtime_resume(pci_dev); + else + ret = cnss_auto_resume(dev); + + if (!ret) + pci_priv->drv_connected_last = 0; + + cnss_pr_vdbg("Runtime resume status: %d\n", ret); + + return ret; +} + +static int cnss_pci_runtime_idle(struct device *dev) +{ + cnss_pr_vdbg("Runtime idle\n"); + + pm_request_autosuspend(dev); + + return -EBUSY; +} + +int cnss_wlan_pm_control(struct device *dev, bool vote) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + int ret = 0; + + if (!pci_priv) + return -ENODEV; + + ret = msm_pcie_pm_control(vote ? MSM_PCIE_DISABLE_PC : + MSM_PCIE_ENABLE_PC, + pci_dev->bus->number, pci_dev, + NULL, PM_OPTIONS_DEFAULT); + if (ret) + return ret; + + pci_priv->disable_pc = vote; + cnss_pr_dbg("%s PCIe power collapse\n", vote ? "disable" : "enable"); + + return 0; +} +EXPORT_SYMBOL(cnss_wlan_pm_control); + +void cnss_pci_pm_runtime_show_usage_count(struct cnss_pci_data *pci_priv) +{ + struct device *dev; + + if (!pci_priv) + return; + + dev = &pci_priv->pci_dev->dev; + + cnss_pr_dbg("Runtime PM usage count: %d\n", + atomic_read(&dev->power.usage_count)); +} + +int cnss_pci_pm_request_resume(struct cnss_pci_data *pci_priv) +{ + struct pci_dev *pci_dev; + + if (!pci_priv) + return -ENODEV; + + pci_dev = pci_priv->pci_dev; + if (!pci_dev) + return -ENODEV; + + return pm_request_resume(&pci_dev->dev); +} + +int cnss_pci_pm_runtime_resume(struct cnss_pci_data *pci_priv) +{ + struct pci_dev *pci_dev; + + if (!pci_priv) + return -ENODEV; + + pci_dev = pci_priv->pci_dev; + if (!pci_dev) + return -ENODEV; + + return pm_runtime_resume(&pci_dev->dev); +} + +int cnss_pci_pm_runtime_get(struct cnss_pci_data *pci_priv) +{ + if (!pci_priv) + return -ENODEV; + + return pm_runtime_get(&pci_priv->pci_dev->dev); +} + +int cnss_pci_pm_runtime_get_sync(struct cnss_pci_data *pci_priv) +{ + if (!pci_priv) + return -ENODEV; + + return pm_runtime_get_sync(&pci_priv->pci_dev->dev); +} + +void cnss_pci_pm_runtime_get_noresume(struct cnss_pci_data *pci_priv) +{ + if (!pci_priv) + return; + + return pm_runtime_get_noresume(&pci_priv->pci_dev->dev); +} + +int cnss_pci_pm_runtime_put_autosuspend(struct cnss_pci_data *pci_priv) +{ + if (!pci_priv) + return -ENODEV; + + return pm_runtime_put_autosuspend(&pci_priv->pci_dev->dev); +} + +void cnss_pci_pm_runtime_put_noidle(struct cnss_pci_data *pci_priv) +{ + if (!pci_priv) + return; + + pm_runtime_put_noidle(&pci_priv->pci_dev->dev); +} + +void cnss_pci_pm_runtime_mark_last_busy(struct cnss_pci_data *pci_priv) +{ + if (!pci_priv) + return; + + pm_runtime_mark_last_busy(&pci_priv->pci_dev->dev); +} + +int cnss_auto_suspend(struct device *dev) +{ + int ret = 0; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; + + if (!pci_priv) + return -ENODEV; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + return -ENODEV; + + if (pci_priv->pci_link_state == PCI_LINK_UP) { + if (cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_SUSPEND)) { + ret = -EAGAIN; + goto out; + } + + if (pci_priv->drv_connected_last) + goto skip_disable_pci; + + pci_clear_master(pci_dev); + cnss_set_pci_config_space(pci_priv, SAVE_PCI_CONFIG_SPACE); + pci_disable_device(pci_dev); + + ret = pci_set_power_state(pci_dev, PCI_D3hot); + if (ret) + cnss_pr_err("Failed to set D3Hot, err = %d\n", ret); + +skip_disable_pci: + if (cnss_set_pci_link(pci_priv, PCI_LINK_DOWN)) { + ret = -EAGAIN; + goto resume_mhi; + } + + pci_priv->pci_link_state = PCI_LINK_DOWN; + } + + cnss_pci_set_auto_suspended(pci_priv, 1); + cnss_pci_set_monitor_wake_intr(pci_priv, true); + + cnss_request_bus_bandwidth(dev, CNSS_BUS_WIDTH_NONE); + + return 0; + +resume_mhi: + if (pci_enable_device(pci_dev)) + cnss_pr_err("Failed to enable PCI device!\n"); + cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_RESUME); +out: + return ret; +} +EXPORT_SYMBOL(cnss_auto_suspend); + +int cnss_auto_resume(struct device *dev) +{ + int ret = 0; + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; + + if (!pci_priv) + return -ENODEV; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + return -ENODEV; + + if (pci_priv->pci_link_state == PCI_LINK_DOWN) { + if (cnss_set_pci_link(pci_priv, PCI_LINK_UP)) { + cnss_fatal_err("Failed to resume PCI link from suspend\n"); + cnss_pci_link_down(dev); + ret = -EAGAIN; + goto out; + } + pci_priv->pci_link_state = PCI_LINK_UP; + + if (pci_priv->drv_connected_last) + goto skip_enable_pci; + + ret = pci_enable_device(pci_dev); + if (ret) + cnss_pr_err("Failed to enable PCI device, err = %d\n", + ret); + + cnss_set_pci_config_space(pci_priv, RESTORE_PCI_CONFIG_SPACE); + pci_set_master(pci_dev); + +skip_enable_pci: + cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_RESUME); + } + + cnss_pci_set_auto_suspended(pci_priv, 0); + + cnss_request_bus_bandwidth(dev, + plat_priv->bus_bw_info->current_bw_vote); + +out: + return ret; +} +EXPORT_SYMBOL(cnss_auto_resume); + +int cnss_pci_force_wake_request(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; + struct mhi_controller *mhi_ctrl; + + if (!pci_priv) + return -ENODEV; + + if (pci_priv->device_id != QCA6390_DEVICE_ID && + pci_priv->device_id != QCA6490_DEVICE_ID) + return 0; + + mhi_ctrl = pci_priv->mhi_ctrl; + if (!mhi_ctrl) + return -EINVAL; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + return -ENODEV; + + if (test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) + return -EAGAIN; + + mhi_device_get(mhi_ctrl->mhi_dev, MHI_VOTE_DEVICE); + + return 0; +} +EXPORT_SYMBOL(cnss_pci_force_wake_request); + +int cnss_pci_is_device_awake(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct mhi_controller *mhi_ctrl; + + if (!pci_priv) + return -ENODEV; + + if (pci_priv->device_id != QCA6390_DEVICE_ID && + pci_priv->device_id != QCA6490_DEVICE_ID) + return true; + + mhi_ctrl = pci_priv->mhi_ctrl; + if (!mhi_ctrl) + return -EINVAL; + + return (mhi_ctrl->dev_state == MHI_STATE_M0); +} +EXPORT_SYMBOL(cnss_pci_is_device_awake); + +int cnss_pci_force_wake_release(struct device *dev) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv; + struct mhi_controller *mhi_ctrl; + + if (!pci_priv) + return -ENODEV; + + if (pci_priv->device_id != QCA6390_DEVICE_ID && + pci_priv->device_id != QCA6490_DEVICE_ID) + return 0; + + mhi_ctrl = pci_priv->mhi_ctrl; + if (!mhi_ctrl) + return -EINVAL; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + return -ENODEV; + + if (test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) + return -EAGAIN; + + mhi_device_put(mhi_ctrl->mhi_dev, MHI_VOTE_DEVICE); + + return 0; +} +EXPORT_SYMBOL(cnss_pci_force_wake_release); + +int cnss_pci_alloc_fw_mem(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_fw_mem *fw_mem = plat_priv->fw_mem; + int i; + + for (i = 0; i < plat_priv->fw_mem_seg_len; i++) { + if (!fw_mem[i].va && fw_mem[i].size) { + fw_mem[i].va = + dma_alloc_coherent(&pci_priv->pci_dev->dev, + fw_mem[i].size, + &fw_mem[i].pa, GFP_KERNEL); + if (!fw_mem[i].va) { + cnss_pr_err("Failed to allocate memory for FW, size: 0x%zx, type: %u\n", + fw_mem[i].size, fw_mem[i].type); + + return -ENOMEM; + } + } + } + + return 0; +} + +int cnss_pci_alloc_qdss_mem(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem; + int i, j; + + for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) { + if (!qdss_mem[i].va && qdss_mem[i].size) { + qdss_mem[i].va = + dma_alloc_coherent(&pci_priv->pci_dev->dev, + qdss_mem[i].size, + &qdss_mem[i].pa, + GFP_KERNEL); + if (!qdss_mem[i].va) { + cnss_pr_err("Failed to allocate QDSS memory for FW, size: 0x%zx, type: %u, chuck-ID: %d\n", + qdss_mem[i].size, + qdss_mem[i].type, i); + break; + } + } + } + + /* Best-effort allocation for QDSS trace */ + if (i < plat_priv->qdss_mem_seg_len) { + for (j = i; j < plat_priv->qdss_mem_seg_len; j++) { + qdss_mem[j].type = 0; + qdss_mem[j].size = 0; + } + plat_priv->qdss_mem_seg_len = i; + } + + return 0; +} + +void cnss_pci_free_qdss_mem(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem; + int i; + + for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) { + if (qdss_mem[i].va && qdss_mem[i].size) { + cnss_pr_dbg("Freeing memory for QDSS: pa: %pa, size: 0x%zx, type: %u\n", + &qdss_mem[i].pa, qdss_mem[i].size, + qdss_mem[i].type); + dma_free_coherent(&pci_priv->pci_dev->dev, + qdss_mem[i].size, qdss_mem[i].va, + qdss_mem[i].pa); + qdss_mem[i].va = NULL; + qdss_mem[i].pa = 0; + qdss_mem[i].size = 0; + qdss_mem[i].type = 0; + } + } + plat_priv->qdss_mem_seg_len = 0; +} + +static void cnss_pci_free_fw_mem(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_fw_mem *fw_mem = plat_priv->fw_mem; + int i; + + for (i = 0; i < plat_priv->fw_mem_seg_len; i++) { + if (fw_mem[i].va && fw_mem[i].size) { + cnss_pr_dbg("Freeing memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n", + fw_mem[i].va, &fw_mem[i].pa, + fw_mem[i].size, fw_mem[i].type); + dma_free_coherent(&pci_priv->pci_dev->dev, + fw_mem[i].size, fw_mem[i].va, + fw_mem[i].pa); + fw_mem[i].va = NULL; + fw_mem[i].pa = 0; + fw_mem[i].size = 0; + fw_mem[i].type = 0; + } + } + + plat_priv->fw_mem_seg_len = 0; +} + +int cnss_pci_load_m3(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem; + char filename[MAX_M3_FILE_NAME_LENGTH]; + const struct firmware *fw_entry; + int ret = 0; + + if (!m3_mem->va && !m3_mem->size) { + snprintf(filename, sizeof(filename), DEFAULT_M3_FILE_NAME); + + ret = request_firmware(&fw_entry, filename, + &pci_priv->pci_dev->dev); + if (ret) { + cnss_pr_err("Failed to load M3 image: %s\n", filename); + return ret; + } + + m3_mem->va = dma_alloc_coherent(&pci_priv->pci_dev->dev, + fw_entry->size, &m3_mem->pa, + GFP_KERNEL); + if (!m3_mem->va) { + cnss_pr_err("Failed to allocate memory for M3, size: 0x%zx\n", + fw_entry->size); + release_firmware(fw_entry); + return -ENOMEM; + } + + memcpy(m3_mem->va, fw_entry->data, fw_entry->size); + m3_mem->size = fw_entry->size; + release_firmware(fw_entry); + } + + return 0; +} + +static void cnss_pci_free_m3_mem(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem; + + if (m3_mem->va && m3_mem->size) { + cnss_pr_dbg("Freeing memory for M3, va: 0x%pK, pa: %pa, size: 0x%zx\n", + m3_mem->va, &m3_mem->pa, m3_mem->size); + dma_free_coherent(&pci_priv->pci_dev->dev, m3_mem->size, + m3_mem->va, m3_mem->pa); + } + + m3_mem->va = NULL; + m3_mem->pa = 0; + m3_mem->size = 0; +} + +int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv) +{ + int ret; + struct cnss_plat_data *plat_priv; + + if (!pci_priv) + return -ENODEV; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + return -ENODEV; + + cnss_auto_resume(&pci_priv->pci_dev->dev); + cnss_pci_dump_shadow_reg(pci_priv); + + ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_TRIGGER_RDDM); + if (ret) { + cnss_fatal_err("Failed to trigger RDDM, err = %d\n", ret); + cnss_schedule_recovery(&pci_priv->pci_dev->dev, + CNSS_REASON_DEFAULT); + return ret; + } + + if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) { + mod_timer(&plat_priv->fw_boot_timer, + jiffies + msecs_to_jiffies(FW_ASSERT_TIMEOUT)); + } + + return 0; +} + +void cnss_pci_fw_boot_timeout_hdlr(struct cnss_pci_data *pci_priv) +{ + if (!pci_priv) + return; + + cnss_fatal_err("Timeout waiting for FW ready indication\n"); + + cnss_schedule_recovery(&pci_priv->pci_dev->dev, + CNSS_REASON_TIMEOUT); +} + +static int cnss_pci_smmu_fault_handler(struct iommu_domain *domain, + struct device *dev, unsigned long iova, + int flags, void *handler_token) +{ + struct cnss_pci_data *pci_priv = handler_token; + + cnss_pr_err("SMMU fault happened with IOVA 0x%lx\n", iova); + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -ENODEV; + } + + cnss_force_fw_assert(&pci_priv->pci_dev->dev); + + /* IOMMU driver requires non-zero return value to print debug info. */ + return -EINVAL; +} + +static int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv) +{ + struct pci_dev *pci_dev = pci_priv->pci_dev; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct device_node *of_node; + struct resource *res; + const char *iommu_dma_type; + u32 addr_win[2]; + int ret = 0; + + of_node = of_parse_phandle(pci_dev->dev.of_node, "qcom,iommu-group", 0); + if (!of_node) + return ret; + + cnss_pr_dbg("Initializing SMMU\n"); + + pci_priv->iommu_domain = iommu_get_domain_for_dev(&pci_dev->dev); + ret = of_property_read_string(of_node, "qcom,iommu-dma", + &iommu_dma_type); + if (!ret && !strcmp("fastmap", iommu_dma_type)) { + cnss_pr_dbg("Enabling SMMU S1 stage\n"); + pci_priv->smmu_s1_enable = true; + iommu_set_fault_handler(pci_priv->iommu_domain, + cnss_pci_smmu_fault_handler, pci_priv); + } + + ret = of_property_read_u32_array(of_node, "qcom,iommu-dma-addr-pool", + addr_win, ARRAY_SIZE(addr_win)); + if (ret) { + cnss_pr_err("Invalid SMMU size window, err = %d\n", ret); + of_node_put(of_node); + return ret; + } + + pci_priv->smmu_iova_start = addr_win[0]; + pci_priv->smmu_iova_len = addr_win[1]; + cnss_pr_dbg("smmu_iova_start: %pa, smmu_iova_len: 0x%zx\n", + &pci_priv->smmu_iova_start, + pci_priv->smmu_iova_len); + + res = platform_get_resource_byname(plat_priv->plat_dev, IORESOURCE_MEM, + "smmu_iova_ipa"); + if (res) { + pci_priv->smmu_iova_ipa_start = res->start; + pci_priv->smmu_iova_ipa_len = resource_size(res); + cnss_pr_dbg("smmu_iova_ipa_start: %pa, smmu_iova_ipa_len: 0x%zx\n", + &pci_priv->smmu_iova_ipa_start, + pci_priv->smmu_iova_ipa_len); + } + + of_node_put(of_node); + + return 0; +} + +static void cnss_pci_deinit_smmu(struct cnss_pci_data *pci_priv) +{ + pci_priv->iommu_domain = NULL; +} + +struct iommu_domain *cnss_smmu_get_domain(struct device *dev) +{ + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(to_pci_dev(dev)); + + if (!pci_priv) + return NULL; + + return pci_priv->iommu_domain; +} +EXPORT_SYMBOL(cnss_smmu_get_domain); + +int cnss_smmu_map(struct device *dev, + phys_addr_t paddr, uint32_t *iova_addr, size_t size) +{ + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(to_pci_dev(dev)); + unsigned long iova; + size_t len; + int ret = 0; + + if (!pci_priv) + return -ENODEV; + + if (!iova_addr) { + cnss_pr_err("iova_addr is NULL, paddr %pa, size %zu\n", + &paddr, size); + return -EINVAL; + } + + len = roundup(size + paddr - rounddown(paddr, PAGE_SIZE), PAGE_SIZE); + iova = roundup(pci_priv->smmu_iova_ipa_start, PAGE_SIZE); + + if (iova >= + (pci_priv->smmu_iova_ipa_start + pci_priv->smmu_iova_ipa_len)) { + cnss_pr_err("No IOVA space to map, iova %lx, smmu_iova_ipa_start %pad, smmu_iova_ipa_len %zu\n", + iova, + &pci_priv->smmu_iova_ipa_start, + pci_priv->smmu_iova_ipa_len); + return -ENOMEM; + } + + ret = iommu_map(pci_priv->iommu_domain, iova, + rounddown(paddr, PAGE_SIZE), len, + IOMMU_READ | IOMMU_WRITE); + if (ret) { + cnss_pr_err("PA to IOVA mapping failed, ret %d\n", ret); + return ret; + } + + pci_priv->smmu_iova_ipa_start = iova + len; + *iova_addr = (uint32_t)(iova + paddr - rounddown(paddr, PAGE_SIZE)); + + return 0; +} +EXPORT_SYMBOL(cnss_smmu_map); + +int cnss_get_soc_info(struct device *dev, struct cnss_soc_info *info) +{ + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(to_pci_dev(dev)); + struct cnss_plat_data *plat_priv; + + if (!pci_priv) + return -ENODEV; + + plat_priv = pci_priv->plat_priv; + if (!plat_priv) + return -ENODEV; + + info->va = pci_priv->bar; + info->pa = pci_resource_start(pci_priv->pci_dev, PCI_BAR_NUM); + + memcpy(&info->device_version, &plat_priv->device_version, + sizeof(info->device_version)); + + return 0; +} +EXPORT_SYMBOL(cnss_get_soc_info); + +static struct cnss_msi_config msi_config = { + .total_vectors = 32, + .total_users = 4, + .users = (struct cnss_msi_user[]) { + { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, + { .name = "CE", .num_vectors = 10, .base_vector = 3 }, + { .name = "WAKE", .num_vectors = 1, .base_vector = 13 }, + { .name = "DP", .num_vectors = 18, .base_vector = 14 }, + }, +}; + +static int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv) +{ + pci_priv->msi_config = &msi_config; + + return 0; +} + +static int cnss_pci_enable_msi(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct pci_dev *pci_dev = pci_priv->pci_dev; + int num_vectors; + struct cnss_msi_config *msi_config; + struct msi_desc *msi_desc; + + ret = cnss_pci_get_msi_assignment(pci_priv); + if (ret) { + cnss_pr_err("Failed to get MSI assignment, err = %d\n", ret); + goto out; + } + + msi_config = pci_priv->msi_config; + if (!msi_config) { + cnss_pr_err("msi_config is NULL!\n"); + ret = -EINVAL; + goto out; + } + + num_vectors = pci_alloc_irq_vectors(pci_dev, + msi_config->total_vectors, + msi_config->total_vectors, + PCI_IRQ_MSI); + if (num_vectors != msi_config->total_vectors) { + cnss_pr_err("Failed to get enough MSI vectors (%d), available vectors = %d", + msi_config->total_vectors, num_vectors); + if (num_vectors >= 0) + ret = -EINVAL; + goto reset_msi_config; + } + + msi_desc = irq_get_msi_desc(pci_dev->irq); + if (!msi_desc) { + cnss_pr_err("msi_desc is NULL!\n"); + ret = -EINVAL; + goto free_msi_vector; + } + + pci_priv->msi_ep_base_data = msi_desc->msg.data; + if (!pci_priv->msi_ep_base_data) { + cnss_pr_err("Got 0 MSI base data!\n"); + CNSS_ASSERT(0); + } + + cnss_pr_dbg("MSI base data is %d\n", pci_priv->msi_ep_base_data); + + return 0; + +free_msi_vector: + pci_free_irq_vectors(pci_priv->pci_dev); +reset_msi_config: + pci_priv->msi_config = NULL; +out: + return ret; +} + +static void cnss_pci_disable_msi(struct cnss_pci_data *pci_priv) +{ + pci_free_irq_vectors(pci_priv->pci_dev); +} + +int cnss_get_user_msi_assignment(struct device *dev, char *user_name, + int *num_vectors, u32 *user_base_data, + u32 *base_vector) +{ + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(to_pci_dev(dev)); + struct cnss_msi_config *msi_config; + int idx; + + if (!pci_priv) + return -ENODEV; + + msi_config = pci_priv->msi_config; + if (!msi_config) { + cnss_pr_err("MSI is not supported.\n"); + return -EINVAL; + } + + for (idx = 0; idx < msi_config->total_users; idx++) { + if (strcmp(user_name, msi_config->users[idx].name) == 0) { + *num_vectors = msi_config->users[idx].num_vectors; + *user_base_data = msi_config->users[idx].base_vector + + pci_priv->msi_ep_base_data; + *base_vector = msi_config->users[idx].base_vector; + + cnss_pr_dbg("Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", + user_name, *num_vectors, *user_base_data, + *base_vector); + + return 0; + } + } + + cnss_pr_err("Failed to find MSI assignment for %s!\n", user_name); + + return -EINVAL; +} +EXPORT_SYMBOL(cnss_get_user_msi_assignment); + +int cnss_get_msi_irq(struct device *dev, unsigned int vector) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + int irq_num; + + irq_num = pci_irq_vector(pci_dev, vector); + cnss_pr_dbg("Get IRQ number %d for vector index %d\n", irq_num, vector); + + return irq_num; +} +EXPORT_SYMBOL(cnss_get_msi_irq); + +void cnss_get_msi_address(struct device *dev, u32 *msi_addr_low, + u32 *msi_addr_high) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + + pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, + msi_addr_low); + + pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, + msi_addr_high); +} +EXPORT_SYMBOL(cnss_get_msi_address); + +u32 cnss_pci_get_wake_msi(struct cnss_pci_data *pci_priv) +{ + int ret, num_vectors; + u32 user_base_data, base_vector; + + if (!pci_priv) + return -ENODEV; + + ret = cnss_get_user_msi_assignment(&pci_priv->pci_dev->dev, + WAKE_MSI_NAME, &num_vectors, + &user_base_data, &base_vector); + if (ret) { + cnss_pr_err("WAKE MSI is not valid\n"); + return 0; + } + + return user_base_data; +} + +static int cnss_pci_enable_bus(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct pci_dev *pci_dev = pci_priv->pci_dev; + u16 device_id; + u32 pci_dma_mask = PCI_DMA_MASK_64_BIT; + + pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id); + if (device_id != pci_priv->pci_device_id->device) { + cnss_pr_err("PCI device ID mismatch, config ID: 0x%x, probe ID: 0x%x\n", + device_id, pci_priv->pci_device_id->device); + ret = -EIO; + goto out; + } + + ret = pci_assign_resource(pci_dev, PCI_BAR_NUM); + if (ret) { + pr_err("Failed to assign PCI resource, err = %d\n", ret); + goto out; + } + + ret = pci_enable_device(pci_dev); + if (ret) { + cnss_pr_err("Failed to enable PCI device, err = %d\n", ret); + goto out; + } + + ret = pci_request_region(pci_dev, PCI_BAR_NUM, "cnss"); + if (ret) { + cnss_pr_err("Failed to request PCI region, err = %d\n", ret); + goto disable_device; + } + + if (device_id == QCA6174_DEVICE_ID) + pci_dma_mask = PCI_DMA_MASK_32_BIT; + + ret = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(pci_dma_mask)); + if (ret) { + cnss_pr_err("Failed to set PCI DMA mask (%d), err = %d\n", + ret, pci_dma_mask); + goto release_region; + } + + ret = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(pci_dma_mask)); + if (ret) { + cnss_pr_err("Failed to set PCI consistent DMA mask (%d), err = %d\n", + ret, pci_dma_mask); + goto release_region; + } + + pci_set_master(pci_dev); + + pci_priv->bar = pci_iomap(pci_dev, PCI_BAR_NUM, 0); + if (!pci_priv->bar) { + cnss_pr_err("Failed to do PCI IO map!\n"); + ret = -EIO; + goto clear_master; + } + return 0; + +clear_master: + pci_clear_master(pci_dev); +release_region: + pci_release_region(pci_dev, PCI_BAR_NUM); +disable_device: + pci_disable_device(pci_dev); +out: + return ret; +} + +static void cnss_pci_disable_bus(struct cnss_pci_data *pci_priv) +{ + struct pci_dev *pci_dev = pci_priv->pci_dev; + + if (pci_priv->bar) { + pci_iounmap(pci_dev, pci_priv->bar); + pci_priv->bar = NULL; + } + + pci_clear_master(pci_dev); + pci_release_region(pci_dev, PCI_BAR_NUM); + if (pci_is_enabled(pci_dev)) + pci_disable_device(pci_dev); +} + +static void cnss_pci_dump_qdss_reg(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + int i, array_size = ARRAY_SIZE(qdss_csr) - 1; + gfp_t gfp = GFP_KERNEL; + u32 reg_offset; + + if (in_interrupt() || irqs_disabled()) + gfp = GFP_ATOMIC; + + if (!plat_priv->qdss_reg) { + plat_priv->qdss_reg = devm_kzalloc(&pci_priv->pci_dev->dev, + sizeof(*plat_priv->qdss_reg) + * array_size, gfp); + if (!plat_priv->qdss_reg) + return; + } + + for (i = 0; qdss_csr[i].name; i++) { + reg_offset = QDSS_APB_DEC_CSR_BASE + qdss_csr[i].offset; + if (cnss_pci_reg_read(pci_priv, reg_offset, + &plat_priv->qdss_reg[i])) + return; + cnss_pr_dbg("%s[0x%x] = 0x%x\n", qdss_csr[i].name, reg_offset, + plat_priv->qdss_reg[i]); + } +} + +static void cnss_pci_dump_ce_reg(struct cnss_pci_data *pci_priv, + enum cnss_ce_index ce) +{ + int i; + u32 ce_base = ce * QCA6390_CE_REG_INTERVAL; + u32 reg_offset, val; + + switch (ce) { + case CNSS_CE_09: + case CNSS_CE_10: + for (i = 0; ce_src[i].name; i++) { + reg_offset = QCA6390_CE_SRC_RING_REG_BASE + + ce_base + ce_src[i].offset; + if (cnss_pci_reg_read(pci_priv, reg_offset, &val)) + return; + cnss_pr_dbg("CE_%02d_%s[0x%x] = 0x%x\n", + ce, ce_src[i].name, reg_offset, val); + } + + for (i = 0; ce_dst[i].name; i++) { + reg_offset = QCA6390_CE_DST_RING_REG_BASE + + ce_base + ce_dst[i].offset; + if (cnss_pci_reg_read(pci_priv, reg_offset, &val)) + return; + cnss_pr_dbg("CE_%02d_%s[0x%x] = 0x%x\n", + ce, ce_dst[i].name, reg_offset, val); + } + break; + case CNSS_CE_COMMON: + for (i = 0; ce_cmn[i].name; i++) { + reg_offset = QCA6390_CE_COMMON_REG_BASE + + ce_cmn[i].offset; + if (cnss_pci_reg_read(pci_priv, reg_offset, &val)) + return; + cnss_pr_dbg("CE_COMMON_%s[0x%x] = 0x%x\n", + ce_cmn[i].name, reg_offset, val); + } + break; + default: + cnss_pr_err("Unsupported CE[%d] registers dump\n", ce); + } +} + +static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv) +{ + cnss_pr_dbg("Start to dump debug registers\n"); + + if (cnss_pci_check_link_status(pci_priv)) + return; + + mhi_debug_reg_dump(pci_priv->mhi_ctrl); + cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON); + cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09); + cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_10); +} + +void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct cnss_dump_data *dump_data = + &plat_priv->ramdump_info_v2.dump_data; + struct cnss_dump_seg *dump_seg = + plat_priv->ramdump_info_v2.dump_data_vaddr; + struct image_info *fw_image, *rddm_image; + struct cnss_fw_mem *fw_mem = plat_priv->fw_mem; + int ret, i; + + if (test_bit(CNSS_MHI_RDDM_DONE, &pci_priv->mhi_state)) { + cnss_pr_dbg("RAM dump is already collected, skip\n"); + return; + } + + if (cnss_pci_check_link_status(pci_priv)) + return; + + cnss_pci_dump_qdss_reg(pci_priv); + + ret = mhi_download_rddm_img(pci_priv->mhi_ctrl, in_panic); + if (ret) { + cnss_fatal_err("Failed to download RDDM image, err = %d\n", + ret); + cnss_pci_dump_registers(pci_priv); + return; + } + + fw_image = pci_priv->mhi_ctrl->fbc_image; + rddm_image = pci_priv->mhi_ctrl->rddm_image; + dump_data->nentries = 0; + + cnss_pr_dbg("Collect FW image dump segment, nentries %d\n", + fw_image->entries); + + for (i = 0; i < fw_image->entries; i++) { + dump_seg->address = fw_image->mhi_buf[i].dma_addr; + dump_seg->v_address = fw_image->mhi_buf[i].buf; + dump_seg->size = fw_image->mhi_buf[i].len; + dump_seg->type = CNSS_FW_IMAGE; + cnss_pr_dbg("seg-%d: address 0x%lx, v_address %pK, size 0x%lx\n", + i, dump_seg->address, + dump_seg->v_address, dump_seg->size); + dump_seg++; + } + + dump_data->nentries += fw_image->entries; + + cnss_pr_dbg("Collect RDDM image dump segment, nentries %d\n", + rddm_image->entries); + + for (i = 0; i < rddm_image->entries; i++) { + dump_seg->address = rddm_image->mhi_buf[i].dma_addr; + dump_seg->v_address = rddm_image->mhi_buf[i].buf; + dump_seg->size = rddm_image->mhi_buf[i].len; + dump_seg->type = CNSS_FW_RDDM; + cnss_pr_dbg("seg-%d: address 0x%lx, v_address %pK, size 0x%lx\n", + i, dump_seg->address, + dump_seg->v_address, dump_seg->size); + dump_seg++; + } + + dump_data->nentries += rddm_image->entries; + + cnss_pr_dbg("Collect remote heap dump segment\n"); + + for (i = 0; i < plat_priv->fw_mem_seg_len; i++) { + if (fw_mem[i].type == CNSS_MEM_TYPE_DDR) { + dump_seg->address = fw_mem[i].pa; + dump_seg->v_address = fw_mem[i].va; + dump_seg->size = fw_mem[i].size; + dump_seg->type = CNSS_FW_REMOTE_HEAP; + cnss_pr_dbg("seg-%d: address 0x%lx, v_address %pK, size 0x%lx\n", + i, dump_seg->address, dump_seg->v_address, + dump_seg->size); + dump_seg++; + dump_data->nentries++; + } + } + + if (dump_data->nentries > 0) + plat_priv->ramdump_info_v2.dump_data_valid = true; + + cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_RDDM_DONE); + complete(&plat_priv->rddm_complete); +} + +void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + + plat_priv->ramdump_info_v2.dump_data.nentries = 0; + plat_priv->ramdump_info_v2.dump_data_valid = false; +} + +static int cnss_mhi_pm_runtime_get(struct mhi_controller *mhi_ctrl, void *priv) +{ + struct cnss_pci_data *pci_priv = priv; + + return cnss_pci_pm_runtime_get(pci_priv); +} + +static void cnss_mhi_pm_runtime_put_noidle(struct mhi_controller *mhi_ctrl, + void *priv) +{ + struct cnss_pci_data *pci_priv = priv; + + cnss_pci_pm_runtime_put_noidle(pci_priv); +} + +static char *cnss_mhi_notify_status_to_str(enum MHI_CB status) +{ + switch (status) { + case MHI_CB_IDLE: + return "IDLE"; + case MHI_CB_EE_RDDM: + return "RDDM"; + case MHI_CB_SYS_ERROR: + return "SYS_ERROR"; + case MHI_CB_FATAL_ERROR: + return "FATAL_ERROR"; + default: + return "UNKNOWN"; + } +}; + +static void cnss_dev_rddm_timeout_hdlr(struct timer_list *t) +{ + struct cnss_pci_data *pci_priv = + from_timer(pci_priv, t, dev_rddm_timer); + + if (!pci_priv) + return; + + cnss_fatal_err("Timeout waiting for RDDM notification\n"); + + cnss_schedule_recovery(&pci_priv->pci_dev->dev, CNSS_REASON_TIMEOUT); +} + +static int cnss_mhi_link_status(struct mhi_controller *mhi_ctrl, void *priv) +{ + struct cnss_pci_data *pci_priv = priv; + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL\n"); + return -EINVAL; + } + + return cnss_pci_check_link_status(pci_priv); +} + +static void cnss_mhi_notify_status(struct mhi_controller *mhi_ctrl, void *priv, + enum MHI_CB reason) +{ + struct cnss_pci_data *pci_priv = priv; + struct cnss_plat_data *plat_priv; + enum cnss_recovery_reason cnss_reason; + + if (!pci_priv) { + cnss_pr_err("pci_priv is NULL"); + return; + } + + plat_priv = pci_priv->plat_priv; + + if (reason != MHI_CB_IDLE) + cnss_pr_dbg("MHI status cb is called with reason %s(%d)\n", + cnss_mhi_notify_status_to_str(reason), reason); + + switch (reason) { + case MHI_CB_IDLE: + return; + case MHI_CB_FATAL_ERROR: + set_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); + del_timer(&plat_priv->fw_boot_timer); + cnss_pci_update_status(pci_priv, CNSS_FW_DOWN); + cnss_reason = CNSS_REASON_DEFAULT; + break; + case MHI_CB_SYS_ERROR: + set_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); + del_timer(&plat_priv->fw_boot_timer); + mod_timer(&pci_priv->dev_rddm_timer, + jiffies + msecs_to_jiffies(DEV_RDDM_TIMEOUT)); + cnss_pci_update_status(pci_priv, CNSS_FW_DOWN); + return; + case MHI_CB_EE_RDDM: + set_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state); + del_timer(&plat_priv->fw_boot_timer); + del_timer(&pci_priv->dev_rddm_timer); + cnss_pci_update_status(pci_priv, CNSS_FW_DOWN); + cnss_reason = CNSS_REASON_RDDM; + break; + default: + cnss_pr_err("Unsupported MHI status cb reason: %d\n", reason); + return; + } + + cnss_schedule_recovery(&pci_priv->pci_dev->dev, cnss_reason); +} + +static int cnss_pci_get_mhi_msi(struct cnss_pci_data *pci_priv) +{ + int ret, num_vectors, i; + u32 user_base_data, base_vector; + int *irq; + + ret = cnss_get_user_msi_assignment(&pci_priv->pci_dev->dev, + MHI_MSI_NAME, &num_vectors, + &user_base_data, &base_vector); + if (ret) + return ret; + + cnss_pr_dbg("Number of assigned MSI for MHI is %d, base vector is %d\n", + num_vectors, base_vector); + + irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); + if (!irq) + return -ENOMEM; + + for (i = 0; i < num_vectors; i++) + irq[i] = cnss_get_msi_irq(&pci_priv->pci_dev->dev, + base_vector + i); + + pci_priv->mhi_ctrl->irq = irq; + pci_priv->mhi_ctrl->msi_allocated = num_vectors; + + return 0; +} + +static void cnss_pci_update_fw_name(struct cnss_pci_data *pci_priv) +{ + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct mhi_controller *mhi_ctrl = pci_priv->mhi_ctrl; + + plat_priv->device_version.family_number = mhi_ctrl->family_number; + plat_priv->device_version.device_number = mhi_ctrl->device_number; + plat_priv->device_version.major_version = mhi_ctrl->major_version; + plat_priv->device_version.minor_version = mhi_ctrl->minor_version; + + cnss_pr_dbg("Get device version info, family number: 0x%x, device number: 0x%x, major version: 0x%x, minor version: 0x%x\n", + plat_priv->device_version.family_number, + plat_priv->device_version.device_number, + plat_priv->device_version.major_version, + plat_priv->device_version.minor_version); + + if (pci_priv->device_id == QCA6390_DEVICE_ID && + plat_priv->device_version.major_version >= FW_V2_NUMBER) { + scnprintf(plat_priv->firmware_name, + sizeof(plat_priv->firmware_name), FW_V2_FILE_NAME); + mhi_ctrl->fw_image = plat_priv->firmware_name; + } + + cnss_pr_dbg("Firmware name is %s\n", mhi_ctrl->fw_image); +} + +static int cnss_pci_register_mhi(struct cnss_pci_data *pci_priv) +{ + int ret = 0; + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + struct pci_dev *pci_dev = pci_priv->pci_dev; + struct mhi_controller *mhi_ctrl; + + mhi_ctrl = mhi_alloc_controller(0); + if (!mhi_ctrl) { + cnss_pr_err("Invalid MHI controller context\n"); + return -EINVAL; + } + + pci_priv->mhi_ctrl = mhi_ctrl; + + mhi_ctrl->priv_data = pci_priv; + mhi_ctrl->dev = &pci_dev->dev; + mhi_ctrl->of_node = (&plat_priv->plat_dev->dev)->of_node; + mhi_ctrl->dev_id = pci_priv->device_id; + mhi_ctrl->domain = pci_domain_nr(pci_dev->bus); + mhi_ctrl->bus = pci_dev->bus->number; + mhi_ctrl->slot = PCI_SLOT(pci_dev->devfn); + + mhi_ctrl->fw_image = plat_priv->firmware_name; + + mhi_ctrl->regs = pci_priv->bar; + cnss_pr_dbg("BAR starts at %pa\n", + &pci_resource_start(pci_priv->pci_dev, PCI_BAR_NUM)); + + ret = cnss_pci_get_mhi_msi(pci_priv); + if (ret) { + cnss_pr_err("Failed to get MSI for MHI\n"); + return ret; + } + + if (pci_priv->smmu_s1_enable) { + mhi_ctrl->iova_start = pci_priv->smmu_iova_start; + mhi_ctrl->iova_stop = pci_priv->smmu_iova_start + + pci_priv->smmu_iova_len; + } else { + mhi_ctrl->iova_start = memblock_start_of_DRAM(); + mhi_ctrl->iova_stop = memblock_end_of_DRAM(); + } + + mhi_ctrl->link_status = cnss_mhi_link_status; + mhi_ctrl->status_cb = cnss_mhi_notify_status; + mhi_ctrl->runtime_get = cnss_mhi_pm_runtime_get; + mhi_ctrl->runtime_put = cnss_mhi_pm_runtime_put_noidle; + + mhi_ctrl->rddm_size = pci_priv->plat_priv->ramdump_info_v2.ramdump_size; + mhi_ctrl->sbl_size = SZ_512K; + mhi_ctrl->seg_len = SZ_512K; + mhi_ctrl->fbc_download = true; + + mhi_ctrl->log_buf = ipc_log_context_create(CNSS_IPC_LOG_PAGES, + "cnss-mhi", 0); + if (!mhi_ctrl->log_buf) + cnss_pr_err("Unable to create CNSS MHI IPC log context\n"); + + ret = of_register_mhi_controller(mhi_ctrl); + if (ret) { + cnss_pr_err("Failed to register to MHI bus, err = %d\n", ret); + return ret; + } + + cnss_pci_update_fw_name(pci_priv); + + return 0; +} + +static void cnss_pci_unregister_mhi(struct cnss_pci_data *pci_priv) +{ + struct mhi_controller *mhi_ctrl = pci_priv->mhi_ctrl; + + mhi_unregister_mhi_controller(mhi_ctrl); + ipc_log_context_destroy(mhi_ctrl->log_buf); + kfree(mhi_ctrl->irq); +} + +static int cnss_pci_probe(struct pci_dev *pci_dev, + const struct pci_device_id *id) +{ + int ret = 0; + struct cnss_pci_data *pci_priv; + struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(NULL); + + cnss_pr_dbg("PCI is probing, vendor ID: 0x%x, device ID: 0x%x\n", + id->vendor, pci_dev->device); + + pci_priv = devm_kzalloc(&pci_dev->dev, sizeof(*pci_priv), + GFP_KERNEL); + if (!pci_priv) { + ret = -ENOMEM; + goto out; + } + + pci_dev->no_d3hot = true; + pci_priv->pci_link_state = PCI_LINK_UP; + pci_priv->plat_priv = plat_priv; + pci_priv->pci_dev = pci_dev; + pci_priv->pci_device_id = id; + pci_priv->device_id = pci_dev->device; + cnss_set_pci_priv(pci_dev, pci_priv); + plat_priv->device_id = pci_dev->device; + plat_priv->bus_priv = pci_priv; + snprintf(plat_priv->firmware_name, sizeof(plat_priv->firmware_name), + DEFAULT_FW_FILE_NAME); + + ret = cnss_register_subsys(plat_priv); + if (ret) + goto reset_ctx; + + ret = cnss_register_ramdump(plat_priv); + if (ret) + goto unregister_subsys; + + ret = cnss_pci_init_smmu(pci_priv); + if (ret) + goto unregister_ramdump; + + ret = cnss_reg_pci_event(pci_priv); + if (ret) { + cnss_pr_err("Failed to register PCI event, err = %d\n", ret); + goto deinit_smmu; + } + + ret = cnss_pci_enable_bus(pci_priv); + if (ret) + goto dereg_pci_event; + + pci_save_state(pci_dev); + pci_priv->default_state = pci_store_saved_state(pci_dev); + + switch (pci_dev->device) { + case QCA6174_DEVICE_ID: + pci_read_config_word(pci_dev, QCA6174_REV_ID_OFFSET, + &pci_priv->revision_id); + ret = cnss_suspend_pci_link(pci_priv); + if (ret) + cnss_pr_err("Failed to suspend PCI link, err = %d\n", + ret); + cnss_power_off_device(plat_priv); + break; + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + timer_setup(&pci_priv->dev_rddm_timer, + cnss_dev_rddm_timeout_hdlr, 0); + INIT_DELAYED_WORK(&pci_priv->time_sync_work, + cnss_pci_time_sync_work_hdlr); + + ret = cnss_pci_enable_msi(pci_priv); + if (ret) + goto disable_bus; + ret = cnss_pci_register_mhi(pci_priv); + if (ret) { + cnss_pci_disable_msi(pci_priv); + goto disable_bus; + } + cnss_pci_get_link_status(pci_priv); + if (EMULATION_HW) + break; + ret = cnss_suspend_pci_link(pci_priv); + if (ret) + cnss_pr_err("Failed to suspend PCI link, err = %d\n", + ret); + cnss_power_off_device(plat_priv); + break; + default: + cnss_pr_err("Unknown PCI device found: 0x%x\n", + pci_dev->device); + ret = -ENODEV; + goto disable_bus; + } + + return 0; + +disable_bus: + cnss_pci_disable_bus(pci_priv); +dereg_pci_event: + cnss_dereg_pci_event(pci_priv); +deinit_smmu: + cnss_pci_deinit_smmu(pci_priv); +unregister_ramdump: + cnss_unregister_ramdump(plat_priv); +unregister_subsys: + cnss_unregister_subsys(plat_priv); +reset_ctx: + plat_priv->bus_priv = NULL; +out: + return ret; +} + +static void cnss_pci_remove(struct pci_dev *pci_dev) +{ + struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + struct cnss_plat_data *plat_priv = + cnss_bus_dev_to_plat_priv(&pci_dev->dev); + + cnss_pci_free_m3_mem(pci_priv); + cnss_pci_free_fw_mem(pci_priv); + cnss_pci_free_qdss_mem(pci_priv); + + switch (pci_dev->device) { + case QCA6290_DEVICE_ID: + case QCA6390_DEVICE_ID: + case QCA6490_DEVICE_ID: + cnss_pci_unregister_mhi(pci_priv); + cnss_pci_disable_msi(pci_priv); + del_timer(&pci_priv->dev_rddm_timer); + break; + default: + break; + } + + pci_load_and_free_saved_state(pci_dev, &pci_priv->saved_state); + + cnss_pci_disable_bus(pci_priv); + cnss_dereg_pci_event(pci_priv); + cnss_pci_deinit_smmu(pci_priv); + cnss_unregister_ramdump(plat_priv); + cnss_unregister_subsys(plat_priv); + plat_priv->bus_priv = NULL; +} + +static const struct pci_device_id cnss_pci_id_table[] = { + { QCA6174_VENDOR_ID, QCA6174_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, + { QCA6290_VENDOR_ID, QCA6290_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, + { QCA6390_VENDOR_ID, QCA6390_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, + { QCA6490_VENDOR_ID, QCA6490_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID }, + { 0 } +}; +MODULE_DEVICE_TABLE(pci, cnss_pci_id_table); + +static const struct dev_pm_ops cnss_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(cnss_pci_suspend, cnss_pci_resume) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cnss_pci_suspend_noirq, + cnss_pci_resume_noirq) + SET_RUNTIME_PM_OPS(cnss_pci_runtime_suspend, cnss_pci_runtime_resume, + cnss_pci_runtime_idle) +}; + +struct pci_driver cnss_pci_driver = { + .name = "cnss_pci", + .id_table = cnss_pci_id_table, + .probe = cnss_pci_probe, + .remove = cnss_pci_remove, + .driver = { + .pm = &cnss_pm_ops, + }, +}; + +int cnss_pci_init(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + struct device *dev = &plat_priv->plat_dev->dev; + u32 rc_num; + + ret = of_property_read_u32(dev->of_node, "qcom,wlan-rc-num", &rc_num); + if (ret) { + cnss_pr_err("Failed to find PCIe RC number, err = %d\n", ret); + goto out; + } + + ret = msm_pcie_enumerate(rc_num); + if (ret) { + cnss_pr_err("Failed to enable PCIe RC%x, err = %d\n", + rc_num, ret); + goto out; + } + + ret = pci_register_driver(&cnss_pci_driver); + if (ret) { + cnss_pr_err("Failed to register to PCI framework, err = %d\n", + ret); + goto out; + } + + return 0; +out: + return ret; +} + +void cnss_pci_deinit(struct cnss_plat_data *plat_priv) +{ + pci_unregister_driver(&cnss_pci_driver); +} diff --git a/drivers/net/wireless/cnss2/pci.h b/drivers/net/wireless/cnss2/pci.h new file mode 100644 index 000000000000..769ba6651bf2 --- /dev/null +++ b/drivers/net/wireless/cnss2/pci.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ + +#ifndef _CNSS_PCI_H +#define _CNSS_PCI_H + +#include +#include +#include +#include +#include + +#include "main.h" + +enum cnss_mhi_state { + CNSS_MHI_INIT, + CNSS_MHI_DEINIT, + CNSS_MHI_POWER_ON, + CNSS_MHI_POWER_OFF, + CNSS_MHI_FORCE_POWER_OFF, + CNSS_MHI_SUSPEND, + CNSS_MHI_RESUME, + CNSS_MHI_TRIGGER_RDDM, + CNSS_MHI_RDDM, + CNSS_MHI_RDDM_DONE, +}; + +enum pci_link_status { + PCI_GEN1, + PCI_GEN2, + PCI_DEF, +}; + +struct cnss_msi_user { + char *name; + int num_vectors; + u32 base_vector; +}; + +struct cnss_msi_config { + int total_vectors; + int total_users; + struct cnss_msi_user *users; +}; + +struct cnss_pci_reg { + char *name; + u32 offset; +}; + +struct cnss_pci_debug_reg { + u32 offset; + u32 val; +}; + +struct cnss_pci_data { + struct pci_dev *pci_dev; + struct cnss_plat_data *plat_priv; + const struct pci_device_id *pci_device_id; + u32 device_id; + u16 revision_id; + struct cnss_wlan_driver *driver_ops; + u8 pci_link_state; + u8 pci_link_down_ind; + struct pci_saved_state *saved_state; + struct pci_saved_state *default_state; + struct msm_pcie_register_event msm_pci_event; + atomic_t auto_suspended; + atomic_t drv_connected; + u8 drv_connected_last; + u16 def_link_speed; + u16 def_link_width; + u8 monitor_wake_intr; + struct iommu_domain *iommu_domain; + u8 smmu_s1_enable; + dma_addr_t smmu_iova_start; + size_t smmu_iova_len; + dma_addr_t smmu_iova_ipa_start; + size_t smmu_iova_ipa_len; + void __iomem *bar; + struct cnss_msi_config *msi_config; + u32 msi_ep_base_data; + struct mhi_controller *mhi_ctrl; + unsigned long mhi_state; + u32 remap_window; + struct timer_list dev_rddm_timer; + struct delayed_work time_sync_work; + u8 disable_pc; + struct cnss_pci_debug_reg *debug_reg; +}; + +static inline void cnss_set_pci_priv(struct pci_dev *pci_dev, void *data) +{ + pci_set_drvdata(pci_dev, data); +} + +static inline struct cnss_pci_data *cnss_get_pci_priv(struct pci_dev *pci_dev) +{ + return pci_get_drvdata(pci_dev); +} + +static inline struct cnss_plat_data *cnss_pci_priv_to_plat_priv(void *bus_priv) +{ + struct cnss_pci_data *pci_priv = bus_priv; + + return pci_priv->plat_priv; +} + +static inline void cnss_pci_set_monitor_wake_intr(void *bus_priv, bool val) +{ + struct cnss_pci_data *pci_priv = bus_priv; + + pci_priv->monitor_wake_intr = val; +} + +static inline bool cnss_pci_get_monitor_wake_intr(void *bus_priv) +{ + struct cnss_pci_data *pci_priv = bus_priv; + + return pci_priv->monitor_wake_intr; +} + +static inline void cnss_pci_set_auto_suspended(void *bus_priv, int val) +{ + struct cnss_pci_data *pci_priv = bus_priv; + + atomic_set(&pci_priv->auto_suspended, val); +} + +static inline int cnss_pci_get_auto_suspended(void *bus_priv) +{ + struct cnss_pci_data *pci_priv = bus_priv; + + return atomic_read(&pci_priv->auto_suspended); +} + +static inline void cnss_pci_set_drv_connected(void *bus_priv, int val) +{ + struct cnss_pci_data *pci_priv = bus_priv; + + atomic_set(&pci_priv->drv_connected, val); +} + +static inline int cnss_pci_get_drv_connected(void *bus_priv) +{ + struct cnss_pci_data *pci_priv = bus_priv; + + return atomic_read(&pci_priv->drv_connected); +} + +int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv); +int cnss_resume_pci_link(struct cnss_pci_data *pci_priv); +int cnss_pci_init(struct cnss_plat_data *plat_priv); +void cnss_pci_deinit(struct cnss_plat_data *plat_priv); +int cnss_pci_alloc_fw_mem(struct cnss_pci_data *pci_priv); +int cnss_pci_alloc_qdss_mem(struct cnss_pci_data *pci_priv); +void cnss_pci_free_qdss_mem(struct cnss_pci_data *pci_priv); +int cnss_pci_load_m3(struct cnss_pci_data *pci_priv); +int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv); +void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic); +void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv); +u32 cnss_pci_get_wake_msi(struct cnss_pci_data *pci_priv); +int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv); +void cnss_pci_fw_boot_timeout_hdlr(struct cnss_pci_data *pci_priv); +int cnss_pci_call_driver_probe(struct cnss_pci_data *pci_priv); +int cnss_pci_call_driver_remove(struct cnss_pci_data *pci_priv); +int cnss_pci_dev_powerup(struct cnss_pci_data *pci_priv); +int cnss_pci_dev_shutdown(struct cnss_pci_data *pci_priv); +int cnss_pci_dev_crash_shutdown(struct cnss_pci_data *pci_priv); +int cnss_pci_dev_ramdump(struct cnss_pci_data *pci_priv); +int cnss_pci_register_driver_hdlr(struct cnss_pci_data *pci_priv, void *data); +int cnss_pci_unregister_driver_hdlr(struct cnss_pci_data *pci_priv); +int cnss_pci_call_driver_modem_status(struct cnss_pci_data *pci_priv, + int modem_current_status); +void cnss_pci_pm_runtime_show_usage_count(struct cnss_pci_data *pci_priv); +int cnss_pci_pm_request_resume(struct cnss_pci_data *pci_priv); +int cnss_pci_pm_runtime_resume(struct cnss_pci_data *pci_priv); +int cnss_pci_pm_runtime_get(struct cnss_pci_data *pci_priv); +int cnss_pci_pm_runtime_get_sync(struct cnss_pci_data *pci_priv); +void cnss_pci_pm_runtime_get_noresume(struct cnss_pci_data *pci_priv); +int cnss_pci_pm_runtime_put_autosuspend(struct cnss_pci_data *pci_priv); +void cnss_pci_pm_runtime_put_noidle(struct cnss_pci_data *pci_priv); +void cnss_pci_pm_runtime_mark_last_busy(struct cnss_pci_data *pci_priv); +int cnss_pci_update_status(struct cnss_pci_data *pci_priv, + enum cnss_driver_status status); + +#endif /* _CNSS_PCI_H */ diff --git a/drivers/net/wireless/cnss2/power.c b/drivers/net/wireless/cnss2/power.c new file mode 100644 index 000000000000..a224d075e10d --- /dev/null +++ b/drivers/net/wireless/cnss2/power.c @@ -0,0 +1,957 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include + +#include "main.h" +#include "debug.h" + +static struct cnss_vreg_cfg cnss_vreg_list[] = { + {"vdd-wlan-core", 1300000, 1300000, 0, 0, 0}, + {"vdd-wlan-io", 1800000, 1800000, 0, 0, 0}, + {"vdd-wlan-xtal-aon", 0, 0, 0, 0, 0}, + {"vdd-wlan-xtal", 1800000, 1800000, 0, 2, 0}, + {"vdd-wlan", 0, 0, 0, 0, 0}, + {"vdd-wlan-ctrl1", 0, 0, 0, 0, 0}, + {"vdd-wlan-ctrl2", 0, 0, 0, 0, 0}, + {"vdd-wlan-sp2t", 2700000, 2700000, 0, 0, 0}, + {"wlan-ant-switch", 1800000, 1800000, 0, 0, 0}, + {"wlan-soc-swreg", 1200000, 1200000, 0, 0, 0}, + {"vdd-wlan-aon", 950000, 950000, 0, 0, 0}, + {"vdd-wlan-dig", 950000, 952000, 0, 0, 0}, + {"vdd-wlan-rfa1", 1900000, 1900000, 0, 0, 0}, + {"vdd-wlan-rfa2", 1350000, 1350000, 0, 0, 0}, + {"vdd-wlan-en", 0, 0, 0, 10, 0}, +}; + +static struct cnss_clk_cfg cnss_clk_list[] = { + {"rf_clk", 0, 0}, +}; + +#define CNSS_VREG_INFO_SIZE ARRAY_SIZE(cnss_vreg_list) +#define CNSS_CLK_INFO_SIZE ARRAY_SIZE(cnss_clk_list) +#define MAX_PROP_SIZE 32 + +#define BOOTSTRAP_GPIO "qcom,enable-bootstrap-gpio" +#define BOOTSTRAP_ACTIVE "bootstrap_active" +#define WLAN_EN_GPIO "wlan-en-gpio" +#define WLAN_EN_ACTIVE "wlan_en_active" +#define WLAN_EN_SLEEP "wlan_en_sleep" + +#define BOOTSTRAP_DELAY 1000 +#define WLAN_ENABLE_DELAY 1000 + +#define TCS_CMD_DATA_ADDR_OFFSET 0x4 +#define TCS_OFFSET 0xC8 +#define TCS_CMD_OFFSET 0x10 +#define MAX_TCS_NUM 8 +#define MAX_TCS_CMD_NUM 5 +#define BT_CXMX_VOLTAGE_MV 950 + +static int cnss_get_vreg_single(struct cnss_plat_data *plat_priv, + struct cnss_vreg_info *vreg) +{ + int ret = 0; + struct device *dev; + struct regulator *reg; + const __be32 *prop; + char prop_name[MAX_PROP_SIZE] = {0}; + int len; + + dev = &plat_priv->plat_dev->dev; + reg = devm_regulator_get_optional(dev, vreg->cfg.name); + if (IS_ERR(reg)) { + ret = PTR_ERR(reg); + if (ret == -ENODEV) + return ret; + else if (ret == -EPROBE_DEFER) + cnss_pr_info("EPROBE_DEFER for regulator: %s\n", + vreg->cfg.name); + else + cnss_pr_err("Failed to get regulator %s, err = %d\n", + vreg->cfg.name, ret); + return ret; + } + + vreg->reg = reg; + + snprintf(prop_name, MAX_PROP_SIZE, "qcom,%s-config", + vreg->cfg.name); + + prop = of_get_property(dev->of_node, prop_name, &len); + if (!prop || len != (5 * sizeof(__be32))) { + cnss_pr_dbg("Property %s %s, use default\n", prop_name, + prop ? "invalid format" : "doesn't exist"); + } else { + vreg->cfg.min_uv = be32_to_cpup(&prop[0]); + vreg->cfg.max_uv = be32_to_cpup(&prop[1]); + vreg->cfg.load_ua = be32_to_cpup(&prop[2]); + vreg->cfg.delay_us = be32_to_cpup(&prop[3]); + vreg->cfg.need_unvote = be32_to_cpup(&prop[4]); + } + + cnss_pr_dbg("Got regulator: %s, min_uv: %u, max_uv: %u, load_ua: %u, delay_us: %u, need_unvote: %u\n", + vreg->cfg.name, vreg->cfg.min_uv, + vreg->cfg.max_uv, vreg->cfg.load_ua, + vreg->cfg.delay_us, vreg->cfg.need_unvote); + + return 0; +} + +static void cnss_put_vreg_single(struct cnss_plat_data *plat_priv, + struct cnss_vreg_info *vreg) +{ + struct device *dev = &plat_priv->plat_dev->dev; + + cnss_pr_dbg("Put regulator: %s\n", vreg->cfg.name); + devm_regulator_put(vreg->reg); + devm_kfree(dev, vreg); +} + +static int cnss_vreg_on_single(struct cnss_vreg_info *vreg) +{ + int ret = 0; + + if (vreg->enabled) { + cnss_pr_dbg("Regulator %s is already enabled\n", + vreg->cfg.name); + return 0; + } + + cnss_pr_dbg("Regulator %s is being enabled\n", vreg->cfg.name); + + if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) { + ret = regulator_set_voltage(vreg->reg, + vreg->cfg.min_uv, + vreg->cfg.max_uv); + + if (ret) { + cnss_pr_err("Failed to set voltage for regulator %s, min_uv: %u, max_uv: %u, err = %d\n", + vreg->cfg.name, vreg->cfg.min_uv, + vreg->cfg.max_uv, ret); + goto out; + } + } + + if (vreg->cfg.load_ua) { + ret = regulator_set_load(vreg->reg, + vreg->cfg.load_ua); + + if (ret < 0) { + cnss_pr_err("Failed to set load for regulator %s, load: %u, err = %d\n", + vreg->cfg.name, vreg->cfg.load_ua, + ret); + goto out; + } + } + + if (vreg->cfg.delay_us) + udelay(vreg->cfg.delay_us); + + ret = regulator_enable(vreg->reg); + if (ret) { + cnss_pr_err("Failed to enable regulator %s, err = %d\n", + vreg->cfg.name, ret); + goto out; + } + vreg->enabled = true; + +out: + return ret; +} + +static int cnss_vreg_unvote_single(struct cnss_vreg_info *vreg) +{ + int ret = 0; + + if (!vreg->enabled) { + cnss_pr_dbg("Regulator %s is already disabled\n", + vreg->cfg.name); + return 0; + } + + cnss_pr_dbg("Removing vote for Regulator %s\n", vreg->cfg.name); + + if (vreg->cfg.load_ua) { + ret = regulator_set_load(vreg->reg, 0); + if (ret < 0) + cnss_pr_err("Failed to set load for regulator %s, err = %d\n", + vreg->cfg.name, ret); + } + + if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) { + ret = regulator_set_voltage(vreg->reg, 0, + vreg->cfg.max_uv); + if (ret) + cnss_pr_err("Failed to set voltage for regulator %s, err = %d\n", + vreg->cfg.name, ret); + } + + return ret; +} + +static int cnss_vreg_off_single(struct cnss_vreg_info *vreg) +{ + int ret = 0; + + if (!vreg->enabled) { + cnss_pr_dbg("Regulator %s is already disabled\n", + vreg->cfg.name); + return 0; + } + + cnss_pr_dbg("Regulator %s is being disabled\n", + vreg->cfg.name); + + ret = regulator_disable(vreg->reg); + if (ret) + cnss_pr_err("Failed to disable regulator %s, err = %d\n", + vreg->cfg.name, ret); + + if (vreg->cfg.load_ua) { + ret = regulator_set_load(vreg->reg, 0); + if (ret < 0) + cnss_pr_err("Failed to set load for regulator %s, err = %d\n", + vreg->cfg.name, ret); + } + + if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) { + ret = regulator_set_voltage(vreg->reg, 0, + vreg->cfg.max_uv); + if (ret) + cnss_pr_err("Failed to set voltage for regulator %s, err = %d\n", + vreg->cfg.name, ret); + } + vreg->enabled = false; + + return ret; +} + +static struct cnss_vreg_cfg *get_vreg_list(u32 *vreg_list_size, + enum cnss_vreg_type type) +{ + switch (type) { + case CNSS_VREG_PRIM: + *vreg_list_size = CNSS_VREG_INFO_SIZE; + return cnss_vreg_list; + default: + cnss_pr_err("Unsupported vreg type 0x%x\n", type); + *vreg_list_size = 0; + return NULL; + } +} + +static int cnss_get_vreg(struct cnss_plat_data *plat_priv, + struct list_head *vreg_list, + struct cnss_vreg_cfg *vreg_cfg, + u32 vreg_list_size) +{ + int ret = 0; + int i; + struct cnss_vreg_info *vreg; + struct device *dev = &plat_priv->plat_dev->dev; + + if (!list_empty(vreg_list)) { + cnss_pr_dbg("Vregs have already been updated\n"); + return 0; + } + + for (i = 0; i < vreg_list_size; i++) { + vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); + if (!vreg) + return -ENOMEM; + + memcpy(&vreg->cfg, &vreg_cfg[i], sizeof(vreg->cfg)); + ret = cnss_get_vreg_single(plat_priv, vreg); + if (ret != 0) { + if (ret == -ENODEV) { + devm_kfree(dev, vreg); + continue; + } else { + devm_kfree(dev, vreg); + return ret; + } + } + list_add_tail(&vreg->list, vreg_list); + } + + return 0; +} + +static void cnss_put_vreg(struct cnss_plat_data *plat_priv, + struct list_head *vreg_list) +{ + struct cnss_vreg_info *vreg; + + while (!list_empty(vreg_list)) { + vreg = list_first_entry(vreg_list, + struct cnss_vreg_info, list); + list_del(&vreg->list); + if (IS_ERR_OR_NULL(vreg->reg)) + continue; + cnss_put_vreg_single(plat_priv, vreg); + } +} + +static int cnss_vreg_on(struct cnss_plat_data *plat_priv, + struct list_head *vreg_list) +{ + struct cnss_vreg_info *vreg; + int ret = 0; + + list_for_each_entry(vreg, vreg_list, list) { + if (IS_ERR_OR_NULL(vreg->reg)) + continue; + ret = cnss_vreg_on_single(vreg); + if (ret) + break; + } + + if (!ret) + return 0; + + list_for_each_entry_continue_reverse(vreg, vreg_list, list) { + if (IS_ERR_OR_NULL(vreg->reg) || !vreg->enabled) + continue; + + cnss_vreg_off_single(vreg); + } + + return ret; +} + +static int cnss_vreg_off(struct cnss_plat_data *plat_priv, + struct list_head *vreg_list) +{ + struct cnss_vreg_info *vreg; + + list_for_each_entry_reverse(vreg, vreg_list, list) { + if (IS_ERR_OR_NULL(vreg->reg)) + continue; + + cnss_vreg_off_single(vreg); + } + + return 0; +} + +static int cnss_vreg_unvote(struct cnss_plat_data *plat_priv, + struct list_head *vreg_list) +{ + struct cnss_vreg_info *vreg; + + list_for_each_entry_reverse(vreg, vreg_list, list) { + if (IS_ERR_OR_NULL(vreg->reg)) + continue; + + if (vreg->cfg.need_unvote) + cnss_vreg_unvote_single(vreg); + } + + return 0; +} + +int cnss_get_vreg_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type) +{ + struct cnss_vreg_cfg *vreg_cfg; + u32 vreg_list_size = 0; + int ret = 0; + + vreg_cfg = get_vreg_list(&vreg_list_size, type); + if (!vreg_cfg) + return -EINVAL; + + switch (type) { + case CNSS_VREG_PRIM: + ret = cnss_get_vreg(plat_priv, &plat_priv->vreg_list, + vreg_cfg, vreg_list_size); + break; + default: + cnss_pr_err("Unsupported vreg type 0x%x\n", type); + return -EINVAL; + } + + return ret; +} + +void cnss_put_vreg_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type) +{ + switch (type) { + case CNSS_VREG_PRIM: + cnss_put_vreg(plat_priv, &plat_priv->vreg_list); + break; + default: + return; + } +} + +int cnss_vreg_on_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type) +{ + int ret = 0; + + switch (type) { + case CNSS_VREG_PRIM: + ret = cnss_vreg_on(plat_priv, &plat_priv->vreg_list); + break; + default: + cnss_pr_err("Unsupported vreg type 0x%x\n", type); + return -EINVAL; + } + + return ret; +} + +int cnss_vreg_off_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type) +{ + int ret = 0; + + switch (type) { + case CNSS_VREG_PRIM: + ret = cnss_vreg_off(plat_priv, &plat_priv->vreg_list); + break; + default: + cnss_pr_err("Unsupported vreg type 0x%x\n", type); + return -EINVAL; + } + + return ret; +} + +int cnss_vreg_unvote_type(struct cnss_plat_data *plat_priv, + enum cnss_vreg_type type) +{ + int ret = 0; + + switch (type) { + case CNSS_VREG_PRIM: + ret = cnss_vreg_unvote(plat_priv, &plat_priv->vreg_list); + break; + default: + cnss_pr_err("Unsupported vreg type 0x%x\n", type); + return -EINVAL; + } + + return ret; +} + +static int cnss_get_clk_single(struct cnss_plat_data *plat_priv, + struct cnss_clk_info *clk_info) +{ + struct device *dev = &plat_priv->plat_dev->dev; + struct clk *clk; + int ret; + + clk = devm_clk_get(dev, clk_info->cfg.name); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + if (clk_info->cfg.required) + cnss_pr_err("Failed to get clock %s, err = %d\n", + clk_info->cfg.name, ret); + else + cnss_pr_dbg("Failed to get optional clock %s, err = %d\n", + clk_info->cfg.name, ret); + return ret; + } + + clk_info->clk = clk; + cnss_pr_dbg("Got clock: %s, freq: %u\n", + clk_info->cfg.name, clk_info->cfg.freq); + + return 0; +} + +static void cnss_put_clk_single(struct cnss_plat_data *plat_priv, + struct cnss_clk_info *clk_info) +{ + struct device *dev = &plat_priv->plat_dev->dev; + + cnss_pr_dbg("Put clock: %s\n", clk_info->cfg.name); + devm_clk_put(dev, clk_info->clk); +} + +static int cnss_clk_on_single(struct cnss_clk_info *clk_info) +{ + int ret; + + if (clk_info->enabled) { + cnss_pr_dbg("Clock %s is already enabled\n", + clk_info->cfg.name); + return 0; + } + + cnss_pr_dbg("Clock %s is being enabled\n", clk_info->cfg.name); + + if (clk_info->cfg.freq) { + ret = clk_set_rate(clk_info->clk, clk_info->cfg.freq); + if (ret) { + cnss_pr_err("Failed to set frequency %u for clock %s, err = %d\n", + clk_info->cfg.freq, clk_info->cfg.name, + ret); + return ret; + } + } + + ret = clk_prepare_enable(clk_info->clk); + if (ret) { + cnss_pr_err("Failed to enable clock %s, err = %d\n", + clk_info->cfg.name, ret); + return ret; + } + + clk_info->enabled = true; + + return 0; +} + +static int cnss_clk_off_single(struct cnss_clk_info *clk_info) +{ + if (!clk_info->enabled) { + cnss_pr_dbg("Clock %s is already disabled\n", + clk_info->cfg.name); + return 0; + } + + cnss_pr_dbg("Clock %s is being disabled\n", clk_info->cfg.name); + + clk_disable_unprepare(clk_info->clk); + clk_info->enabled = false; + + return 0; +} + +int cnss_get_clk(struct cnss_plat_data *plat_priv) +{ + struct device *dev; + struct list_head *clk_list; + struct cnss_clk_info *clk_info; + int ret, i; + + if (!plat_priv) + return -ENODEV; + + dev = &plat_priv->plat_dev->dev; + clk_list = &plat_priv->clk_list; + + if (!list_empty(clk_list)) { + cnss_pr_dbg("Clocks have already been updated\n"); + return 0; + } + + for (i = 0; i < CNSS_CLK_INFO_SIZE; i++) { + clk_info = devm_kzalloc(dev, sizeof(*clk_info), GFP_KERNEL); + if (!clk_info) { + ret = -ENOMEM; + goto cleanup; + } + + memcpy(&clk_info->cfg, &cnss_clk_list[i], + sizeof(clk_info->cfg)); + ret = cnss_get_clk_single(plat_priv, clk_info); + if (ret != 0) { + if (clk_info->cfg.required) { + devm_kfree(dev, clk_info); + goto cleanup; + } else { + devm_kfree(dev, clk_info); + continue; + } + } + list_add_tail(&clk_info->list, clk_list); + } + + return 0; + +cleanup: + while (!list_empty(clk_list)) { + clk_info = list_first_entry(clk_list, struct cnss_clk_info, + list); + list_del(&clk_info->list); + if (IS_ERR_OR_NULL(clk_info->clk)) + continue; + cnss_put_clk_single(plat_priv, clk_info); + devm_kfree(dev, clk_info); + } + + return ret; +} + +void cnss_put_clk(struct cnss_plat_data *plat_priv) +{ + struct device *dev; + struct list_head *clk_list; + struct cnss_clk_info *clk_info; + + if (!plat_priv) + return; + + dev = &plat_priv->plat_dev->dev; + clk_list = &plat_priv->clk_list; + + while (!list_empty(clk_list)) { + clk_info = list_first_entry(clk_list, struct cnss_clk_info, + list); + list_del(&clk_info->list); + if (IS_ERR_OR_NULL(clk_info->clk)) + continue; + cnss_put_clk_single(plat_priv, clk_info); + devm_kfree(dev, clk_info); + } +} + +static int cnss_clk_on(struct cnss_plat_data *plat_priv, + struct list_head *clk_list) +{ + struct cnss_clk_info *clk_info; + int ret = 0; + + list_for_each_entry(clk_info, clk_list, list) { + if (IS_ERR_OR_NULL(clk_info->clk)) + continue; + ret = cnss_clk_on_single(clk_info); + if (ret) + break; + } + + if (!ret) + return 0; + + list_for_each_entry_continue_reverse(clk_info, clk_list, list) { + if (IS_ERR_OR_NULL(clk_info->clk)) + continue; + + cnss_clk_off_single(clk_info); + } + + return ret; +} + +static int cnss_clk_off(struct cnss_plat_data *plat_priv, + struct list_head *clk_list) +{ + struct cnss_clk_info *clk_info; + + list_for_each_entry_reverse(clk_info, clk_list, list) { + if (IS_ERR_OR_NULL(clk_info->clk)) + continue; + + cnss_clk_off_single(clk_info); + } + + return 0; +} + +int cnss_get_pinctrl(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + struct device *dev; + struct cnss_pinctrl_info *pinctrl_info; + + dev = &plat_priv->plat_dev->dev; + pinctrl_info = &plat_priv->pinctrl_info; + + pinctrl_info->pinctrl = devm_pinctrl_get(dev); + if (IS_ERR_OR_NULL(pinctrl_info->pinctrl)) { + ret = PTR_ERR(pinctrl_info->pinctrl); + cnss_pr_err("Failed to get pinctrl, err = %d\n", ret); + goto out; + } + + if (of_find_property(dev->of_node, BOOTSTRAP_GPIO, NULL)) { + pinctrl_info->bootstrap_active = + pinctrl_lookup_state(pinctrl_info->pinctrl, + BOOTSTRAP_ACTIVE); + if (IS_ERR_OR_NULL(pinctrl_info->bootstrap_active)) { + ret = PTR_ERR(pinctrl_info->bootstrap_active); + cnss_pr_err("Failed to get bootstrap active state, err = %d\n", + ret); + goto out; + } + } + + if (of_find_property(dev->of_node, WLAN_EN_GPIO, NULL)) { + pinctrl_info->wlan_en_active = + pinctrl_lookup_state(pinctrl_info->pinctrl, + WLAN_EN_ACTIVE); + if (IS_ERR_OR_NULL(pinctrl_info->wlan_en_active)) { + ret = PTR_ERR(pinctrl_info->wlan_en_active); + cnss_pr_err("Failed to get wlan_en active state, err = %d\n", + ret); + goto out; + } + + pinctrl_info->wlan_en_sleep = + pinctrl_lookup_state(pinctrl_info->pinctrl, + WLAN_EN_SLEEP); + if (IS_ERR_OR_NULL(pinctrl_info->wlan_en_sleep)) { + ret = PTR_ERR(pinctrl_info->wlan_en_sleep); + cnss_pr_err("Failed to get wlan_en sleep state, err = %d\n", + ret); + goto out; + } + } + + return 0; +out: + return ret; +} + +static int cnss_select_pinctrl_state(struct cnss_plat_data *plat_priv, + bool state) +{ + int ret = 0; + struct cnss_pinctrl_info *pinctrl_info; + + if (!plat_priv) { + cnss_pr_err("plat_priv is NULL!\n"); + ret = -ENODEV; + goto out; + } + + pinctrl_info = &plat_priv->pinctrl_info; + + if (state) { + if (!IS_ERR_OR_NULL(pinctrl_info->bootstrap_active)) { + ret = pinctrl_select_state + (pinctrl_info->pinctrl, + pinctrl_info->bootstrap_active); + if (ret) { + cnss_pr_err("Failed to select bootstrap active state, err = %d\n", + ret); + goto out; + } + udelay(BOOTSTRAP_DELAY); + } + + if (!IS_ERR_OR_NULL(pinctrl_info->wlan_en_active)) { + ret = pinctrl_select_state + (pinctrl_info->pinctrl, + pinctrl_info->wlan_en_active); + if (ret) { + cnss_pr_err("Failed to select wlan_en active state, err = %d\n", + ret); + goto out; + } + udelay(WLAN_ENABLE_DELAY); + } + } else { + if (!IS_ERR_OR_NULL(pinctrl_info->wlan_en_sleep)) { + ret = pinctrl_select_state(pinctrl_info->pinctrl, + pinctrl_info->wlan_en_sleep); + if (ret) { + cnss_pr_err("Failed to select wlan_en sleep state, err = %d\n", + ret); + goto out; + } + } + } + + return 0; +out: + return ret; +} + +int cnss_power_on_device(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + if (plat_priv->powered_on) { + cnss_pr_dbg("Already powered up"); + return 0; + } + + ret = cnss_vreg_on_type(plat_priv, CNSS_VREG_PRIM); + if (ret) { + cnss_pr_err("Failed to turn on vreg, err = %d\n", ret); + goto out; + } + + ret = cnss_clk_on(plat_priv, &plat_priv->clk_list); + if (ret) { + cnss_pr_err("Failed to turn on clocks, err = %d\n", ret); + goto vreg_off; + } + + ret = cnss_select_pinctrl_state(plat_priv, true); + if (ret) { + cnss_pr_err("Failed to select pinctrl state, err = %d\n", ret); + goto clk_off; + } + + plat_priv->powered_on = true; + + return 0; + +clk_off: + cnss_clk_off(plat_priv, &plat_priv->clk_list); +vreg_off: + cnss_vreg_off_type(plat_priv, CNSS_VREG_PRIM); +out: + return ret; +} + +void cnss_power_off_device(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv->powered_on) { + cnss_pr_dbg("Already powered down"); + return; + } + + cnss_select_pinctrl_state(plat_priv, false); + cnss_clk_off(plat_priv, &plat_priv->clk_list); + cnss_vreg_off_type(plat_priv, CNSS_VREG_PRIM); + plat_priv->powered_on = false; +} + +bool cnss_is_device_powered_on(struct cnss_plat_data *plat_priv) +{ + return plat_priv->powered_on; +} + +void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv) +{ + unsigned long pin_status = 0; + + set_bit(CNSS_WLAN_EN, &pin_status); + set_bit(CNSS_PCIE_TXN, &pin_status); + set_bit(CNSS_PCIE_TXP, &pin_status); + set_bit(CNSS_PCIE_RXN, &pin_status); + set_bit(CNSS_PCIE_RXP, &pin_status); + set_bit(CNSS_PCIE_REFCLKN, &pin_status); + set_bit(CNSS_PCIE_REFCLKP, &pin_status); + set_bit(CNSS_PCIE_RST, &pin_status); + + plat_priv->pin_result.host_pin_result = pin_status; +} + +int cnss_get_cpr_info(struct cnss_plat_data *plat_priv) +{ + struct platform_device *plat_dev = plat_priv->plat_dev; + struct cnss_cpr_info *cpr_info = &plat_priv->cpr_info; + struct resource *res; + resource_size_t addr_len; + void __iomem *tcs_cmd_base_addr; + const char *cmd_db_name; + u32 cpr_pmic_addr = 0; + int ret = 0; + + res = platform_get_resource_byname(plat_dev, IORESOURCE_MEM, "tcs_cmd"); + if (!res) { + cnss_pr_dbg("TCS CMD address is not present for CPR\n"); + goto out; + } + + ret = of_property_read_string(plat_dev->dev.of_node, + "qcom,cmd_db_name", &cmd_db_name); + if (ret) { + cnss_pr_dbg("CommandDB name is not present for CPR\n"); + goto out; + } + + ret = cmd_db_ready(); + if (ret) { + cnss_pr_err("CommandDB is not ready\n"); + goto out; + } + + cpr_pmic_addr = cmd_db_read_addr(cmd_db_name); + if (cpr_pmic_addr > 0) { + cpr_info->cpr_pmic_addr = cpr_pmic_addr; + cnss_pr_dbg("Get CPR PMIC address 0x%x from %s\n", + cpr_info->cpr_pmic_addr, cmd_db_name); + } else { + cnss_pr_err("CPR PMIC address is not available for %s\n", + cmd_db_name); + ret = -EINVAL; + goto out; + } + + cpr_info->tcs_cmd_base_addr = res->start; + addr_len = resource_size(res); + cnss_pr_dbg("TCS CMD base address is %pa with length %pa\n", + &cpr_info->tcs_cmd_base_addr, &addr_len); + + tcs_cmd_base_addr = devm_ioremap_resource(&plat_dev->dev, res); + if (IS_ERR(tcs_cmd_base_addr)) { + ret = PTR_ERR(tcs_cmd_base_addr); + cnss_pr_err("Failed to map TCS CMD address, err = %d\n", + ret); + goto out; + } + + cpr_info->tcs_cmd_base_addr_io = tcs_cmd_base_addr; + + return 0; + +out: + return ret; +} + +int cnss_update_cpr_info(struct cnss_plat_data *plat_priv) +{ + struct cnss_cpr_info *cpr_info = &plat_priv->cpr_info; + u32 pmic_addr, voltage = 0, voltage_tmp, offset; + void __iomem *tcs_cmd_addr, *tcs_cmd_data_addr; + int i, j; + + if (cpr_info->tcs_cmd_base_addr == 0) { + cnss_pr_dbg("CPR is not enabled\n"); + return 0; + } + + if (cpr_info->voltage == 0 || cpr_info->cpr_pmic_addr == 0) { + cnss_pr_err("Voltage %dmV or PMIC address 0x%x is not valid\n", + cpr_info->voltage, cpr_info->cpr_pmic_addr); + return -EINVAL; + } + + if (cpr_info->tcs_cmd_data_addr_io) + goto update_cpr; + + for (i = 0; i < MAX_TCS_NUM; i++) { + for (j = 0; j < MAX_TCS_CMD_NUM; j++) { + offset = i * TCS_OFFSET + j * TCS_CMD_OFFSET; + tcs_cmd_addr = cpr_info->tcs_cmd_base_addr_io + offset; + pmic_addr = readl_relaxed(tcs_cmd_addr); + if (pmic_addr == cpr_info->cpr_pmic_addr) { + tcs_cmd_data_addr = tcs_cmd_addr + + TCS_CMD_DATA_ADDR_OFFSET; + voltage_tmp = readl_relaxed(tcs_cmd_data_addr); + cnss_pr_dbg("Got voltage %dmV from i: %d, j: %d\n", + voltage_tmp, i, j); + + if (voltage_tmp > voltage) { + voltage = voltage_tmp; + cpr_info->tcs_cmd_data_addr = + cpr_info->tcs_cmd_base_addr + + offset + + TCS_CMD_DATA_ADDR_OFFSET; + cpr_info->tcs_cmd_data_addr_io = + tcs_cmd_data_addr; + } + } + } + } + + if (!cpr_info->tcs_cmd_data_addr_io) { + cnss_pr_err("Failed to find proper TCS CMD data address\n"); + return -EINVAL; + } + +update_cpr: + cpr_info->voltage = cpr_info->voltage > BT_CXMX_VOLTAGE_MV ? + cpr_info->voltage : BT_CXMX_VOLTAGE_MV; + cnss_pr_dbg("Update TCS CMD data address %pa with voltage %dmV\n", + &cpr_info->tcs_cmd_data_addr, cpr_info->voltage); + writel_relaxed(cpr_info->voltage, cpr_info->tcs_cmd_data_addr_io); + + return 0; +} diff --git a/drivers/net/wireless/cnss2/qmi.c b/drivers/net/wireless/cnss2/qmi.c new file mode 100644 index 000000000000..89e12659d9ad --- /dev/null +++ b/drivers/net/wireless/cnss2/qmi.c @@ -0,0 +1,2299 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. */ + +#include +#include +#include + +#include "bus.h" +#include "debug.h" +#include "main.h" +#include "qmi.h" + +#define WLFW_SERVICE_INS_ID_V01 1 +#define WLFW_CLIENT_ID 0x4b4e454c +#define MAX_BDF_FILE_NAME 13 +#define BDF_FILE_NAME_PREFIX "bdwlan" +#define ELF_BDF_FILE_NAME "bdwlan.elf" +#define ELF_BDF_FILE_NAME_PREFIX "bdwlan.e" +#define BIN_BDF_FILE_NAME "bdwlan.bin" +#define BIN_BDF_FILE_NAME_PREFIX "bdwlan.b" +#define REGDB_FILE_NAME "regdb.bin" +#define DUMMY_BDF_FILE_NAME "bdwlan.dmy" + +#define QMI_WLFW_TIMEOUT_MS (plat_priv->ctrl_params.qmi_timeout) +#define QMI_WLFW_TIMEOUT_JF msecs_to_jiffies(QMI_WLFW_TIMEOUT_MS) +#define COEX_TIMEOUT QMI_WLFW_TIMEOUT_JF +#define IMS_TIMEOUT QMI_WLFW_TIMEOUT_JF + +#define QMI_WLFW_MAX_RECV_BUF_SIZE SZ_8K + +static char *cnss_qmi_mode_to_str(enum cnss_driver_mode mode) +{ + switch (mode) { + case CNSS_MISSION: + return "MISSION"; + case CNSS_FTM: + return "FTM"; + case CNSS_EPPING: + return "EPPING"; + case CNSS_WALTEST: + return "WALTEST"; + case CNSS_OFF: + return "OFF"; + case CNSS_CCPM: + return "CCPM"; + case CNSS_QVIT: + return "QVIT"; + case CNSS_CALIBRATION: + return "CALIBRATION"; + default: + return "UNKNOWN"; + } +}; + +static int cnss_wlfw_ind_register_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_ind_register_req_msg_v01 *req; + struct wlfw_ind_register_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + cnss_pr_dbg("Sending indication register message, state: 0x%lx\n", + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->client_id_valid = 1; + req->client_id = WLFW_CLIENT_ID; + req->fw_ready_enable_valid = 1; + req->fw_ready_enable = 1; + req->request_mem_enable_valid = 1; + req->request_mem_enable = 1; + req->fw_mem_ready_enable_valid = 1; + req->fw_mem_ready_enable = 1; + req->fw_init_done_enable_valid = 1; + req->fw_init_done_enable = 1; + req->pin_connect_result_enable_valid = 1; + req->pin_connect_result_enable = 1; + req->cal_done_enable_valid = 1; + req->cal_done_enable = 1; + req->qdss_trace_req_mem_enable_valid = 1; + req->qdss_trace_req_mem_enable = 1; + req->qdss_trace_save_enable_valid = 1; + req->qdss_trace_save_enable = 1; + req->qdss_trace_free_enable_valid = 1; + req->qdss_trace_free_enable = 1; + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_ind_register_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for indication register request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_IND_REGISTER_REQ_V01, + WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_ind_register_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send indication register request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of indication register request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Indication register request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + if (resp->fw_status_valid) { + if (resp->fw_status & QMI_WLFW_ALREADY_REGISTERED_V01) { + ret = -EALREADY; + goto qmi_registered; + } + } + + kfree(req); + kfree(resp); + return 0; + +out: + CNSS_ASSERT(0); + +qmi_registered: + kfree(req); + kfree(resp); + return ret; +} + +static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_host_cap_req_msg_v01 *req; + struct wlfw_host_cap_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + cnss_pr_dbg("Sending host capability message, state: 0x%lx\n", + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->num_clients_valid = 1; + if (test_bit(ENABLE_DAEMON_SUPPORT, + &plat_priv->ctrl_params.quirks)) + req->num_clients = 2; + else + req->num_clients = 1; + cnss_pr_dbg("Number of clients is %d\n", req->num_clients); + + req->wake_msi = cnss_bus_get_wake_irq(plat_priv); + if (req->wake_msi) { + cnss_pr_dbg("WAKE MSI base data is %d\n", req->wake_msi); + req->wake_msi_valid = 1; + } + + req->bdf_support_valid = 1; + req->bdf_support = 1; + + req->m3_support_valid = 1; + req->m3_support = 1; + + req->m3_cache_support_valid = 1; + req->m3_cache_support = 1; + + req->cal_done_valid = 1; + req->cal_done = plat_priv->cal_done; + cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done); + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_host_cap_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for host capability request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_HOST_CAP_REQ_V01, + WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_host_cap_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send host capability request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of host capability request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Host capability request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + CNSS_ASSERT(0); + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_respond_mem_req_msg_v01 *req; + struct wlfw_respond_mem_resp_msg_v01 *resp; + struct qmi_txn txn; + struct cnss_fw_mem *fw_mem = plat_priv->fw_mem; + int ret = 0, i; + + cnss_pr_dbg("Sending respond memory message, state: 0x%lx\n", + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->mem_seg_len = plat_priv->fw_mem_seg_len; + for (i = 0; i < req->mem_seg_len; i++) { + if (!fw_mem[i].pa || !fw_mem[i].size) { + if (fw_mem[i].type == 0) { + cnss_pr_err("Invalid memory for FW type, segment = %d\n", + i); + ret = -EINVAL; + goto out; + } + cnss_pr_err("Memory for FW is not available for type: %u\n", + fw_mem[i].type); + ret = -ENOMEM; + goto out; + } + + cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n", + fw_mem[i].va, &fw_mem[i].pa, + fw_mem[i].size, fw_mem[i].type); + + req->mem_seg[i].addr = fw_mem[i].pa; + req->mem_seg[i].size = fw_mem[i].size; + req->mem_seg[i].type = fw_mem[i].type; + } + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_respond_mem_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for respond memory request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_RESPOND_MEM_REQ_V01, + WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_respond_mem_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send respond memory request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of respond memory request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Respond memory request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + CNSS_ASSERT(0); + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_cap_req_msg_v01 *req; + struct wlfw_cap_resp_msg_v01 *resp; + struct qmi_txn txn; + char *fw_build_timestamp; + int ret = 0; + + cnss_pr_dbg("Sending target capability message, state: 0x%lx\n", + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_cap_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for target capability request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_CAP_REQ_V01, + WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_cap_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send respond target capability request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of target capability request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Target capability request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + if (resp->chip_info_valid) { + plat_priv->chip_info.chip_id = resp->chip_info.chip_id; + plat_priv->chip_info.chip_family = resp->chip_info.chip_family; + } + if (resp->board_info_valid) + plat_priv->board_info.board_id = resp->board_info.board_id; + else + plat_priv->board_info.board_id = 0xFF; + if (resp->soc_info_valid) + plat_priv->soc_info.soc_id = resp->soc_info.soc_id; + if (resp->fw_version_info_valid) { + plat_priv->fw_version_info.fw_version = + resp->fw_version_info.fw_version; + fw_build_timestamp = resp->fw_version_info.fw_build_timestamp; + fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN] = '\0'; + strlcpy(plat_priv->fw_version_info.fw_build_timestamp, + resp->fw_version_info.fw_build_timestamp, + QMI_WLFW_MAX_TIMESTAMP_LEN + 1); + } + if (resp->voltage_mv_valid) { + plat_priv->cpr_info.voltage = resp->voltage_mv; + cnss_pr_dbg("Voltage for CPR: %dmV\n", + plat_priv->cpr_info.voltage); + cnss_update_cpr_info(plat_priv); + } + if (resp->time_freq_hz_valid) { + plat_priv->device_freq_hz = resp->time_freq_hz; + cnss_pr_dbg("Device frequency is %d HZ\n", + plat_priv->device_freq_hz); + } + if (resp->otp_version_valid) + plat_priv->otp_version = resp->otp_version; + + cnss_pr_dbg("Target capability: chip_id: 0x%x, chip_family: 0x%x, board_id: 0x%x, soc_id: 0x%x, fw_version: 0x%x, fw_build_timestamp: %s, otp_version: 0x%x\n", + plat_priv->chip_info.chip_id, + plat_priv->chip_info.chip_family, + plat_priv->board_info.board_id, plat_priv->soc_info.soc_id, + plat_priv->fw_version_info.fw_version, + plat_priv->fw_version_info.fw_build_timestamp, + plat_priv->otp_version); + + kfree(req); + kfree(resp); + return 0; + +out: + CNSS_ASSERT(0); + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv, + u32 bdf_type) +{ + struct wlfw_bdf_download_req_msg_v01 *req; + struct wlfw_bdf_download_resp_msg_v01 *resp; + struct qmi_txn txn; + char filename[MAX_BDF_FILE_NAME]; + const struct firmware *fw_entry; + const u8 *temp; + unsigned int remaining; + int ret = 0; + + cnss_pr_dbg("Sending BDF download message, state: 0x%lx, type: %d\n", + plat_priv->driver_state, bdf_type); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + switch (bdf_type) { + case CNSS_BDF_ELF: + if (plat_priv->board_info.board_id == 0xFF) + snprintf(filename, sizeof(filename), ELF_BDF_FILE_NAME); + else if (plat_priv->board_info.board_id < 0xFF) + snprintf(filename, sizeof(filename), + ELF_BDF_FILE_NAME_PREFIX "%02x", + plat_priv->board_info.board_id); + else + snprintf(filename, sizeof(filename), + BDF_FILE_NAME_PREFIX "%02x.e%02x", + plat_priv->board_info.board_id >> 8 & 0xFF, + plat_priv->board_info.board_id & 0xFF); + break; + case CNSS_BDF_BIN: + if (plat_priv->board_info.board_id == 0xFF) + snprintf(filename, sizeof(filename), BIN_BDF_FILE_NAME); + else if (plat_priv->board_info.board_id < 0xFF) + snprintf(filename, sizeof(filename), + BIN_BDF_FILE_NAME_PREFIX "%02x", + plat_priv->board_info.board_id); + else + snprintf(filename, sizeof(filename), + BDF_FILE_NAME_PREFIX "%02x.b%02x", + plat_priv->board_info.board_id >> 8 & 0xFF, + plat_priv->board_info.board_id & 0xFF); + break; + case CNSS_BDF_REGDB: + snprintf(filename, sizeof(filename), REGDB_FILE_NAME); + break; + case CNSS_BDF_DUMMY: + cnss_pr_dbg("CNSS_BDF_DUMMY is set, sending dummy BDF\n"); + snprintf(filename, sizeof(filename), DUMMY_BDF_FILE_NAME); + temp = DUMMY_BDF_FILE_NAME; + remaining = MAX_BDF_FILE_NAME; + goto bypass_bdf; + default: + cnss_pr_err("Invalid BDF type: %d\n", + plat_priv->ctrl_params.bdf_type); + ret = -EINVAL; + goto err_req_fw; + } + + ret = request_firmware(&fw_entry, filename, &plat_priv->plat_dev->dev); + if (ret) { + cnss_pr_err("Failed to load BDF: %s\n", filename); + goto err_req_fw; + } + + temp = fw_entry->data; + remaining = fw_entry->size; + +bypass_bdf: + cnss_pr_dbg("Downloading BDF: %s, size: %u\n", filename, remaining); + + while (remaining) { + req->valid = 1; + req->file_id_valid = 1; + req->file_id = plat_priv->board_info.board_id; + req->total_size_valid = 1; + req->total_size = remaining; + req->seg_id_valid = 1; + req->data_valid = 1; + req->end_valid = 1; + req->bdf_type_valid = 1; + req->bdf_type = plat_priv->ctrl_params.bdf_type; + + if (remaining > QMI_WLFW_MAX_DATA_SIZE_V01) { + req->data_len = QMI_WLFW_MAX_DATA_SIZE_V01; + } else { + req->data_len = remaining; + req->end = 1; + } + + memcpy(req->data, temp, req->data_len); + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_bdf_download_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for BDF download request, err: %d\n", + ret); + goto err_send; + } + + ret = qmi_send_request + (&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_BDF_DOWNLOAD_REQ_V01, + WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_bdf_download_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send respond BDF download request, err: %d\n", + ret); + goto err_send; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of BDF download request, err: %d\n", + ret); + goto err_send; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("BDF download request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto err_send; + } + + remaining -= req->data_len; + temp += req->data_len; + req->seg_id++; + } + + kfree(req); + kfree(resp); + return 0; + +err_send: + if (plat_priv->ctrl_params.bdf_type != CNSS_BDF_DUMMY) + release_firmware(fw_entry); +err_req_fw: + if (bdf_type != CNSS_BDF_REGDB) + CNSS_ASSERT(0); + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_m3_info_req_msg_v01 *req; + struct wlfw_m3_info_resp_msg_v01 *resp; + struct qmi_txn txn; + struct cnss_fw_mem *m3_mem = &plat_priv->m3_mem; + int ret = 0; + + cnss_pr_dbg("Sending M3 information message, state: 0x%lx\n", + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + if (!m3_mem->pa || !m3_mem->size) { + cnss_pr_err("Memory for M3 is not available\n"); + ret = -ENOMEM; + goto out; + } + + cnss_pr_dbg("M3 memory, va: 0x%pK, pa: %pa, size: 0x%zx\n", + m3_mem->va, &m3_mem->pa, m3_mem->size); + + req->addr = plat_priv->m3_mem.pa; + req->size = plat_priv->m3_mem.size; + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_m3_info_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for M3 information request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_M3_INFO_REQ_V01, + WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_m3_info_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send M3 information request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of M3 information request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("M3 information request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + CNSS_ASSERT(0); + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv, + enum cnss_driver_mode mode) +{ + struct wlfw_wlan_mode_req_msg_v01 *req; + struct wlfw_wlan_mode_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + cnss_pr_dbg("Sending mode message, mode: %s(%d), state: 0x%lx\n", + cnss_qmi_mode_to_str(mode), mode, plat_priv->driver_state); + + if (mode == CNSS_OFF && + test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) { + cnss_pr_dbg("Recovery is in progress, ignore mode off request\n"); + return 0; + } + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->mode = (enum wlfw_driver_mode_enum_v01)mode; + req->hw_debug_valid = 1; + req->hw_debug = 0; + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_wlan_mode_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for mode request, mode: %s(%d), err: %d\n", + cnss_qmi_mode_to_str(mode), mode, ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_WLAN_MODE_REQ_V01, + WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_wlan_mode_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send mode request, mode: %s(%d), err: %d\n", + cnss_qmi_mode_to_str(mode), mode, ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of mode request, mode: %s(%d), err: %d\n", + cnss_qmi_mode_to_str(mode), mode, ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Mode request failed, mode: %s(%d), result: %d, err: %d\n", + cnss_qmi_mode_to_str(mode), mode, resp->resp.result, + resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + if (mode == CNSS_OFF) { + cnss_pr_dbg("WLFW service is disconnected while sending mode off request\n"); + ret = 0; + } else { + CNSS_ASSERT(0); + } + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv, + struct cnss_wlan_enable_cfg *config, + const char *host_version) +{ + struct wlfw_wlan_cfg_req_msg_v01 *req; + struct wlfw_wlan_cfg_resp_msg_v01 *resp; + struct qmi_txn txn; + u32 i; + int ret = 0; + + cnss_pr_dbg("Sending WLAN config message, state: 0x%lx\n", + plat_priv->driver_state); + + if (!plat_priv) + return -ENODEV; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->host_version_valid = 1; + strlcpy(req->host_version, host_version, + QMI_WLFW_MAX_STR_LEN_V01 + 1); + + req->tgt_cfg_valid = 1; + if (config->num_ce_tgt_cfg > QMI_WLFW_MAX_NUM_CE_V01) + req->tgt_cfg_len = QMI_WLFW_MAX_NUM_CE_V01; + else + req->tgt_cfg_len = config->num_ce_tgt_cfg; + for (i = 0; i < req->tgt_cfg_len; i++) { + req->tgt_cfg[i].pipe_num = config->ce_tgt_cfg[i].pipe_num; + req->tgt_cfg[i].pipe_dir = config->ce_tgt_cfg[i].pipe_dir; + req->tgt_cfg[i].nentries = config->ce_tgt_cfg[i].nentries; + req->tgt_cfg[i].nbytes_max = config->ce_tgt_cfg[i].nbytes_max; + req->tgt_cfg[i].flags = config->ce_tgt_cfg[i].flags; + } + + req->svc_cfg_valid = 1; + if (config->num_ce_svc_pipe_cfg > QMI_WLFW_MAX_NUM_SVC_V01) + req->svc_cfg_len = QMI_WLFW_MAX_NUM_SVC_V01; + else + req->svc_cfg_len = config->num_ce_svc_pipe_cfg; + for (i = 0; i < req->svc_cfg_len; i++) { + req->svc_cfg[i].service_id = config->ce_svc_cfg[i].service_id; + req->svc_cfg[i].pipe_dir = config->ce_svc_cfg[i].pipe_dir; + req->svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num; + } + + req->shadow_reg_v2_valid = 1; + if (config->num_shadow_reg_v2_cfg > + QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01) + req->shadow_reg_v2_len = QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01; + else + req->shadow_reg_v2_len = config->num_shadow_reg_v2_cfg; + + memcpy(req->shadow_reg_v2, config->shadow_reg_v2_cfg, + sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01) + * req->shadow_reg_v2_len); + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_wlan_cfg_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for WLAN config request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_WLAN_CFG_REQ_V01, + WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_wlan_cfg_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send WLAN config request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of WLAN config request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("WLAN config request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + CNSS_ASSERT(0); + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv, + u32 offset, u32 mem_type, + u32 data_len, u8 *data) +{ + struct wlfw_athdiag_read_req_msg_v01 *req; + struct wlfw_athdiag_read_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) { + cnss_pr_err("Invalid parameters for athdiag read: data %p, data_len %u\n", + data, data_len); + return -EINVAL; + } + + cnss_pr_dbg("athdiag read: state 0x%lx, offset %x, mem_type %x, data_len %u\n", + plat_priv->driver_state, offset, mem_type, data_len); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->offset = offset; + req->mem_type = mem_type; + req->data_len = data_len; + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_athdiag_read_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for athdiag read request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_ATHDIAG_READ_REQ_V01, + WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_athdiag_read_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send athdiag read request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of athdiag read request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Athdiag read request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + if (!resp->data_valid || resp->data_len != data_len) { + cnss_pr_err("athdiag read data is invalid, data_valid = %u, data_len = %u\n", + resp->data_valid, resp->data_len); + ret = -EINVAL; + goto out; + } + + memcpy(data, resp->data, resp->data_len); + + kfree(req); + kfree(resp); + return 0; + +out: + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv, + u32 offset, u32 mem_type, + u32 data_len, u8 *data) +{ + struct wlfw_athdiag_write_req_msg_v01 *req; + struct wlfw_athdiag_write_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + if (!data || data_len == 0 || data_len > QMI_WLFW_MAX_DATA_SIZE_V01) { + cnss_pr_err("Invalid parameters for athdiag write: data %p, data_len %u\n", + data, data_len); + return -EINVAL; + } + + cnss_pr_dbg("athdiag write: state 0x%lx, offset %x, mem_type %x, data_len %u, data %p\n", + plat_priv->driver_state, offset, mem_type, data_len, data); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->offset = offset; + req->mem_type = mem_type; + req->data_len = data_len; + memcpy(req->data, data, data_len); + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_athdiag_write_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for athdiag write request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_ATHDIAG_WRITE_REQ_V01, + WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_athdiag_write_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send athdiag write request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of athdiag write request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Athdiag write request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv, + u8 fw_log_mode) +{ + struct wlfw_ini_req_msg_v01 *req; + struct wlfw_ini_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + cnss_pr_dbg("Sending ini sync request, state: 0x%lx, fw_log_mode: %d\n", + plat_priv->driver_state, fw_log_mode); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->enablefwlog_valid = 1; + req->enablefwlog = fw_log_mode; + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_ini_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for ini request, fw_log_mode: %d, err: %d\n", + fw_log_mode, ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_INI_REQ_V01, + WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_ini_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send ini request, fw_log_mode: %d, err: %d\n", + fw_log_mode, ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of ini request, fw_log_mode: %d, err: %d\n", + fw_log_mode, ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Ini request failed, fw_log_mode: %d, result: %d, err: %d\n", + fw_log_mode, resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_antenna_switch_req_msg_v01 *req; + struct wlfw_antenna_switch_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + cnss_pr_dbg("Sending antenna switch sync request, state: 0x%lx\n", + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_antenna_switch_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for antenna switch request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_ANTENNA_SWITCH_REQ_V01, + WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_antenna_switch_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send antenna switch request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of antenna switch request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Antenna switch request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + if (resp->antenna_valid) + plat_priv->antenna = resp->antenna; + + cnss_pr_dbg("Antenna valid: %u, antenna 0x%llx\n", + resp->antenna_valid, resp->antenna); + + kfree(req); + kfree(resp); + return 0; + +out: + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_antenna_grant_req_msg_v01 *req; + struct wlfw_antenna_grant_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + cnss_pr_dbg("Sending antenna grant sync request, state: 0x%lx, grant 0x%llx\n", + plat_priv->driver_state, plat_priv->grant); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->grant_valid = 1; + req->grant = plat_priv->grant; + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_antenna_grant_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Failed to initialize txn for antenna grant request, err: %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_ANTENNA_GRANT_REQ_V01, + WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_antenna_grant_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Failed to send antenna grant request, err: %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Failed to wait for response of antenna grant request, err: %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Antenna grant request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_qdss_trace_mem_info_req_msg_v01 *req; + struct wlfw_qdss_trace_mem_info_resp_msg_v01 *resp; + struct qmi_txn txn; + struct cnss_fw_mem *qdss_mem = plat_priv->qdss_mem; + int ret = 0; + int i; + + cnss_pr_dbg("Sending QDSS trace mem info, state: 0x%lx\n", + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->mem_seg_len = plat_priv->qdss_mem_seg_len; + for (i = 0; i < req->mem_seg_len; i++) { + cnss_pr_dbg("Memory for FW, va: 0x%pK, pa: %pa, size: 0x%zx, type: %u\n", + qdss_mem[i].va, &qdss_mem[i].pa, + qdss_mem[i].size, qdss_mem[i].type); + + req->mem_seg[i].addr = qdss_mem[i].pa; + req->mem_seg[i].size = qdss_mem[i].size; + req->mem_seg[i].type = qdss_mem[i].type; + } + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_qdss_trace_mem_info_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Fail to initialize txn for QDSS trace mem request: err %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01, + WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_qdss_trace_mem_info_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Fail to send QDSS trace mem info request: err %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Fail to wait for response of QDSS trace mem info request, err %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("QDSS trace mem info request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + kfree(req); + kfree(resp); + return ret; +} + +static int cnss_wlfw_wfc_call_status_send_sync(struct cnss_plat_data *plat_priv, + u32 data_len, const void *data) +{ + struct wlfw_wfc_call_status_req_msg_v01 *req; + struct wlfw_wfc_call_status_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + cnss_pr_dbg("Sending WFC call status: state: 0x%lx\n", + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->wfc_call_status_len = data_len; + memcpy(req->wfc_call_status, data, req->wfc_call_status_len); + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_wfc_call_status_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Fail to initialize txn for WFC call status request: err %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_WFC_CALL_STATUS_REQ_V01, + WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_wfc_call_status_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Fail to send WFC call status request: err %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Fail to wait for response of WFC call status request, err %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("WFC call status request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(req); + kfree(resp); + return 0; + +out: + kfree(req); + kfree(resp); + return ret; +} + +int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv) +{ + struct wlfw_dynamic_feature_mask_req_msg_v01 *req; + struct wlfw_dynamic_feature_mask_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + + cnss_pr_dbg("Sending dynamic feature mask 0x%llx, state: 0x%lx\n", + plat_priv->dynamic_feature, + plat_priv->driver_state); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->mask_valid = 1; + req->mask = plat_priv->dynamic_feature; + + ret = qmi_txn_init(&plat_priv->qmi_wlfw, &txn, + wlfw_dynamic_feature_mask_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Fail to initialize txn for dynamic feature mask request: err %d\n", + ret); + goto out; + } + + ret = qmi_send_request + (&plat_priv->qmi_wlfw, NULL, &txn, + QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01, + WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_dynamic_feature_mask_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Fail to send dynamic feature mask request: err %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, QMI_WLFW_TIMEOUT_JF); + if (ret < 0) { + cnss_pr_err("Fail to wait for response of dynamic feature mask request, err %d\n", + ret); + goto out; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Dynamic feature mask request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + +out: + kfree(req); + kfree(resp); + return ret; +} + +unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv) +{ + cnss_pr_dbg("QMI timeout is %u ms\n", QMI_WLFW_TIMEOUT_MS); + + return QMI_WLFW_TIMEOUT_MS; +} + +static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + const struct wlfw_request_mem_ind_msg_v01 *ind_msg = data; + int i; + + cnss_pr_dbg("Received QMI WLFW request memory indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + plat_priv->fw_mem_seg_len = ind_msg->mem_seg_len; + for (i = 0; i < plat_priv->fw_mem_seg_len; i++) { + cnss_pr_dbg("FW requests for memory, size: 0x%x, type: %u\n", + ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type); + plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type; + plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size; + } + + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_REQUEST_MEM, + 0, NULL); +} + +static void cnss_wlfw_fw_mem_ready_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + + cnss_pr_dbg("Received QMI WLFW FW memory ready indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_MEM_READY, + 0, NULL); +} + +static void cnss_wlfw_fw_ready_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + struct cnss_cal_info *cal_info; + + cnss_pr_dbg("Received QMI WLFW FW ready indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL); + if (!cal_info) + return; + + cal_info->cal_status = CNSS_CAL_DONE; + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE, + 0, cal_info); +} + +static void cnss_wlfw_fw_init_done_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + + cnss_pr_dbg("Received QMI WLFW FW initialization done indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_FW_READY, 0, NULL); +} + +static void cnss_wlfw_pin_result_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + const struct wlfw_pin_connect_result_ind_msg_v01 *ind_msg = data; + + cnss_pr_dbg("Received QMI WLFW pin connect result indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + if (ind_msg->pwr_pin_result_valid) + plat_priv->pin_result.fw_pwr_pin_result = + ind_msg->pwr_pin_result; + if (ind_msg->phy_io_pin_result_valid) + plat_priv->pin_result.fw_phy_io_pin_result = + ind_msg->phy_io_pin_result; + if (ind_msg->rf_pin_result_valid) + plat_priv->pin_result.fw_rf_pin_result = ind_msg->rf_pin_result; + + cnss_pr_dbg("Pin connect Result: pwr_pin: 0x%x phy_io_pin: 0x%x rf_io_pin: 0x%x\n", + ind_msg->pwr_pin_result, ind_msg->phy_io_pin_result, + ind_msg->rf_pin_result); +} + +static void cnss_wlfw_cal_done_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + struct cnss_cal_info *cal_info; + + cnss_pr_dbg("Received QMI WLFW calibration done indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL); + if (!cal_info) + return; + + cal_info->cal_status = CNSS_CAL_DONE; + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE, + 0, cal_info); +} + +static void cnss_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + const struct wlfw_qdss_trace_req_mem_ind_msg_v01 *ind_msg = data; + int i; + + cnss_pr_dbg("Received QMI WLFW QDSS trace request mem indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + if (plat_priv->qdss_mem_seg_len) { + cnss_pr_err("Ignore double allocation for QDSS trace, current len %u\n", + plat_priv->qdss_mem_seg_len); + return; + } + + plat_priv->qdss_mem_seg_len = ind_msg->mem_seg_len; + for (i = 0; i < plat_priv->qdss_mem_seg_len; i++) { + cnss_pr_dbg("QDSS requests for memory, size: 0x%x, type: %u\n", + ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type); + plat_priv->qdss_mem[i].type = ind_msg->mem_seg[i].type; + plat_priv->qdss_mem[i].size = ind_msg->mem_seg[i].size; + } + + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM, + 0, NULL); +} + +static void cnss_wlfw_qdss_trace_save_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + const struct wlfw_qdss_trace_save_ind_msg_v01 *ind_msg = data; + struct cnss_qmi_event_qdss_trace_save_data *event_data; + int i = 0; + + cnss_pr_dbg("Received QMI WLFW QDSS trace save indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + cnss_pr_dbg("QDSS_trace_save info: source %u, total_size %u, file_name_valid %u, file_name %s\n", + ind_msg->source, ind_msg->total_size, + ind_msg->file_name_valid, ind_msg->file_name); + + if (ind_msg->source == 1) + return; + + event_data = kzalloc(sizeof(*event_data), GFP_KERNEL); + if (!event_data) + return; + + if (ind_msg->mem_seg_valid) { + if (ind_msg->mem_seg_len > QDSS_TRACE_SEG_LEN_MAX) { + cnss_pr_err("Invalid seg len %u\n", + ind_msg->mem_seg_len); + goto free_event_data; + } + cnss_pr_dbg("QDSS_trace_save seg len %u\n", + ind_msg->mem_seg_len); + event_data->mem_seg_len = ind_msg->mem_seg_len; + for (i = 0; i < ind_msg->mem_seg_len; i++) { + event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr; + event_data->mem_seg[i].size = ind_msg->mem_seg[i].size; + cnss_pr_dbg("seg-%d: addr 0x%llx size 0x%x\n", + i, ind_msg->mem_seg[i].addr, + ind_msg->mem_seg[i].size); + } + } + + event_data->total_size = ind_msg->total_size; + + if (ind_msg->file_name_valid) + strlcpy(event_data->file_name, ind_msg->file_name, + QDSS_TRACE_FILE_NAME_MAX + 1); + else + strlcpy(event_data->file_name, "qdss_trace", + QDSS_TRACE_FILE_NAME_MAX + 1); + + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_SAVE, + 0, event_data); + + return; + +free_event_data: + kfree(event_data); +} + +static void cnss_wlfw_qdss_trace_free_ind_cb(struct qmi_handle *qmi_wlfw, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_QDSS_TRACE_FREE, + 0, NULL); +} + +static struct qmi_msg_handler qmi_wlfw_msg_handlers[] = { + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_REQUEST_MEM_IND_V01, + .ei = wlfw_request_mem_ind_msg_v01_ei, + .decoded_size = sizeof(struct wlfw_request_mem_ind_msg_v01), + .fn = cnss_wlfw_request_mem_ind_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_FW_MEM_READY_IND_V01, + .ei = wlfw_fw_mem_ready_ind_msg_v01_ei, + .decoded_size = sizeof(struct wlfw_fw_mem_ready_ind_msg_v01), + .fn = cnss_wlfw_fw_mem_ready_ind_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_FW_READY_IND_V01, + .ei = wlfw_fw_ready_ind_msg_v01_ei, + .decoded_size = sizeof(struct wlfw_fw_ready_ind_msg_v01), + .fn = cnss_wlfw_fw_ready_ind_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_FW_INIT_DONE_IND_V01, + .ei = wlfw_fw_init_done_ind_msg_v01_ei, + .decoded_size = sizeof(struct wlfw_fw_init_done_ind_msg_v01), + .fn = cnss_wlfw_fw_init_done_ind_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_PIN_CONNECT_RESULT_IND_V01, + .ei = wlfw_pin_connect_result_ind_msg_v01_ei, + .decoded_size = + sizeof(struct wlfw_pin_connect_result_ind_msg_v01), + .fn = cnss_wlfw_pin_result_ind_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_CAL_DONE_IND_V01, + .ei = wlfw_cal_done_ind_msg_v01_ei, + .decoded_size = sizeof(struct wlfw_cal_done_ind_msg_v01), + .fn = cnss_wlfw_cal_done_ind_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01, + .ei = wlfw_qdss_trace_req_mem_ind_msg_v01_ei, + .decoded_size = + sizeof(struct wlfw_qdss_trace_req_mem_ind_msg_v01), + .fn = cnss_wlfw_qdss_trace_req_mem_ind_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01, + .ei = wlfw_qdss_trace_save_ind_msg_v01_ei, + .decoded_size = + sizeof(struct wlfw_qdss_trace_save_ind_msg_v01), + .fn = cnss_wlfw_qdss_trace_save_ind_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_QDSS_TRACE_FREE_IND_V01, + .ei = wlfw_qdss_trace_free_ind_msg_v01_ei, + .decoded_size = + sizeof(struct wlfw_qdss_trace_free_ind_msg_v01), + .fn = cnss_wlfw_qdss_trace_free_ind_cb + }, + {} +}; + +static int cnss_wlfw_connect_to_server(struct cnss_plat_data *plat_priv, + void *data) +{ + struct cnss_qmi_event_server_arrive_data *event_data = data; + struct qmi_handle *qmi_wlfw = &plat_priv->qmi_wlfw; + struct sockaddr_qrtr sq = { 0 }; + int ret = 0; + + if (!event_data) + return -EINVAL; + + sq.sq_family = AF_QIPCRTR; + sq.sq_node = event_data->node; + sq.sq_port = event_data->port; + + ret = kernel_connect(qmi_wlfw->sock, (struct sockaddr *)&sq, + sizeof(sq), 0); + if (ret < 0) { + cnss_pr_err("Failed to connect to QMI WLFW remote service port\n"); + goto out; + } + + set_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state); + + cnss_pr_info("QMI WLFW service connected, state: 0x%lx\n", + plat_priv->driver_state); + + kfree(data); + return 0; + +out: + CNSS_ASSERT(0); + kfree(data); + return ret; +} + +int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data) +{ + int ret = 0; + + if (!plat_priv) + return -ENODEV; + + ret = cnss_wlfw_connect_to_server(plat_priv, data); + if (ret < 0) + goto out; + + ret = cnss_wlfw_ind_register_send_sync(plat_priv); + if (ret < 0) { + if (ret == -EALREADY) + ret = 0; + goto out; + } + + ret = cnss_wlfw_host_cap_send_sync(plat_priv); + if (ret < 0) + goto out; + + return 0; + +out: + return ret; +} + +int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv) +{ + if (!plat_priv) + return -ENODEV; + + clear_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state); + + cnss_pr_info("QMI WLFW service disconnected, state: 0x%lx\n", + plat_priv->driver_state); + + return 0; +} + +static int wlfw_new_server(struct qmi_handle *qmi_wlfw, + struct qmi_service *service) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + struct cnss_qmi_event_server_arrive_data *event_data; + + cnss_pr_dbg("WLFW server arriving: node %u port %u\n", + service->node, service->port); + + event_data = kzalloc(sizeof(*event_data), GFP_KERNEL); + if (!event_data) + return -ENOMEM; + + event_data->node = service->node; + event_data->port = service->port; + + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_ARRIVE, + 0, event_data); + + return 0; +} + +static void wlfw_del_server(struct qmi_handle *qmi_wlfw, + struct qmi_service *service) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi_wlfw, struct cnss_plat_data, qmi_wlfw); + + cnss_pr_dbg("WLFW server exiting\n"); + + cnss_driver_event_post(plat_priv, CNSS_DRIVER_EVENT_SERVER_EXIT, + 0, NULL); +} + +static struct qmi_ops qmi_wlfw_ops = { + .new_server = wlfw_new_server, + .del_server = wlfw_del_server, +}; + +int cnss_qmi_init(struct cnss_plat_data *plat_priv) +{ + int ret = 0; + + ret = qmi_handle_init(&plat_priv->qmi_wlfw, + QMI_WLFW_MAX_RECV_BUF_SIZE, + &qmi_wlfw_ops, qmi_wlfw_msg_handlers); + if (ret < 0) { + cnss_pr_err("Failed to initialize QMI handle, err: %d\n", ret); + goto out; + } + + ret = qmi_add_lookup(&plat_priv->qmi_wlfw, WLFW_SERVICE_ID_V01, + WLFW_SERVICE_VERS_V01, WLFW_SERVICE_INS_ID_V01); + if (ret < 0) + cnss_pr_err("Failed to add QMI lookup, err: %d\n", ret); + +out: + return ret; +} + +void cnss_qmi_deinit(struct cnss_plat_data *plat_priv) +{ + qmi_handle_release(&plat_priv->qmi_wlfw); +} + +int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv) +{ + int ret; + struct coex_antenna_switch_to_wlan_req_msg_v01 *req; + struct coex_antenna_switch_to_wlan_resp_msg_v01 *resp; + struct qmi_txn txn; + + if (!plat_priv) + return -ENODEV; + + cnss_pr_dbg("Sending coex antenna switch_to_wlan\n"); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->antenna = plat_priv->antenna; + + ret = qmi_txn_init(&plat_priv->coex_qmi, &txn, + coex_antenna_switch_to_wlan_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Fail to init txn for coex antenna switch_to_wlan resp %d\n", + ret); + goto out; + } + + ret = qmi_send_request + (&plat_priv->coex_qmi, NULL, &txn, + QMI_COEX_SWITCH_ANTENNA_TO_WLAN_REQ_V01, + COEX_ANTENNA_SWITCH_TO_WLAN_REQ_MSG_V01_MAX_MSG_LEN, + coex_antenna_switch_to_wlan_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Fail to send coex antenna switch_to_wlan req %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, COEX_TIMEOUT); + if (ret < 0) { + cnss_pr_err("Coex antenna switch_to_wlan resp wait failed with ret %d\n", + ret); + goto out; + } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Coex antenna switch_to_wlan request rejected, result:%d error:%d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + if (resp->grant_valid) + plat_priv->grant = resp->grant; + + cnss_pr_dbg("Coex antenna grant: 0x%llx\n", resp->grant); + + kfree(resp); + kfree(req); + return 0; + +out: + kfree(resp); + kfree(req); + return ret; +} + +int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv) +{ + int ret; + struct coex_antenna_switch_to_mdm_req_msg_v01 *req; + struct coex_antenna_switch_to_mdm_resp_msg_v01 *resp; + struct qmi_txn txn; + + if (!plat_priv) + return -ENODEV; + + cnss_pr_dbg("Sending coex antenna switch_to_mdm\n"); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->antenna = plat_priv->antenna; + + ret = qmi_txn_init(&plat_priv->coex_qmi, &txn, + coex_antenna_switch_to_mdm_resp_msg_v01_ei, resp); + if (ret < 0) { + cnss_pr_err("Fail to init txn for coex antenna switch_to_mdm resp %d\n", + ret); + goto out; + } + + ret = qmi_send_request + (&plat_priv->coex_qmi, NULL, &txn, + QMI_COEX_SWITCH_ANTENNA_TO_MDM_REQ_V01, + COEX_ANTENNA_SWITCH_TO_MDM_REQ_MSG_V01_MAX_MSG_LEN, + coex_antenna_switch_to_mdm_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + cnss_pr_err("Fail to send coex antenna switch_to_mdm req %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, COEX_TIMEOUT); + if (ret < 0) { + cnss_pr_err("Coex antenna switch_to_mdm resp wait failed with ret %d\n", + ret); + goto out; + } else if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("Coex antenna switch_to_mdm request rejected, result:%d error:%d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto out; + } + + kfree(resp); + kfree(req); + return 0; + +out: + kfree(resp); + kfree(req); + return ret; +} + +static int coex_new_server(struct qmi_handle *qmi, + struct qmi_service *service) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi, struct cnss_plat_data, coex_qmi); + struct sockaddr_qrtr sq = { 0 }; + int ret = 0; + + cnss_pr_dbg("COEX server arrive: node %u port %u\n", + service->node, service->port); + + sq.sq_family = AF_QIPCRTR; + sq.sq_node = service->node; + sq.sq_port = service->port; + ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0); + if (ret < 0) { + cnss_pr_err("Fail to connect to remote service port\n"); + return ret; + } + + set_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state); + cnss_pr_dbg("COEX Server Connected: 0x%lx\n", + plat_priv->driver_state); + return 0; +} + +static void coex_del_server(struct qmi_handle *qmi, + struct qmi_service *service) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi, struct cnss_plat_data, coex_qmi); + + cnss_pr_dbg("COEX server exit\n"); + + clear_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state); +} + +static struct qmi_ops coex_qmi_ops = { + .new_server = coex_new_server, + .del_server = coex_del_server, +}; + +int cnss_register_coex_service(struct cnss_plat_data *plat_priv) +{ int ret; + + ret = qmi_handle_init(&plat_priv->coex_qmi, + COEX_SERVICE_MAX_MSG_LEN, + &coex_qmi_ops, NULL); + if (ret < 0) + return ret; + + ret = qmi_add_lookup(&plat_priv->coex_qmi, COEX_SERVICE_ID_V01, + COEX_SERVICE_VERS_V01, 0); + return ret; +} + +void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv) +{ + qmi_handle_release(&plat_priv->coex_qmi); +} + +/* IMS Service */ +int ims_subscribe_for_indication_send_async(struct cnss_plat_data *plat_priv) +{ + int ret; + struct ims_private_service_subscribe_for_indications_req_msg_v01 *req; + struct qmi_txn *txn; + + if (!plat_priv) + return -ENODEV; + + cnss_pr_dbg("Sending ASYNC ims subscribe for indication\n"); + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + req->wfc_call_status_valid = 1; + req->wfc_call_status = 1; + + txn = &plat_priv->txn; + ret = qmi_txn_init(&plat_priv->ims_qmi, txn, NULL, NULL); + if (ret < 0) { + cnss_pr_err("Fail to init txn for ims subscribe for indication resp %d\n", + ret); + goto out; + } + + ret = qmi_send_request + (&plat_priv->ims_qmi, NULL, txn, + QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01, + IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_MSG_V01_MAX_MSG_LEN, + ims_private_service_subscribe_for_indications_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(txn); + cnss_pr_err("Fail to send ims subscribe for indication req %d\n", + ret); + goto out; + } + + kfree(req); + return 0; + +out: + kfree(req); + return ret; +} + +static void ims_subscribe_for_indication_resp_cb(struct qmi_handle *qmi, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + const + struct ims_private_service_subscribe_for_indications_rsp_msg_v01 *resp = + data; + + cnss_pr_dbg("Received IMS subscribe indication response\n"); + + if (!txn) { + cnss_pr_err("spurious response\n"); + return; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + cnss_pr_err("IMS subscribe for indication request rejected, result:%d error:%d\n", + resp->resp.result, resp->resp.error); + txn->result = -resp->resp.result; + } +} + +static void ims_wfc_call_status_ind_cb(struct qmi_handle *ims_qmi, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, const void *data) +{ + struct cnss_plat_data *plat_priv = + container_of(ims_qmi, struct cnss_plat_data, ims_qmi); + const + struct ims_private_service_wfc_call_status_ind_msg_v01 *ind_msg = data; + u32 data_len = 0; + + cnss_pr_dbg("Received IMS wfc call status indication\n"); + + if (!txn) { + cnss_pr_err("Spurious indication\n"); + return; + } + + if (!ind_msg) { + cnss_pr_err("Invalid indication\n"); + return; + } + + data_len = sizeof(*ind_msg); + if (data_len > QMI_WLFW_MAX_WFC_CALL_STATUS_DATA_SIZE_V01) { + cnss_pr_err("Exceed maxinum data len:%u\n", data_len); + return; + } + + cnss_wlfw_wfc_call_status_send_sync(plat_priv, data_len, ind_msg); +} + +static struct qmi_msg_handler qmi_ims_msg_handlers[] = { + { + .type = QMI_RESPONSE, + .msg_id = + QMI_IMS_PRIVATE_SERVICE_SUBSCRIBE_FOR_INDICATIONS_REQ_V01, + .ei = + ims_private_service_subscribe_for_indications_rsp_msg_v01_ei, + .decoded_size = sizeof(struct + ims_private_service_subscribe_for_indications_rsp_msg_v01), + .fn = ims_subscribe_for_indication_resp_cb + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_IMS_PRIVATE_SERVICE_WFC_CALL_STATUS_IND_V01, + .ei = ims_private_service_wfc_call_status_ind_msg_v01_ei, + .decoded_size = + sizeof(struct ims_private_service_wfc_call_status_ind_msg_v01), + .fn = ims_wfc_call_status_ind_cb + }, + {} +}; + +static int ims_new_server(struct qmi_handle *qmi, + struct qmi_service *service) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi, struct cnss_plat_data, ims_qmi); + struct sockaddr_qrtr sq = { 0 }; + int ret = 0; + + cnss_pr_dbg("IMS server arrive: node %u port %u\n", + service->node, service->port); + + sq.sq_family = AF_QIPCRTR; + sq.sq_node = service->node; + sq.sq_port = service->port; + ret = kernel_connect(qmi->sock, (struct sockaddr *)&sq, sizeof(sq), 0); + if (ret < 0) { + cnss_pr_err("Fail to connect to remote service port\n"); + return ret; + } + + set_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state); + cnss_pr_dbg("IMS Server Connected: 0x%lx\n", + plat_priv->driver_state); + + ret = ims_subscribe_for_indication_send_async(plat_priv); + return ret; +} + +static void ims_del_server(struct qmi_handle *qmi, + struct qmi_service *service) +{ + struct cnss_plat_data *plat_priv = + container_of(qmi, struct cnss_plat_data, ims_qmi); + + cnss_pr_dbg("IMS server exit\n"); + + clear_bit(CNSS_IMS_CONNECTED, &plat_priv->driver_state); +} + +static struct qmi_ops ims_qmi_ops = { + .new_server = ims_new_server, + .del_server = ims_del_server, +}; + +int cnss_register_ims_service(struct cnss_plat_data *plat_priv) +{ int ret; + + ret = qmi_handle_init(&plat_priv->ims_qmi, + IMSPRIVATE_SERVICE_MAX_MSG_LEN, + &ims_qmi_ops, qmi_ims_msg_handlers); + if (ret < 0) + return ret; + + ret = qmi_add_lookup(&plat_priv->ims_qmi, IMSPRIVATE_SERVICE_ID_V01, + IMSPRIVATE_SERVICE_VERS_V01, 0); + return ret; +} + +void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv) +{ + qmi_handle_release(&plat_priv->ims_qmi); +} diff --git a/drivers/net/wireless/cnss2/qmi.h b/drivers/net/wireless/cnss2/qmi.h new file mode 100644 index 000000000000..a06466097b20 --- /dev/null +++ b/drivers/net/wireless/cnss2/qmi.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. */ + +#ifndef _CNSS_QMI_H +#define _CNSS_QMI_H + +#include + +struct cnss_plat_data; + +struct cnss_qmi_event_server_arrive_data { + unsigned int node; + unsigned int port; +}; + +#define QDSS_TRACE_SEG_LEN_MAX 32 +#define QDSS_TRACE_FILE_NAME_MAX 16 + +struct cnss_mem_seg { + u64 addr; + u32 size; +}; + +struct cnss_qmi_event_qdss_trace_save_data { + u32 total_size; + u32 mem_seg_len; + struct cnss_mem_seg mem_seg[QDSS_TRACE_SEG_LEN_MAX]; + char file_name[QDSS_TRACE_FILE_NAME_MAX + 1]; +}; + +#ifdef CONFIG_CNSS2_QMI +#include "wlan_firmware_service_v01.h" +#include "coexistence_service_v01.h" +#include "ip_multimedia_subsystem_private_service_v01.h" + +int cnss_qmi_init(struct cnss_plat_data *plat_priv); +void cnss_qmi_deinit(struct cnss_plat_data *plat_priv); +unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv); +int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, void *data); +int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv); +int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv); +int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv); +int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv, + u32 bdf_type); +int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv); +int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv, + enum cnss_driver_mode mode); +int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv, + struct cnss_wlan_enable_cfg *config, + const char *host_version); +int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv, + u32 offset, u32 mem_type, + u32 data_len, u8 *data); +int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv, + u32 offset, u32 mem_type, + u32 data_len, u8 *data); +int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv, + u8 fw_log_mode); +int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv); +int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv); +int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv); +int cnss_register_coex_service(struct cnss_plat_data *plat_priv); +void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv); +int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv); +int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv); +int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv); +int cnss_register_ims_service(struct cnss_plat_data *plat_priv); +void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv); +#else +#define QMI_WLFW_TIMEOUT_MS 10000 + +static inline int cnss_qmi_init(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline void cnss_qmi_deinit(struct cnss_plat_data *plat_priv) +{ +} + +static inline +unsigned int cnss_get_qmi_timeout(struct cnss_plat_data *plat_priv) +{ + return QMI_WLFW_TIMEOUT_MS; +} + +static inline int cnss_wlfw_server_arrive(struct cnss_plat_data *plat_priv, + void *data) +{ + return 0; +} + +static inline int cnss_wlfw_server_exit(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +int cnss_wlfw_respond_mem_send_sync(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline int cnss_wlfw_tgt_cap_send_sync(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline int cnss_wlfw_bdf_dnld_send_sync(struct cnss_plat_data *plat_priv, + u32 bdf_type) +{ + return 0; +} + +static inline int cnss_wlfw_m3_dnld_send_sync(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +int cnss_wlfw_wlan_mode_send_sync(struct cnss_plat_data *plat_priv, + enum cnss_driver_mode mode) +{ + return 0; +} + +static inline +int cnss_wlfw_wlan_cfg_send_sync(struct cnss_plat_data *plat_priv, + struct cnss_wlan_enable_cfg *config, + const char *host_version) +{ + return 0; +} + +static inline +int cnss_wlfw_athdiag_read_send_sync(struct cnss_plat_data *plat_priv, + u32 offset, u32 mem_type, + u32 data_len, u8 *data) +{ + return 0; +} + +static inline +int cnss_wlfw_athdiag_write_send_sync(struct cnss_plat_data *plat_priv, + u32 offset, u32 mem_type, + u32 data_len, u8 *data) +{ + return 0; +} + +static inline +int cnss_wlfw_ini_send_sync(struct cnss_plat_data *plat_priv, + u8 fw_log_mode) +{ + return 0; +} + +static inline +int cnss_wlfw_antenna_switch_send_sync(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +int cnss_wlfw_antenna_grant_send_sync(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +int cnss_wlfw_dynamic_feature_mask_send_sync(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +int cnss_register_coex_service(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +void cnss_unregister_coex_service(struct cnss_plat_data *plat_priv) {} + +static inline +int coex_antenna_switch_to_wlan_send_sync_msg(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +int coex_antenna_switch_to_mdm_send_sync_msg(struct cnss_plat_data *plat_priv) + +static inline +int cnss_wlfw_qdss_trace_mem_info_send_sync(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +int cnss_register_ims_service(struct cnss_plat_data *plat_priv) +{ + return 0; +} + +static inline +void cnss_unregister_ims_service(struct cnss_plat_data *plat_priv) {} + +#endif /* CONFIG_CNSS2_QMI */ + +#endif /* _CNSS_QMI_H */ diff --git a/drivers/net/wireless/cnss2/wlan_firmware_service_v01.c b/drivers/net/wireless/cnss2/wlan_firmware_service_v01.c new file mode 100644 index 000000000000..03a418ed5b74 --- /dev/null +++ b/drivers/net/wireless/cnss2/wlan_firmware_service_v01.c @@ -0,0 +1,3610 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. */ + +#include "wlan_firmware_service_v01.h" + +static struct qmi_elem_info wlfw_ce_tgt_pipe_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, + pipe_num), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_pipedir_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, + pipe_dir), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, + nentries), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, + nbytes_max), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01, + flags), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_ce_svc_pipe_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01, + service_id), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_pipedir_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01, + pipe_dir), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01, + pipe_num), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_shadow_reg_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_shadow_reg_cfg_s_v01, + id), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_shadow_reg_cfg_s_v01, + offset), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_shadow_reg_v2_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_shadow_reg_v2_cfg_s_v01, + addr), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_rri_over_ddr_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_rri_over_ddr_cfg_s_v01, + base_addr_low), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_rri_over_ddr_cfg_s_v01, + base_addr_high), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_msi_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_msi_cfg_s_v01, + ce_id), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_msi_cfg_s_v01, + msi_vector), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_memory_region_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_memory_region_info_s_v01, + region_addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_memory_region_info_s_v01, + size), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_memory_region_info_s_v01, + secure_flag), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_mem_cfg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_cfg_s_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_cfg_s_v01, + size), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_cfg_s_v01, + secure_flag), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_mem_seg_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_seg_s_v01, + size), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_mem_type_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_seg_s_v01, + type), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_seg_s_v01, + mem_cfg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_MEM_CFG_V01, + .elem_size = sizeof(struct wlfw_mem_cfg_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_seg_s_v01, + mem_cfg), + .ei_array = wlfw_mem_cfg_s_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_mem_seg_resp_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_seg_resp_s_v01, + addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_seg_resp_s_v01, + size), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_mem_type_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_seg_resp_s_v01, + type), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_mem_seg_resp_s_v01, + restore), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_rf_chip_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_rf_chip_info_s_v01, + chip_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_rf_chip_info_s_v01, + chip_family), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_rf_board_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_rf_board_info_s_v01, + board_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_soc_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_soc_info_s_v01, + soc_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info wlfw_fw_version_info_s_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_fw_version_info_s_v01, + fw_version), + }, + { + .data_type = QMI_STRING, + .elem_len = QMI_WLFW_MAX_TIMESTAMP_LEN_V01 + 1, + .elem_size = sizeof(char), + .array_type = NO_ARRAY, + .tlv_type = 0, + .offset = offsetof(struct wlfw_fw_version_info_s_v01, + fw_build_timestamp), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_ind_register_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_ind_register_req_msg_v01, + fw_ready_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + fw_ready_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + initiate_cal_download_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + initiate_cal_download_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + initiate_cal_update_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + initiate_cal_update_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + msa_ready_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + msa_ready_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + pin_connect_result_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + pin_connect_result_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + client_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + client_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + request_mem_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + request_mem_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + fw_mem_ready_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + fw_mem_ready_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + fw_init_done_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + fw_init_done_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + rejuvenate_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + rejuvenate_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1A, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + xo_cal_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1A, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + xo_cal_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1B, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + cal_done_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1B, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + cal_done_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + qdss_trace_req_mem_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + qdss_trace_req_mem_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + qdss_trace_save_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + qdss_trace_save_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1E, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + qdss_trace_free_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1E, + .offset = offsetof(struct wlfw_ind_register_req_msg_v01, + qdss_trace_free_enable), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_ind_register_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_ind_register_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_ind_register_resp_msg_v01, + fw_status_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_ind_register_resp_msg_v01, + fw_status), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_fw_ready_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_msa_ready_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_pin_connect_result_ind_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_pin_connect_result_ind_msg_v01, + pwr_pin_result_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_pin_connect_result_ind_msg_v01, + pwr_pin_result), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_pin_connect_result_ind_msg_v01, + phy_io_pin_result_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_pin_connect_result_ind_msg_v01, + phy_io_pin_result), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + wlfw_pin_connect_result_ind_msg_v01, + rf_pin_result_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + wlfw_pin_connect_result_ind_msg_v01, + rf_pin_result), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_wlan_mode_req_msg_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_driver_mode_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_wlan_mode_req_msg_v01, + mode), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_wlan_mode_req_msg_v01, + hw_debug_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_wlan_mode_req_msg_v01, + hw_debug), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_wlan_mode_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_wlan_mode_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_wlan_cfg_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + host_version_valid), + }, + { + .data_type = QMI_STRING, + .elem_len = QMI_WLFW_MAX_STR_LEN_V01 + 1, + .elem_size = sizeof(char), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + host_version), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + tgt_cfg_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + tgt_cfg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_CE_V01, + .elem_size = sizeof(struct wlfw_ce_tgt_pipe_cfg_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + tgt_cfg), + .ei_array = wlfw_ce_tgt_pipe_cfg_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + svc_cfg_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + svc_cfg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_SVC_V01, + .elem_size = sizeof(struct wlfw_ce_svc_pipe_cfg_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + svc_cfg), + .ei_array = wlfw_ce_svc_pipe_cfg_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + shadow_reg_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + shadow_reg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_SHADOW_REG_V01, + .elem_size = sizeof(struct wlfw_shadow_reg_cfg_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + shadow_reg), + .ei_array = wlfw_shadow_reg_cfg_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + shadow_reg_v2_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + shadow_reg_v2_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01, + .elem_size = sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + shadow_reg_v2), + .ei_array = wlfw_shadow_reg_v2_cfg_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + rri_over_ddr_cfg_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct wlfw_rri_over_ddr_cfg_s_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + rri_over_ddr_cfg), + .ei_array = wlfw_rri_over_ddr_cfg_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + msi_cfg_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + msi_cfg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_CE_V01, + .elem_size = sizeof(struct wlfw_msi_cfg_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01, + msi_cfg), + .ei_array = wlfw_msi_cfg_s_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_wlan_cfg_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_wlan_cfg_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cap_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cap_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + chip_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct wlfw_rf_chip_info_s_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + chip_info), + .ei_array = wlfw_rf_chip_info_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + board_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct wlfw_rf_board_info_s_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + board_info), + .ei_array = wlfw_rf_board_info_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + soc_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct wlfw_soc_info_s_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + soc_info), + .ei_array = wlfw_soc_info_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + fw_version_info_valid), + }, + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct wlfw_fw_version_info_s_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + fw_version_info), + .ei_array = wlfw_fw_version_info_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + fw_build_id_valid), + }, + { + .data_type = QMI_STRING, + .elem_len = QMI_WLFW_MAX_BUILD_ID_LEN_V01 + 1, + .elem_size = sizeof(char), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + fw_build_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + num_macs_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + num_macs), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + voltage_mv_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + voltage_mv), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + time_freq_hz_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + time_freq_hz), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + otp_version_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof(struct wlfw_cap_resp_msg_v01, + otp_version), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_bdf_download_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + valid), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + file_id_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_cal_temp_id_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + file_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + total_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + seg_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + seg_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + data), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + end_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + end), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + bdf_type_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_bdf_download_req_msg_v01, + bdf_type), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_bdf_download_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_bdf_download_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cal_report_req_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_cal_report_req_msg_v01, + meta_data_len), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = QMI_WLFW_MAX_NUM_CAL_V01, + .elem_size = sizeof(enum wlfw_cal_temp_id_enum_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_cal_report_req_msg_v01, + meta_data), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_cal_report_req_msg_v01, + xo_cal_data_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_cal_report_req_msg_v01, + xo_cal_data), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cal_report_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_cal_report_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_initiate_cal_download_ind_msg_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_cal_temp_id_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_initiate_cal_download_ind_msg_v01, + cal_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_initiate_cal_download_ind_msg_v01, + total_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_initiate_cal_download_ind_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_initiate_cal_download_ind_msg_v01, + cal_data_location_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_initiate_cal_download_ind_msg_v01, + cal_data_location), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cal_download_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + valid), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + file_id_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_cal_temp_id_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + file_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + total_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + seg_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + seg_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + data), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + end_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + end), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + cal_data_location_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_cal_download_req_msg_v01, + cal_data_location), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cal_download_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_cal_download_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_initiate_cal_update_ind_msg_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_cal_temp_id_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_initiate_cal_update_ind_msg_v01, + cal_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_initiate_cal_update_ind_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_initiate_cal_update_ind_msg_v01, + cal_data_location_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_initiate_cal_update_ind_msg_v01, + cal_data_location), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cal_update_req_msg_v01_ei[] = { + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_cal_temp_id_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_cal_update_req_msg_v01, + cal_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_cal_update_req_msg_v01, + seg_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cal_update_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + file_id_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_cal_temp_id_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + file_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + total_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + seg_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + seg_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + data), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + end_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + end), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + cal_data_location_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_cal_update_resp_msg_v01, + cal_data_location), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_msa_info_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_msa_info_req_msg_v01, + msa_addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_msa_info_req_msg_v01, + size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_msa_info_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_msa_info_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct wlfw_msa_info_resp_msg_v01, + mem_region_info_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_MEMORY_REGIONS_V01, + .elem_size = sizeof(struct wlfw_memory_region_info_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct wlfw_msa_info_resp_msg_v01, + mem_region_info), + .ei_array = wlfw_memory_region_info_s_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_msa_ready_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_msa_ready_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_msa_ready_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_ini_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_ini_req_msg_v01, + enablefwlog_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_ini_req_msg_v01, + enablefwlog), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_ini_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_ini_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_athdiag_read_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_athdiag_read_req_msg_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_athdiag_read_req_msg_v01, + mem_type), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct wlfw_athdiag_read_req_msg_v01, + data_len), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_athdiag_read_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_athdiag_read_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_athdiag_read_resp_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_athdiag_read_resp_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_athdiag_read_resp_msg_v01, + data), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_athdiag_write_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_athdiag_write_req_msg_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_athdiag_write_req_msg_v01, + mem_type), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct + wlfw_athdiag_write_req_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct + wlfw_athdiag_write_req_msg_v01, + data), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_athdiag_write_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_athdiag_write_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_vbatt_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_vbatt_req_msg_v01, + voltage_uv), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_vbatt_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_vbatt_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_mac_addr_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_mac_addr_req_msg_v01, + mac_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAC_ADDR_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = STATIC_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_mac_addr_req_msg_v01, + mac_addr), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_mac_addr_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_mac_addr_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_host_cap_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + num_clients_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + num_clients), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + wake_msi_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + wake_msi), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + gpios_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + gpios_len), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = QMI_WLFW_MAX_NUM_GPIO_V01, + .elem_size = sizeof(u32), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + gpios), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + nm_modem_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + nm_modem), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + bdf_support_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + bdf_support), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + bdf_cache_support_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x15, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + bdf_cache_support), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + m3_support_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x16, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + m3_support), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + m3_cache_support_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x17, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + m3_cache_support), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + cal_filesys_support_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x18, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + cal_filesys_support), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + cal_cache_support_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x19, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + cal_cache_support), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1A, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + cal_done_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1A, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + cal_done), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1B, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + mem_bucket_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x1B, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + mem_bucket), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + mem_cfg_mode_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + mem_cfg_mode), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + cal_duration_valid), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof(struct wlfw_host_cap_req_msg_v01, + cal_duration), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_host_cap_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_host_cap_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_request_mem_ind_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_request_mem_ind_msg_v01, + mem_seg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_MEM_SEG_V01, + .elem_size = sizeof(struct wlfw_mem_seg_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_request_mem_ind_msg_v01, + mem_seg), + .ei_array = wlfw_mem_seg_s_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_respond_mem_req_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_respond_mem_req_msg_v01, + mem_seg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_MEM_SEG_V01, + .elem_size = sizeof(struct wlfw_mem_seg_resp_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_respond_mem_req_msg_v01, + mem_seg), + .ei_array = wlfw_mem_seg_resp_s_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_respond_mem_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_respond_mem_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_fw_mem_ready_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_fw_init_done_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_rejuvenate_ind_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_rejuvenate_ind_msg_v01, + cause_for_rejuvenation_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_rejuvenate_ind_msg_v01, + cause_for_rejuvenation), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_rejuvenate_ind_msg_v01, + requesting_sub_system_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlfw_rejuvenate_ind_msg_v01, + requesting_sub_system), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_rejuvenate_ind_msg_v01, + line_number_valid), + }, + { + .data_type = QMI_UNSIGNED_2_BYTE, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlfw_rejuvenate_ind_msg_v01, + line_number), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_rejuvenate_ind_msg_v01, + function_name_valid), + }, + { + .data_type = QMI_STRING, + .elem_len = QMI_WLFW_FUNCTION_NAME_LEN_V01 + 1, + .elem_size = sizeof(char), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlfw_rejuvenate_ind_msg_v01, + function_name), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_rejuvenate_ack_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_rejuvenate_ack_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_rejuvenate_ack_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_dynamic_feature_mask_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_dynamic_feature_mask_req_msg_v01, + mask_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_dynamic_feature_mask_req_msg_v01, + mask), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_dynamic_feature_mask_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_dynamic_feature_mask_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_dynamic_feature_mask_resp_msg_v01, + prev_mask_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_dynamic_feature_mask_resp_msg_v01, + prev_mask), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_dynamic_feature_mask_resp_msg_v01, + curr_mask_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_dynamic_feature_mask_resp_msg_v01, + curr_mask), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_m3_info_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_m3_info_req_msg_v01, + addr), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_m3_info_req_msg_v01, + size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_m3_info_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_m3_info_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_xo_cal_ind_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct wlfw_xo_cal_ind_msg_v01, + xo_cal_data), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_cal_done_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_req_mem_ind_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_qdss_trace_req_mem_ind_msg_v01, + mem_seg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_MEM_SEG_V01, + .elem_size = sizeof(struct wlfw_mem_seg_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_qdss_trace_req_mem_ind_msg_v01, + mem_seg), + .ei_array = wlfw_mem_seg_s_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_mem_info_req_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_qdss_trace_mem_info_req_msg_v01, + mem_seg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_MEM_SEG_V01, + .elem_size = sizeof(struct wlfw_mem_seg_resp_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_qdss_trace_mem_info_req_msg_v01, + mem_seg), + .ei_array = wlfw_mem_seg_resp_s_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_mem_info_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_qdss_trace_mem_info_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_save_ind_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_qdss_trace_save_ind_msg_v01, + source), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_qdss_trace_save_ind_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_save_ind_msg_v01, + mem_seg_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_save_ind_msg_v01, + mem_seg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_MEM_SEG_V01, + .elem_size = sizeof(struct wlfw_mem_seg_resp_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_save_ind_msg_v01, + mem_seg), + .ei_array = wlfw_mem_seg_resp_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_qdss_trace_save_ind_msg_v01, + file_name_valid), + }, + { + .data_type = QMI_STRING, + .elem_len = QMI_WLFW_MAX_STR_LEN_V01 + 1, + .elem_size = sizeof(char), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_qdss_trace_save_ind_msg_v01, + file_name), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_data_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_qdss_trace_data_req_msg_v01, + seg_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_data_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + total_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + seg_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + seg_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + data), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + end_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct + wlfw_qdss_trace_data_resp_msg_v01, + end), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_config_download_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + total_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + seg_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + seg_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + data), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + end_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_req_msg_v01, + end), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_config_download_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_qdss_trace_config_download_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_mode_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_mode_req_msg_v01, + mode_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlfw_qdss_trace_mode_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_mode_req_msg_v01, + mode), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_qdss_trace_mode_req_msg_v01, + option_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + wlfw_qdss_trace_mode_req_msg_v01, + option), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_mode_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_qdss_trace_mode_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_qdss_trace_free_ind_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_free_ind_msg_v01, + mem_seg_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_free_ind_msg_v01, + mem_seg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = QMI_WLFW_MAX_NUM_MEM_SEG_V01, + .elem_size = sizeof(struct wlfw_mem_seg_resp_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_qdss_trace_free_ind_msg_v01, + mem_seg), + .ei_array = wlfw_mem_seg_resp_s_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_shutdown_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_shutdown_req_msg_v01, + shutdown_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_shutdown_req_msg_v01, + shutdown), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_shutdown_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_shutdown_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_antenna_switch_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_antenna_switch_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_antenna_switch_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_antenna_switch_resp_msg_v01, + antenna_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_antenna_switch_resp_msg_v01, + antenna), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_antenna_grant_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_antenna_grant_req_msg_v01, + grant_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + wlfw_antenna_grant_req_msg_v01, + grant), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_antenna_grant_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_antenna_grant_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_wfc_call_status_req_msg_v01_ei[] = { + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_wfc_call_status_req_msg_v01, + wfc_call_status_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLFW_MAX_WFC_CALL_STATUS_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + wlfw_wfc_call_status_req_msg_v01, + wfc_call_status), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_wfc_call_status_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + wlfw_wfc_call_status_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + diff --git a/drivers/net/wireless/cnss2/wlan_firmware_service_v01.h b/drivers/net/wireless/cnss2/wlan_firmware_service_v01.h new file mode 100644 index 000000000000..dacdfdb2a471 --- /dev/null +++ b/drivers/net/wireless/cnss2/wlan_firmware_service_v01.h @@ -0,0 +1,952 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. */ + +#ifndef WLAN_FIRMWARE_SERVICE_V01_H +#define WLAN_FIRMWARE_SERVICE_V01_H + +#include + +#define WLFW_SERVICE_ID_V01 0x45 +#define WLFW_SERVICE_VERS_V01 0x01 + +#define QMI_WLFW_WFC_CALL_STATUS_REQ_V01 0x0049 +#define QMI_WLFW_BDF_DOWNLOAD_REQ_V01 0x0025 +#define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 +#define QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01 0x0044 +#define QMI_WLFW_INITIATE_CAL_UPDATE_IND_V01 0x002A +#define QMI_WLFW_CAL_DONE_IND_V01 0x003E +#define QMI_WLFW_WFC_CALL_STATUS_RESP_V01 0x0049 +#define QMI_WLFW_HOST_CAP_REQ_V01 0x0034 +#define QMI_WLFW_DYNAMIC_FEATURE_MASK_RESP_V01 0x003B +#define QMI_WLFW_M3_INFO_REQ_V01 0x003C +#define QMI_WLFW_CAP_REQ_V01 0x0024 +#define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038 +#define QMI_WLFW_ANTENNA_GRANT_RESP_V01 0x0048 +#define QMI_WLFW_CAL_REPORT_REQ_V01 0x0026 +#define QMI_WLFW_M3_INFO_RESP_V01 0x003C +#define QMI_WLFW_CAL_UPDATE_RESP_V01 0x0029 +#define QMI_WLFW_CAL_DOWNLOAD_RESP_V01 0x0027 +#define QMI_WLFW_XO_CAL_IND_V01 0x003D +#define QMI_WLFW_INI_RESP_V01 0x002F +#define QMI_WLFW_CAL_REPORT_RESP_V01 0x0026 +#define QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01 0x0040 +#define QMI_WLFW_ANTENNA_SWITCH_REQ_V01 0x0047 +#define QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01 0x003F +#define QMI_WLFW_SHUTDOWN_RESP_V01 0x0043 +#define QMI_WLFW_MAC_ADDR_RESP_V01 0x0033 +#define QMI_WLFW_INITIATE_CAL_DOWNLOAD_IND_V01 0x0028 +#define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 +#define QMI_WLFW_MSA_READY_IND_V01 0x002B +#define QMI_WLFW_ATHDIAG_WRITE_RESP_V01 0x0031 +#define QMI_WLFW_WLAN_MODE_REQ_V01 0x0022 +#define QMI_WLFW_IND_REGISTER_REQ_V01 0x0020 +#define QMI_WLFW_WLAN_CFG_RESP_V01 0x0023 +#define QMI_WLFW_QDSS_TRACE_MODE_REQ_V01 0x0045 +#define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 +#define QMI_WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_RESP_V01 0x0044 +#define QMI_WLFW_REJUVENATE_IND_V01 0x0039 +#define QMI_WLFW_DYNAMIC_FEATURE_MASK_REQ_V01 0x003B +#define QMI_WLFW_ATHDIAG_WRITE_REQ_V01 0x0031 +#define QMI_WLFW_WLAN_MODE_RESP_V01 0x0022 +#define QMI_WLFW_RESPOND_MEM_REQ_V01 0x0036 +#define QMI_WLFW_QDSS_TRACE_MODE_RESP_V01 0x0045 +#define QMI_WLFW_PIN_CONNECT_RESULT_IND_V01 0x002C +#define QMI_WLFW_FW_READY_IND_V01 0x0021 +#define QMI_WLFW_QDSS_TRACE_SAVE_IND_V01 0x0041 +#define QMI_WLFW_QDSS_TRACE_MEM_INFO_RESP_V01 0x0040 +#define QMI_WLFW_ANTENNA_GRANT_REQ_V01 0x0048 +#define QMI_WLFW_MSA_READY_RESP_V01 0x002E +#define QMI_WLFW_QDSS_TRACE_DATA_REQ_V01 0x0042 +#define QMI_WLFW_CAL_UPDATE_REQ_V01 0x0029 +#define QMI_WLFW_INI_REQ_V01 0x002F +#define QMI_WLFW_BDF_DOWNLOAD_RESP_V01 0x0025 +#define QMI_WLFW_REJUVENATE_ACK_RESP_V01 0x003A +#define QMI_WLFW_MSA_INFO_RESP_V01 0x002D +#define QMI_WLFW_MSA_READY_REQ_V01 0x002E +#define QMI_WLFW_QDSS_TRACE_DATA_RESP_V01 0x0042 +#define QMI_WLFW_CAP_RESP_V01 0x0024 +#define QMI_WLFW_REJUVENATE_ACK_REQ_V01 0x003A +#define QMI_WLFW_ATHDIAG_READ_RESP_V01 0x0030 +#define QMI_WLFW_SHUTDOWN_REQ_V01 0x0043 +#define QMI_WLFW_VBATT_REQ_V01 0x0032 +#define QMI_WLFW_ANTENNA_SWITCH_RESP_V01 0x0047 +#define QMI_WLFW_MAC_ADDR_REQ_V01 0x0033 +#define QMI_WLFW_RESPOND_MEM_RESP_V01 0x0036 +#define QMI_WLFW_VBATT_RESP_V01 0x0032 +#define QMI_WLFW_MSA_INFO_REQ_V01 0x002D +#define QMI_WLFW_QDSS_TRACE_FREE_IND_V01 0x0046 +#define QMI_WLFW_CAL_DOWNLOAD_REQ_V01 0x0027 +#define QMI_WLFW_ATHDIAG_READ_REQ_V01 0x0030 +#define QMI_WLFW_WLAN_CFG_REQ_V01 0x0023 +#define QMI_WLFW_IND_REGISTER_RESP_V01 0x0020 + +#define QMI_WLFW_MAX_NUM_MEMORY_REGIONS_V01 2 +#define QMI_WLFW_MAX_NUM_MEM_SEG_V01 32 +#define QMI_WLFW_MAX_NUM_CAL_V01 5 +#define QMI_WLFW_MAX_DATA_SIZE_V01 6144 +#define QMI_WLFW_FUNCTION_NAME_LEN_V01 128 +#define QMI_WLFW_MAX_NUM_CE_V01 12 +#define QMI_WLFW_MAX_TIMESTAMP_LEN_V01 32 +#define QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01 6144 +#define QMI_WLFW_MAX_WFC_CALL_STATUS_DATA_SIZE_V01 256 +#define QMI_WLFW_MAX_NUM_GPIO_V01 32 +#define QMI_WLFW_MAX_BUILD_ID_LEN_V01 128 +#define QMI_WLFW_MAX_NUM_MEM_CFG_V01 2 +#define QMI_WLFW_MAX_STR_LEN_V01 16 +#define QMI_WLFW_MAX_NUM_SHADOW_REG_V01 24 +#define QMI_WLFW_MAC_ADDR_SIZE_V01 6 +#define QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01 36 +#define QMI_WLFW_MAX_NUM_SVC_V01 24 + +enum wlfw_driver_mode_enum_v01 { + WLFW_DRIVER_MODE_ENUM_MIN_VAL_V01 = INT_MIN, + QMI_WLFW_MISSION_V01 = 0, + QMI_WLFW_FTM_V01 = 1, + QMI_WLFW_EPPING_V01 = 2, + QMI_WLFW_WALTEST_V01 = 3, + QMI_WLFW_OFF_V01 = 4, + QMI_WLFW_CCPM_V01 = 5, + QMI_WLFW_QVIT_V01 = 6, + QMI_WLFW_CALIBRATION_V01 = 7, + WLFW_DRIVER_MODE_ENUM_MAX_VAL_V01 = INT_MAX, +}; + +enum wlfw_cal_temp_id_enum_v01 { + WLFW_CAL_TEMP_ID_ENUM_MIN_VAL_V01 = INT_MIN, + QMI_WLFW_CAL_TEMP_IDX_0_V01 = 0, + QMI_WLFW_CAL_TEMP_IDX_1_V01 = 1, + QMI_WLFW_CAL_TEMP_IDX_2_V01 = 2, + QMI_WLFW_CAL_TEMP_IDX_3_V01 = 3, + QMI_WLFW_CAL_TEMP_IDX_4_V01 = 4, + WLFW_CAL_TEMP_ID_ENUM_MAX_VAL_V01 = INT_MAX, +}; + +enum wlfw_pipedir_enum_v01 { + WLFW_PIPEDIR_ENUM_MIN_VAL_V01 = INT_MIN, + QMI_WLFW_PIPEDIR_NONE_V01 = 0, + QMI_WLFW_PIPEDIR_IN_V01 = 1, + QMI_WLFW_PIPEDIR_OUT_V01 = 2, + QMI_WLFW_PIPEDIR_INOUT_V01 = 3, + WLFW_PIPEDIR_ENUM_MAX_VAL_V01 = INT_MAX, +}; + +enum wlfw_mem_type_enum_v01 { + WLFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, + QMI_WLFW_MEM_TYPE_MSA_V01 = 0, + QMI_WLFW_MEM_TYPE_DDR_V01 = 1, + QMI_WLFW_MEM_BDF_V01 = 2, + QMI_WLFW_MEM_M3_V01 = 3, + QMI_WLFW_MEM_CAL_V01 = 4, + QMI_WLFW_MEM_DPD_V01 = 5, + QMI_WLFW_MEM_QDSS_V01 = 6, + WLFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, +}; + +enum wlfw_qdss_trace_mode_enum_v01 { + WLFW_QDSS_TRACE_MODE_ENUM_MIN_VAL_V01 = INT_MIN, + QMI_WLFW_QDSS_TRACE_OFF_V01 = 0, + QMI_WLFW_QDSS_TRACE_ON_V01 = 1, + WLFW_QDSS_TRACE_MODE_ENUM_MAX_VAL_V01 = INT_MAX, +}; + +#define QMI_WLFW_CE_ATTR_FLAGS_V01 ((u32)0x00) +#define QMI_WLFW_CE_ATTR_NO_SNOOP_V01 ((u32)0x01) +#define QMI_WLFW_CE_ATTR_BYTE_SWAP_DATA_V01 ((u32)0x02) +#define QMI_WLFW_CE_ATTR_SWIZZLE_DESCRIPTORS_V01 ((u32)0x04) +#define QMI_WLFW_CE_ATTR_DISABLE_INTR_V01 ((u32)0x08) +#define QMI_WLFW_CE_ATTR_ENABLE_POLL_V01 ((u32)0x10) + +#define QMI_WLFW_ALREADY_REGISTERED_V01 ((u64)0x01ULL) +#define QMI_WLFW_FW_READY_V01 ((u64)0x02ULL) +#define QMI_WLFW_MSA_READY_V01 ((u64)0x04ULL) +#define QMI_WLFW_FW_MEM_READY_V01 ((u64)0x08ULL) +#define QMI_WLFW_FW_INIT_DONE_V01 ((u64)0x10ULL) + +#define QMI_WLFW_FW_REJUVENATE_V01 ((u64)0x01ULL) + +struct wlfw_ce_tgt_pipe_cfg_s_v01 { + u32 pipe_num; + enum wlfw_pipedir_enum_v01 pipe_dir; + u32 nentries; + u32 nbytes_max; + u32 flags; +}; + +struct wlfw_ce_svc_pipe_cfg_s_v01 { + u32 service_id; + enum wlfw_pipedir_enum_v01 pipe_dir; + u32 pipe_num; +}; + +struct wlfw_shadow_reg_cfg_s_v01 { + u16 id; + u16 offset; +}; + +struct wlfw_shadow_reg_v2_cfg_s_v01 { + u32 addr; +}; + +struct wlfw_rri_over_ddr_cfg_s_v01 { + u32 base_addr_low; + u32 base_addr_high; +}; + +struct wlfw_msi_cfg_s_v01 { + u16 ce_id; + u16 msi_vector; +}; + +struct wlfw_memory_region_info_s_v01 { + u64 region_addr; + u32 size; + u8 secure_flag; +}; + +struct wlfw_mem_cfg_s_v01 { + u64 offset; + u32 size; + u8 secure_flag; +}; + +struct wlfw_mem_seg_s_v01 { + u32 size; + enum wlfw_mem_type_enum_v01 type; + u32 mem_cfg_len; + struct wlfw_mem_cfg_s_v01 mem_cfg[QMI_WLFW_MAX_NUM_MEM_CFG_V01]; +}; + +struct wlfw_mem_seg_resp_s_v01 { + u64 addr; + u32 size; + enum wlfw_mem_type_enum_v01 type; + u8 restore; +}; + +struct wlfw_rf_chip_info_s_v01 { + u32 chip_id; + u32 chip_family; +}; + +struct wlfw_rf_board_info_s_v01 { + u32 board_id; +}; + +struct wlfw_soc_info_s_v01 { + u32 soc_id; +}; + +struct wlfw_fw_version_info_s_v01 { + u32 fw_version; + char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN_V01 + 1]; +}; + +struct wlfw_ind_register_req_msg_v01 { + u8 fw_ready_enable_valid; + u8 fw_ready_enable; + u8 initiate_cal_download_enable_valid; + u8 initiate_cal_download_enable; + u8 initiate_cal_update_enable_valid; + u8 initiate_cal_update_enable; + u8 msa_ready_enable_valid; + u8 msa_ready_enable; + u8 pin_connect_result_enable_valid; + u8 pin_connect_result_enable; + u8 client_id_valid; + u32 client_id; + u8 request_mem_enable_valid; + u8 request_mem_enable; + u8 fw_mem_ready_enable_valid; + u8 fw_mem_ready_enable; + u8 fw_init_done_enable_valid; + u8 fw_init_done_enable; + u8 rejuvenate_enable_valid; + u32 rejuvenate_enable; + u8 xo_cal_enable_valid; + u8 xo_cal_enable; + u8 cal_done_enable_valid; + u8 cal_done_enable; + u8 qdss_trace_req_mem_enable_valid; + u8 qdss_trace_req_mem_enable; + u8 qdss_trace_save_enable_valid; + u8 qdss_trace_save_enable; + u8 qdss_trace_free_enable_valid; + u8 qdss_trace_free_enable; +}; + +#define WLFW_IND_REGISTER_REQ_MSG_V01_MAX_MSG_LEN 66 +extern struct qmi_elem_info wlfw_ind_register_req_msg_v01_ei[]; + +struct wlfw_ind_register_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 fw_status_valid; + u64 fw_status; +}; + +#define WLFW_IND_REGISTER_RESP_MSG_V01_MAX_MSG_LEN 18 +extern struct qmi_elem_info wlfw_ind_register_resp_msg_v01_ei[]; + +struct wlfw_fw_ready_ind_msg_v01 { + char placeholder; +}; + +#define WLFW_FW_READY_IND_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_fw_ready_ind_msg_v01_ei[]; + +struct wlfw_msa_ready_ind_msg_v01 { + char placeholder; +}; + +#define WLFW_MSA_READY_IND_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_msa_ready_ind_msg_v01_ei[]; + +struct wlfw_pin_connect_result_ind_msg_v01 { + u8 pwr_pin_result_valid; + u32 pwr_pin_result; + u8 phy_io_pin_result_valid; + u32 phy_io_pin_result; + u8 rf_pin_result_valid; + u32 rf_pin_result; +}; + +#define WLFW_PIN_CONNECT_RESULT_IND_MSG_V01_MAX_MSG_LEN 21 +extern struct qmi_elem_info wlfw_pin_connect_result_ind_msg_v01_ei[]; + +struct wlfw_wlan_mode_req_msg_v01 { + enum wlfw_driver_mode_enum_v01 mode; + u8 hw_debug_valid; + u8 hw_debug; +}; + +#define WLFW_WLAN_MODE_REQ_MSG_V01_MAX_MSG_LEN 11 +extern struct qmi_elem_info wlfw_wlan_mode_req_msg_v01_ei[]; + +struct wlfw_wlan_mode_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_WLAN_MODE_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_wlan_mode_resp_msg_v01_ei[]; + +struct wlfw_wlan_cfg_req_msg_v01 { + u8 host_version_valid; + char host_version[QMI_WLFW_MAX_STR_LEN_V01 + 1]; + u8 tgt_cfg_valid; + u32 tgt_cfg_len; + struct wlfw_ce_tgt_pipe_cfg_s_v01 tgt_cfg[QMI_WLFW_MAX_NUM_CE_V01]; + u8 svc_cfg_valid; + u32 svc_cfg_len; + struct wlfw_ce_svc_pipe_cfg_s_v01 svc_cfg[QMI_WLFW_MAX_NUM_SVC_V01]; + u8 shadow_reg_valid; + u32 shadow_reg_len; + struct wlfw_shadow_reg_cfg_s_v01 + shadow_reg[QMI_WLFW_MAX_NUM_SHADOW_REG_V01]; + u8 shadow_reg_v2_valid; + u32 shadow_reg_v2_len; + struct wlfw_shadow_reg_v2_cfg_s_v01 + shadow_reg_v2[QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01]; + u8 rri_over_ddr_cfg_valid; + struct wlfw_rri_over_ddr_cfg_s_v01 rri_over_ddr_cfg; + u8 msi_cfg_valid; + u32 msi_cfg_len; + struct wlfw_msi_cfg_s_v01 msi_cfg[QMI_WLFW_MAX_NUM_CE_V01]; +}; + +#define WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN 866 +extern struct qmi_elem_info wlfw_wlan_cfg_req_msg_v01_ei[]; + +struct wlfw_wlan_cfg_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_WLAN_CFG_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_wlan_cfg_resp_msg_v01_ei[]; + +struct wlfw_cap_req_msg_v01 { + char placeholder; +}; + +#define WLFW_CAP_REQ_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_cap_req_msg_v01_ei[]; + +struct wlfw_cap_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 chip_info_valid; + struct wlfw_rf_chip_info_s_v01 chip_info; + u8 board_info_valid; + struct wlfw_rf_board_info_s_v01 board_info; + u8 soc_info_valid; + struct wlfw_soc_info_s_v01 soc_info; + u8 fw_version_info_valid; + struct wlfw_fw_version_info_s_v01 fw_version_info; + u8 fw_build_id_valid; + char fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN_V01 + 1]; + u8 num_macs_valid; + u8 num_macs; + u8 voltage_mv_valid; + u32 voltage_mv; + u8 time_freq_hz_valid; + u32 time_freq_hz; + u8 otp_version_valid; + u32 otp_version; +}; + +#define WLFW_CAP_RESP_MSG_V01_MAX_MSG_LEN 228 +extern struct qmi_elem_info wlfw_cap_resp_msg_v01_ei[]; + +struct wlfw_bdf_download_req_msg_v01 { + u8 valid; + u8 file_id_valid; + enum wlfw_cal_temp_id_enum_v01 file_id; + u8 total_size_valid; + u32 total_size; + u8 seg_id_valid; + u32 seg_id; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; + u8 end_valid; + u8 end; + u8 bdf_type_valid; + u8 bdf_type; +}; + +#define WLFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6182 +extern struct qmi_elem_info wlfw_bdf_download_req_msg_v01_ei[]; + +struct wlfw_bdf_download_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_bdf_download_resp_msg_v01_ei[]; + +struct wlfw_cal_report_req_msg_v01 { + u32 meta_data_len; + enum wlfw_cal_temp_id_enum_v01 meta_data[QMI_WLFW_MAX_NUM_CAL_V01]; + u8 xo_cal_data_valid; + u8 xo_cal_data; +}; + +#define WLFW_CAL_REPORT_REQ_MSG_V01_MAX_MSG_LEN 28 +extern struct qmi_elem_info wlfw_cal_report_req_msg_v01_ei[]; + +struct wlfw_cal_report_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_CAL_REPORT_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_cal_report_resp_msg_v01_ei[]; + +struct wlfw_initiate_cal_download_ind_msg_v01 { + enum wlfw_cal_temp_id_enum_v01 cal_id; + u8 total_size_valid; + u32 total_size; + u8 cal_data_location_valid; + u32 cal_data_location; +}; + +#define WLFW_INITIATE_CAL_DOWNLOAD_IND_MSG_V01_MAX_MSG_LEN 21 +extern struct qmi_elem_info wlfw_initiate_cal_download_ind_msg_v01_ei[]; + +struct wlfw_cal_download_req_msg_v01 { + u8 valid; + u8 file_id_valid; + enum wlfw_cal_temp_id_enum_v01 file_id; + u8 total_size_valid; + u32 total_size; + u8 seg_id_valid; + u32 seg_id; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; + u8 end_valid; + u8 end; + u8 cal_data_location_valid; + u32 cal_data_location; +}; + +#define WLFW_CAL_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6185 +extern struct qmi_elem_info wlfw_cal_download_req_msg_v01_ei[]; + +struct wlfw_cal_download_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_CAL_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_cal_download_resp_msg_v01_ei[]; + +struct wlfw_initiate_cal_update_ind_msg_v01 { + enum wlfw_cal_temp_id_enum_v01 cal_id; + u32 total_size; + u8 cal_data_location_valid; + u32 cal_data_location; +}; + +#define WLFW_INITIATE_CAL_UPDATE_IND_MSG_V01_MAX_MSG_LEN 21 +extern struct qmi_elem_info wlfw_initiate_cal_update_ind_msg_v01_ei[]; + +struct wlfw_cal_update_req_msg_v01 { + enum wlfw_cal_temp_id_enum_v01 cal_id; + u32 seg_id; +}; + +#define WLFW_CAL_UPDATE_REQ_MSG_V01_MAX_MSG_LEN 14 +extern struct qmi_elem_info wlfw_cal_update_req_msg_v01_ei[]; + +struct wlfw_cal_update_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 file_id_valid; + enum wlfw_cal_temp_id_enum_v01 file_id; + u8 total_size_valid; + u32 total_size; + u8 seg_id_valid; + u32 seg_id; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; + u8 end_valid; + u8 end; + u8 cal_data_location_valid; + u32 cal_data_location; +}; + +#define WLFW_CAL_UPDATE_RESP_MSG_V01_MAX_MSG_LEN 6188 +extern struct qmi_elem_info wlfw_cal_update_resp_msg_v01_ei[]; + +struct wlfw_msa_info_req_msg_v01 { + u64 msa_addr; + u32 size; +}; + +#define WLFW_MSA_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 +extern struct qmi_elem_info wlfw_msa_info_req_msg_v01_ei[]; + +struct wlfw_msa_info_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u32 mem_region_info_len; + struct wlfw_memory_region_info_s_v01 + mem_region_info[QMI_WLFW_MAX_NUM_MEMORY_REGIONS_V01]; +}; + +#define WLFW_MSA_INFO_RESP_MSG_V01_MAX_MSG_LEN 37 +extern struct qmi_elem_info wlfw_msa_info_resp_msg_v01_ei[]; + +struct wlfw_msa_ready_req_msg_v01 { + char placeholder; +}; + +#define WLFW_MSA_READY_REQ_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_msa_ready_req_msg_v01_ei[]; + +struct wlfw_msa_ready_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_MSA_READY_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_msa_ready_resp_msg_v01_ei[]; + +struct wlfw_ini_req_msg_v01 { + u8 enablefwlog_valid; + u8 enablefwlog; +}; + +#define WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN 4 +extern struct qmi_elem_info wlfw_ini_req_msg_v01_ei[]; + +struct wlfw_ini_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_INI_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_ini_resp_msg_v01_ei[]; + +struct wlfw_athdiag_read_req_msg_v01 { + u32 offset; + u32 mem_type; + u32 data_len; +}; + +#define WLFW_ATHDIAG_READ_REQ_MSG_V01_MAX_MSG_LEN 21 +extern struct qmi_elem_info wlfw_athdiag_read_req_msg_v01_ei[]; + +struct wlfw_athdiag_read_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01]; +}; + +#define WLFW_ATHDIAG_READ_RESP_MSG_V01_MAX_MSG_LEN 6156 +extern struct qmi_elem_info wlfw_athdiag_read_resp_msg_v01_ei[]; + +struct wlfw_athdiag_write_req_msg_v01 { + u32 offset; + u32 mem_type; + u32 data_len; + u8 data[QMI_WLFW_MAX_ATHDIAG_DATA_SIZE_V01]; +}; + +#define WLFW_ATHDIAG_WRITE_REQ_MSG_V01_MAX_MSG_LEN 6163 +extern struct qmi_elem_info wlfw_athdiag_write_req_msg_v01_ei[]; + +struct wlfw_athdiag_write_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_ATHDIAG_WRITE_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_athdiag_write_resp_msg_v01_ei[]; + +struct wlfw_vbatt_req_msg_v01 { + u64 voltage_uv; +}; + +#define WLFW_VBATT_REQ_MSG_V01_MAX_MSG_LEN 11 +extern struct qmi_elem_info wlfw_vbatt_req_msg_v01_ei[]; + +struct wlfw_vbatt_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_VBATT_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_vbatt_resp_msg_v01_ei[]; + +struct wlfw_mac_addr_req_msg_v01 { + u8 mac_addr_valid; + u8 mac_addr[QMI_WLFW_MAC_ADDR_SIZE_V01]; +}; + +#define WLFW_MAC_ADDR_REQ_MSG_V01_MAX_MSG_LEN 9 +extern struct qmi_elem_info wlfw_mac_addr_req_msg_v01_ei[]; + +struct wlfw_mac_addr_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_MAC_ADDR_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_mac_addr_resp_msg_v01_ei[]; + +struct wlfw_host_cap_req_msg_v01 { + u8 num_clients_valid; + u32 num_clients; + u8 wake_msi_valid; + u32 wake_msi; + u8 gpios_valid; + u32 gpios_len; + u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; + u8 nm_modem_valid; + u8 nm_modem; + u8 bdf_support_valid; + u8 bdf_support; + u8 bdf_cache_support_valid; + u8 bdf_cache_support; + u8 m3_support_valid; + u8 m3_support; + u8 m3_cache_support_valid; + u8 m3_cache_support; + u8 cal_filesys_support_valid; + u8 cal_filesys_support; + u8 cal_cache_support_valid; + u8 cal_cache_support; + u8 cal_done_valid; + u8 cal_done; + u8 mem_bucket_valid; + u32 mem_bucket; + u8 mem_cfg_mode_valid; + u8 mem_cfg_mode; + u8 cal_duration_valid; + u16 cal_duration; +}; + +#define WLFW_HOST_CAP_REQ_MSG_V01_MAX_MSG_LEN 194 +extern struct qmi_elem_info wlfw_host_cap_req_msg_v01_ei[]; + +struct wlfw_host_cap_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_HOST_CAP_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_host_cap_resp_msg_v01_ei[]; + +struct wlfw_request_mem_ind_msg_v01 { + u32 mem_seg_len; + struct wlfw_mem_seg_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; +}; + +#define WLFW_REQUEST_MEM_IND_MSG_V01_MAX_MSG_LEN 1124 +extern struct qmi_elem_info wlfw_request_mem_ind_msg_v01_ei[]; + +struct wlfw_respond_mem_req_msg_v01 { + u32 mem_seg_len; + struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; +}; + +#define WLFW_RESPOND_MEM_REQ_MSG_V01_MAX_MSG_LEN 548 +extern struct qmi_elem_info wlfw_respond_mem_req_msg_v01_ei[]; + +struct wlfw_respond_mem_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_RESPOND_MEM_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_respond_mem_resp_msg_v01_ei[]; + +struct wlfw_fw_mem_ready_ind_msg_v01 { + char placeholder; +}; + +#define WLFW_FW_MEM_READY_IND_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_fw_mem_ready_ind_msg_v01_ei[]; + +struct wlfw_fw_init_done_ind_msg_v01 { + char placeholder; +}; + +#define WLFW_FW_INIT_DONE_IND_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_fw_init_done_ind_msg_v01_ei[]; + +struct wlfw_rejuvenate_ind_msg_v01 { + u8 cause_for_rejuvenation_valid; + u8 cause_for_rejuvenation; + u8 requesting_sub_system_valid; + u8 requesting_sub_system; + u8 line_number_valid; + u16 line_number; + u8 function_name_valid; + char function_name[QMI_WLFW_FUNCTION_NAME_LEN_V01 + 1]; +}; + +#define WLFW_REJUVENATE_IND_MSG_V01_MAX_MSG_LEN 144 +extern struct qmi_elem_info wlfw_rejuvenate_ind_msg_v01_ei[]; + +struct wlfw_rejuvenate_ack_req_msg_v01 { + char placeholder; +}; + +#define WLFW_REJUVENATE_ACK_REQ_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_rejuvenate_ack_req_msg_v01_ei[]; + +struct wlfw_rejuvenate_ack_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_REJUVENATE_ACK_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_rejuvenate_ack_resp_msg_v01_ei[]; + +struct wlfw_dynamic_feature_mask_req_msg_v01 { + u8 mask_valid; + u64 mask; +}; + +#define WLFW_DYNAMIC_FEATURE_MASK_REQ_MSG_V01_MAX_MSG_LEN 11 +extern struct qmi_elem_info wlfw_dynamic_feature_mask_req_msg_v01_ei[]; + +struct wlfw_dynamic_feature_mask_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 prev_mask_valid; + u64 prev_mask; + u8 curr_mask_valid; + u64 curr_mask; +}; + +#define WLFW_DYNAMIC_FEATURE_MASK_RESP_MSG_V01_MAX_MSG_LEN 29 +extern struct qmi_elem_info wlfw_dynamic_feature_mask_resp_msg_v01_ei[]; + +struct wlfw_m3_info_req_msg_v01 { + u64 addr; + u32 size; +}; + +#define WLFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 +extern struct qmi_elem_info wlfw_m3_info_req_msg_v01_ei[]; + +struct wlfw_m3_info_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_m3_info_resp_msg_v01_ei[]; + +struct wlfw_xo_cal_ind_msg_v01 { + u8 xo_cal_data; +}; + +#define WLFW_XO_CAL_IND_MSG_V01_MAX_MSG_LEN 4 +extern struct qmi_elem_info wlfw_xo_cal_ind_msg_v01_ei[]; + +struct wlfw_cal_done_ind_msg_v01 { + char placeholder; +}; + +#define WLFW_CAL_DONE_IND_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_cal_done_ind_msg_v01_ei[]; + +struct wlfw_qdss_trace_req_mem_ind_msg_v01 { + u32 mem_seg_len; + struct wlfw_mem_seg_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; +}; + +#define WLFW_QDSS_TRACE_REQ_MEM_IND_MSG_V01_MAX_MSG_LEN 1124 +extern struct qmi_elem_info wlfw_qdss_trace_req_mem_ind_msg_v01_ei[]; + +struct wlfw_qdss_trace_mem_info_req_msg_v01 { + u32 mem_seg_len; + struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; +}; + +#define WLFW_QDSS_TRACE_MEM_INFO_REQ_MSG_V01_MAX_MSG_LEN 548 +extern struct qmi_elem_info wlfw_qdss_trace_mem_info_req_msg_v01_ei[]; + +struct wlfw_qdss_trace_mem_info_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_QDSS_TRACE_MEM_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_qdss_trace_mem_info_resp_msg_v01_ei[]; + +struct wlfw_qdss_trace_save_ind_msg_v01 { + u32 source; + u32 total_size; + u8 mem_seg_valid; + u32 mem_seg_len; + struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; + u8 file_name_valid; + char file_name[QMI_WLFW_MAX_STR_LEN_V01 + 1]; +}; + +#define WLFW_QDSS_TRACE_SAVE_IND_MSG_V01_MAX_MSG_LEN 581 +extern struct qmi_elem_info wlfw_qdss_trace_save_ind_msg_v01_ei[]; + +struct wlfw_qdss_trace_data_req_msg_v01 { + u32 seg_id; +}; + +#define WLFW_QDSS_TRACE_DATA_REQ_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_qdss_trace_data_req_msg_v01_ei[]; + +struct wlfw_qdss_trace_data_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 total_size_valid; + u32 total_size; + u8 seg_id_valid; + u32 seg_id; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; + u8 end_valid; + u8 end; +}; + +#define WLFW_QDSS_TRACE_DATA_RESP_MSG_V01_MAX_MSG_LEN 6174 +extern struct qmi_elem_info wlfw_qdss_trace_data_resp_msg_v01_ei[]; + +struct wlfw_qdss_trace_config_download_req_msg_v01 { + u8 total_size_valid; + u32 total_size; + u8 seg_id_valid; + u32 seg_id; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLFW_MAX_DATA_SIZE_V01]; + u8 end_valid; + u8 end; +}; + +#define WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6167 +extern struct qmi_elem_info wlfw_qdss_trace_config_download_req_msg_v01_ei[]; + +struct wlfw_qdss_trace_config_download_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_QDSS_TRACE_CONFIG_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_qdss_trace_config_download_resp_msg_v01_ei[]; + +struct wlfw_qdss_trace_mode_req_msg_v01 { + u8 mode_valid; + enum wlfw_qdss_trace_mode_enum_v01 mode; + u8 option_valid; + u64 option; +}; + +#define WLFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_MSG_LEN 18 +extern struct qmi_elem_info wlfw_qdss_trace_mode_req_msg_v01_ei[]; + +struct wlfw_qdss_trace_mode_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_QDSS_TRACE_MODE_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_qdss_trace_mode_resp_msg_v01_ei[]; + +struct wlfw_qdss_trace_free_ind_msg_v01 { + u8 mem_seg_valid; + u32 mem_seg_len; + struct wlfw_mem_seg_resp_s_v01 mem_seg[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; +}; + +#define WLFW_QDSS_TRACE_FREE_IND_MSG_V01_MAX_MSG_LEN 548 +extern struct qmi_elem_info wlfw_qdss_trace_free_ind_msg_v01_ei[]; + +struct wlfw_shutdown_req_msg_v01 { + u8 shutdown_valid; + u8 shutdown; +}; + +#define WLFW_SHUTDOWN_REQ_MSG_V01_MAX_MSG_LEN 4 +extern struct qmi_elem_info wlfw_shutdown_req_msg_v01_ei[]; + +struct wlfw_shutdown_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_SHUTDOWN_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_shutdown_resp_msg_v01_ei[]; + +struct wlfw_antenna_switch_req_msg_v01 { + char placeholder; +}; + +#define WLFW_ANTENNA_SWITCH_REQ_MSG_V01_MAX_MSG_LEN 0 +extern struct qmi_elem_info wlfw_antenna_switch_req_msg_v01_ei[]; + +struct wlfw_antenna_switch_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 antenna_valid; + u64 antenna; +}; + +#define WLFW_ANTENNA_SWITCH_RESP_MSG_V01_MAX_MSG_LEN 18 +extern struct qmi_elem_info wlfw_antenna_switch_resp_msg_v01_ei[]; + +struct wlfw_antenna_grant_req_msg_v01 { + u8 grant_valid; + u64 grant; +}; + +#define WLFW_ANTENNA_GRANT_REQ_MSG_V01_MAX_MSG_LEN 11 +extern struct qmi_elem_info wlfw_antenna_grant_req_msg_v01_ei[]; + +struct wlfw_antenna_grant_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_ANTENNA_GRANT_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_antenna_grant_resp_msg_v01_ei[]; + +struct wlfw_wfc_call_status_req_msg_v01 { + u32 wfc_call_status_len; + u8 wfc_call_status[QMI_WLFW_MAX_WFC_CALL_STATUS_DATA_SIZE_V01]; +}; + +#define WLFW_WFC_CALL_STATUS_REQ_MSG_V01_MAX_MSG_LEN 261 +extern struct qmi_elem_info wlfw_wfc_call_status_req_msg_v01_ei[]; + +struct wlfw_wfc_call_status_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define WLFW_WFC_CALL_STATUS_RESP_MSG_V01_MAX_MSG_LEN 7 +extern struct qmi_elem_info wlfw_wfc_call_status_resp_msg_v01_ei[]; + +#endif diff --git a/include/net/cnss2.h b/include/net/cnss2.h new file mode 100644 index 000000000000..892096b85993 --- /dev/null +++ b/include/net/cnss2.h @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ + +#ifndef _NET_CNSS2_H +#define _NET_CNSS2_H + +#include + +#define CNSS_MAX_FILE_NAME 20 +#define CNSS_MAX_TIMESTAMP_LEN 32 + +/* + * Temporary change for compilation, will be removed + * after WLAN host driver switched to use new APIs + */ +#define CNSS_API_WITH_DEV + +enum cnss_bus_width_type { + CNSS_BUS_WIDTH_NONE, + CNSS_BUS_WIDTH_IDLE, + CNSS_BUS_WIDTH_LOW, + CNSS_BUS_WIDTH_MEDIUM, + CNSS_BUS_WIDTH_HIGH, + CNSS_BUS_WIDTH_VERY_HIGH +}; + +enum cnss_platform_cap_flag { + CNSS_HAS_EXTERNAL_SWREG = 0x01, + CNSS_HAS_UART_ACCESS = 0x02, +}; + +struct cnss_platform_cap { + u32 cap_flag; +}; + +struct cnss_fw_files { + char image_file[CNSS_MAX_FILE_NAME]; + char board_data[CNSS_MAX_FILE_NAME]; + char otp_data[CNSS_MAX_FILE_NAME]; + char utf_file[CNSS_MAX_FILE_NAME]; + char utf_board_data[CNSS_MAX_FILE_NAME]; + char epping_file[CNSS_MAX_FILE_NAME]; + char evicted_data[CNSS_MAX_FILE_NAME]; +}; + +struct cnss_device_version { + u32 family_number; + u32 device_number; + u32 major_version; + u32 minor_version; +}; + +struct cnss_soc_info { + void __iomem *va; + phys_addr_t pa; + uint32_t chip_id; + uint32_t chip_family; + uint32_t board_id; + uint32_t soc_id; + uint32_t fw_version; + char fw_build_timestamp[CNSS_MAX_TIMESTAMP_LEN + 1]; + struct cnss_device_version device_version; +}; + +struct cnss_wlan_runtime_ops { + int (*runtime_suspend)(struct pci_dev *pdev); + int (*runtime_resume)(struct pci_dev *pdev); +}; + +struct cnss_wlan_driver { + char *name; + int (*probe)(struct pci_dev *pdev, const struct pci_device_id *id); + void (*remove)(struct pci_dev *pdev); + int (*idle_restart)(struct pci_dev *pdev, + const struct pci_device_id *id); + int (*idle_shutdown)(struct pci_dev *pdev); + int (*reinit)(struct pci_dev *pdev, const struct pci_device_id *id); + void (*shutdown)(struct pci_dev *pdev); + void (*crash_shutdown)(struct pci_dev *pdev); + int (*suspend)(struct pci_dev *pdev, pm_message_t state); + int (*resume)(struct pci_dev *pdev); + int (*suspend_noirq)(struct pci_dev *pdev); + int (*resume_noirq)(struct pci_dev *pdev); + void (*modem_status)(struct pci_dev *pdev, int state); + void (*update_status)(struct pci_dev *pdev, uint32_t status); + struct cnss_wlan_runtime_ops *runtime_ops; + const struct pci_device_id *id_table; +}; + +enum cnss_driver_status { + CNSS_UNINITIALIZED, + CNSS_INITIALIZED, + CNSS_LOAD_UNLOAD, + CNSS_RECOVERY, + CNSS_FW_DOWN, +}; + +struct cnss_ce_tgt_pipe_cfg { + u32 pipe_num; + u32 pipe_dir; + u32 nentries; + u32 nbytes_max; + u32 flags; + u32 reserved; +}; + +struct cnss_ce_svc_pipe_cfg { + u32 service_id; + u32 pipe_dir; + u32 pipe_num; +}; + +struct cnss_shadow_reg_cfg { + u16 ce_id; + u16 reg_offset; +}; + +struct cnss_shadow_reg_v2_cfg { + u32 addr; +}; + +struct cnss_rri_over_ddr_cfg { + u32 base_addr_low; + u32 base_addr_high; +}; + +struct cnss_wlan_enable_cfg { + u32 num_ce_tgt_cfg; + struct cnss_ce_tgt_pipe_cfg *ce_tgt_cfg; + u32 num_ce_svc_pipe_cfg; + struct cnss_ce_svc_pipe_cfg *ce_svc_cfg; + u32 num_shadow_reg_cfg; + struct cnss_shadow_reg_cfg *shadow_reg_cfg; + u32 num_shadow_reg_v2_cfg; + struct cnss_shadow_reg_v2_cfg *shadow_reg_v2_cfg; + bool rri_over_ddr_cfg_valid; + struct cnss_rri_over_ddr_cfg rri_over_ddr_cfg; +}; + +enum cnss_driver_mode { + CNSS_MISSION, + CNSS_FTM, + CNSS_EPPING, + CNSS_WALTEST, + CNSS_OFF, + CNSS_CCPM, + CNSS_QVIT, + CNSS_CALIBRATION, +}; + +enum cnss_recovery_reason { + CNSS_REASON_DEFAULT, + CNSS_REASON_LINK_DOWN, + CNSS_REASON_RDDM, + CNSS_REASON_TIMEOUT, +}; + +extern int cnss_wlan_register_driver(struct cnss_wlan_driver *driver); +extern void cnss_wlan_unregister_driver(struct cnss_wlan_driver *driver); +extern void cnss_device_crashed(struct device *dev); +extern int cnss_pci_link_down(struct device *dev); +extern int cnss_pci_is_device_down(struct device *dev); +extern void cnss_schedule_recovery(struct device *dev, + enum cnss_recovery_reason reason); +extern int cnss_self_recovery(struct device *dev, + enum cnss_recovery_reason reason); +extern int cnss_force_fw_assert(struct device *dev); +extern int cnss_force_collect_rddm(struct device *dev); +extern void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size); +extern int cnss_get_fw_files_for_target(struct device *dev, + struct cnss_fw_files *pfw_files, + u32 target_type, u32 target_version); +extern int cnss_get_platform_cap(struct device *dev, + struct cnss_platform_cap *cap); +extern struct iommu_domain *cnss_smmu_get_domain(struct device *dev); +extern int cnss_smmu_map(struct device *dev, + phys_addr_t paddr, uint32_t *iova_addr, size_t size); +extern int cnss_get_soc_info(struct device *dev, struct cnss_soc_info *info); +extern int cnss_request_bus_bandwidth(struct device *dev, int bandwidth); +extern int cnss_power_up(struct device *dev); +extern int cnss_power_down(struct device *dev); +extern int cnss_idle_restart(struct device *dev); +extern int cnss_idle_shutdown(struct device *dev); +extern void cnss_request_pm_qos(struct device *dev, u32 qos_val); +extern void cnss_remove_pm_qos(struct device *dev); +extern void cnss_lock_pm_sem(struct device *dev); +extern void cnss_release_pm_sem(struct device *dev); +extern int cnss_wlan_pm_control(struct device *dev, bool vote); +extern int cnss_auto_suspend(struct device *dev); +extern int cnss_auto_resume(struct device *dev); +extern int cnss_pci_is_drv_connected(struct device *dev); +extern int cnss_pci_force_wake_request(struct device *dev); +extern int cnss_pci_is_device_awake(struct device *dev); +extern int cnss_pci_force_wake_release(struct device *dev); +extern int cnss_get_user_msi_assignment(struct device *dev, char *user_name, + int *num_vectors, + uint32_t *user_base_data, + uint32_t *base_vector); +extern int cnss_get_msi_irq(struct device *dev, unsigned int vector); +extern void cnss_get_msi_address(struct device *dev, uint32_t *msi_addr_low, + uint32_t *msi_addr_high); +extern int cnss_wlan_enable(struct device *dev, + struct cnss_wlan_enable_cfg *config, + enum cnss_driver_mode mode, + const char *host_version); +extern int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode); +extern unsigned int cnss_get_boot_timeout(struct device *dev); +extern int cnss_athdiag_read(struct device *dev, uint32_t offset, + uint32_t mem_type, uint32_t data_len, + uint8_t *output); +extern int cnss_athdiag_write(struct device *dev, uint32_t offset, + uint32_t mem_type, uint32_t data_len, + uint8_t *input); +extern int cnss_set_fw_log_mode(struct device *dev, uint8_t fw_log_mode); + +#endif /* _NET_CNSS2_H */