From bef68d7d306fca25ba956e20d8afbf26bd63dfb6 Mon Sep 17 00:00:00 2001 From: Yimin Peng Date: Tue, 5 Jan 2021 16:45:01 +0800 Subject: [PATCH] clk: qcom: Add 2nd UFS virtio clocks for sa8195p These virtio clocks are necessary for 2nd UFS pass-through on sa8195p virtual machine. Change-Id: Ic117eab58eaaf1ef9e91311a17e6e59eebf0200b Signed-off-by: Yimin Peng --- drivers/clk/qcom/virtio_clk_sa8195p.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/virtio_clk_sa8195p.c b/drivers/clk/qcom/virtio_clk_sa8195p.c index 08069594c424..b1010e99fc2f 100644 --- a/drivers/clk/qcom/virtio_clk_sa8195p.c +++ b/drivers/clk/qcom/virtio_clk_sa8195p.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #include @@ -90,6 +90,16 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { [GCC_SDCC2_AHB_CLK] = "gcc_sdcc2_ahb_clk", [GCC_SDCC2_APPS_CLK] = "gcc_sdcc2_apps_clk", [GCC_PRNG_AHB_CLK] = "gcc_prng_ahb_clk", + [GCC_UFS_PHY_ICE_CORE_CLK] = "gcc_ufs_phy_ice_core_clk", + [GCC_UFS_CARD_2_AHB_CLK] = "gcc_ufs_card_2_ahb_clk", + [GCC_UFS_CARD_2_ICE_CORE_CLK] = "gcc_ufs_card_2_ice_core_clk", + [GCC_UFS_CARD_2_PHY_AUX_CLK] = "gcc_ufs_card_2_phy_aux_clk", + [GCC_UFS_CARD_2_AXI_CLK] = "gcc_ufs_card_2_axi_clk", + [GCC_AGGRE_UFS_CARD_2_AXI_CLK] = "gcc_aggre_ufs_card_2_axi_clk", + [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = "gcc_ufs_card_2_unipro_core_clk", + [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = "gcc_ufs_card_2_tx_symbol_0_clk", + [GCC_UFS_CARD_2_RX_SYMBOL_0_CLK] = "gcc_ufs_card_2_rx_symbol_0_clk", + [GCC_UFS_CARD_2_RX_SYMBOL_1_CLK] = "gcc_ufs_card_2_rx_symbol_1_clk", }; static const char * const sa8195p_gcc_virtio_resets[] = { @@ -105,6 +115,7 @@ static const char * const sa8195p_gcc_virtio_resets[] = { [GCC_PCIE_2_PHY_BCR] = "gcc_pcie_2_phy_bcr", [GCC_PCIE_3_BCR] = "gcc_pcie_3_mstr_axi_clk", [GCC_PCIE_3_PHY_BCR] = "gcc_pcie_3_phy_bcr", + [GCC_UFS_CARD_2_BCR] = "gcc_ufs_card_2_axi_clk", }; const struct clk_virtio_desc clk_virtio_sa8195p_gcc = {