From 8f72d44655b30a2c2d2db59bd295a25ae0eceead Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Tue, 8 Dec 2020 15:41:40 +0530 Subject: [PATCH] msm: kgsl: Dump PWR_COL_PREEMPT_KEEPALIVE on wait for lowest idle timeout On A660 GPU, PWR_COL_PREEMPT_KEEPALIVE register is used to disallow ifpc during preemption trigger. Dump this register also in case of wait for lowest idle timeout to capture this ifpc abort reason. Change-Id: Ide6bef3169987f17ec6a761e9735caef1c5deaa7 Signed-off-by: Deepak Kumar --- drivers/gpu/msm/adreno_a6xx_gmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index f90d7f2d51e6..69877654c764 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -1164,6 +1164,13 @@ int a6xx_gmu_wait_for_lowest_idle(struct adreno_device *adreno_dev) reg3, reg4); dev_err(&gmu->pdev->dev, "A6XX_GMU_AO_SPARE_CNTL=%x\n", reg5); + if (adreno_is_a660(adreno_dev)) { + u32 val; + + gmu_core_regread(device, A6XX_GMU_PWR_COL_PREEMPT_KEEPALIVE, &val); + dev_err(&gmu->pdev->dev, "PWR_COL_PREEMPT_KEEPALIVE=%x\n", val); + } + /* Access GX registers only when GX is ON */ if (is_on(reg1)) { kgsl_regread(device, A6XX_CP_STATUS_1, ®6);