A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-28 02:32:09 -04:00
Code Issues Projects Releases Packages Wiki Activity

cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SoCs

Browse source 
According to the data provided by HW Team, at least 12 internal platform
clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs.
This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition
latency to make DFS governors work normally on Freescale e500mc boards.

Signed-off-by: Zhuoyu Zhang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
This commit is contained in:
Zhuoyu Zhang 2014-03-18 13:41:25 +08:00 • committed by Rafael J. Wysocki
commit bfa709bc82
1 changed files with 3 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
drivers/cpufreq/ppc-corenet-cpufreq.c
View file

@ -21,6 +21,7 @@
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/smp.h>
#include <sysdev/fsl_soc.h>
/**
* struct cpu_data - per CPU data struct
@ -205,7 +206,8 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
for_each_cpu(i, per_cpu(cpu_mask, cpu))
per_cpu(cpu_data, i) = data;
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
policy->cpuinfo.transition_latency =
(12 * NSEC_PER_SEC) / fsl_get_sys_freq();
of_node_put(np);
return 0;