mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 14:13:01 -04:00
Merge branch 'orion' into devel
* orion: (26 commits) [ARM] Orion: implement power-off method for QNAP TS-109/209 [ARM] Orion: add support for QNAP TS-109/TS-209 [ARM] Orion: I2C support [I2C] i2c-mv64xxx: Don't set i2c_adapter.retries [I2C] Split mv643xx I2C platform support [ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323 [ARM] Orion defconfig [ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323 [ARM] Orion: MV88F5181 support bits [ARM] Orion: Buffalo/Revogear Kurobox Pro support [ARM] OrionNAS RD board support [ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board [ARM] Orion: common platform setup for Gigabit Ethernet port [ARM] Orion: platform device registration for UART, USB and NAND [ARM] Orion: system timer support [ARM] Orion edge GPIO IRQ support [ARM] Orion: IRQ support [ARM] Orion: provide GPIO method for enabling hardware assisted blinking [ARM] Orion: GPIO support [ARM] Orion: programable address map support ... Conflicts: arch/arm/Kconfig arch/arm/Makefile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Russell King
commit
c00d4ffdba
44 changed files with 6156 additions and 37 deletions
17
include/asm-arm/arch-orion/debug-macro.S
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17
include/asm-arm/arch-orion/debug-macro.S
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@ -0,0 +1,17 @@
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|||
/*
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* linux/include/asm-arm/arch-orion/debug-macro.S
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*
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||||
* Debugging macro include header
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
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||||
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.macro addruart,rx
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mov \rx, #0xf1000000
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orr \rx, \rx, #0x00012000
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.endm
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#define UART_SHIFT 2
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#include <asm/hardware/debug-8250.S>
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1
include/asm-arm/arch-orion/dma.h
Normal file
1
include/asm-arm/arch-orion/dma.h
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@ -0,0 +1 @@
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/* empty */
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31
include/asm-arm/arch-orion/entry-macro.S
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31
include/asm-arm/arch-orion/entry-macro.S
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@ -0,0 +1,31 @@
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/*
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* include/asm-arm/arch-orion/entry-macro.S
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*
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* Low-level IRQ helper macros for Orion platforms
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*
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||||
* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/arch/orion.h>
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.macro disable_fiq
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =MAIN_IRQ_CAUSE
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #0] @ main cause
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ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
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mov \irqnr, #0 @ default irqnr
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@ find cause bits that are unmasked
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ands \irqstat, \irqstat, \tmp @ clear Z flag if any
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clzne \irqnr, \irqstat @ calc irqnr
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rsbne \irqnr, \irqnr, #31
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.endm
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28
include/asm-arm/arch-orion/gpio.h
Normal file
28
include/asm-arm/arch-orion/gpio.h
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@ -0,0 +1,28 @@
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/*
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* include/asm-arm/arch-orion/gpio.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
|
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* warranty of any kind, whether express or implied.
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*/
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extern int gpio_request(unsigned pin, const char *label);
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extern void gpio_free(unsigned pin);
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extern int gpio_direction_input(unsigned pin);
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extern int gpio_direction_output(unsigned pin, int value);
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extern int gpio_get_value(unsigned pin);
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extern void gpio_set_value(unsigned pin, int value);
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extern void orion_gpio_set_blink(unsigned pin, int blink);
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extern void gpio_display(void); /* debug */
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static inline int gpio_to_irq(int pin)
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{
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return pin + IRQ_ORION_GPIO_START;
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}
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static inline int irq_to_gpio(int irq)
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{
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return irq - IRQ_ORION_GPIO_START;
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}
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#include <asm-generic/gpio.h> /* cansleep wrappers */
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24
include/asm-arm/arch-orion/hardware.h
Normal file
24
include/asm-arm/arch-orion/hardware.h
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@ -0,0 +1,24 @@
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/*
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* include/asm-arm/arch-orion/hardware.h
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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#define __ASM_ARCH_HARDWARE_H__
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#include "orion.h"
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#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
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#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
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#define pcibios_assign_all_busses() 1
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x01000000
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#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
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#endif /* _ASM_ARCH_HARDWARE_H */
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27
include/asm-arm/arch-orion/io.h
Normal file
27
include/asm-arm/arch-orion/io.h
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@ -0,0 +1,27 @@
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/*
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* include/asm-arm/arch-orion/io.h
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include "orion.h"
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#define IO_SPACE_LIMIT 0xffffffff
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#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE
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static inline void __iomem *__io(unsigned long addr)
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{
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return (void __iomem *)addr;
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}
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#define __io(a) __io(a)
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#define __mem_pci(a) (a)
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#endif
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61
include/asm-arm/arch-orion/irqs.h
Normal file
61
include/asm-arm/arch-orion/irqs.h
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@ -0,0 +1,61 @@
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/*
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* include/asm-arm/arch-orion/irqs.h
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*
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* IRQ definitions for Orion SoC
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IRQS_H__
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#define __ASM_ARCH_IRQS_H__
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#include "orion.h" /* need GPIO_MAX */
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/*
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* Orion Main Interrupt Controller
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*/
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#define IRQ_ORION_BRIDGE 0
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#define IRQ_ORION_DOORBELL_H2C 1
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#define IRQ_ORION_DOORBELL_C2H 2
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#define IRQ_ORION_UART0 3
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#define IRQ_ORION_UART1 4
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#define IRQ_ORION_I2C 5
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#define IRQ_ORION_GPIO_0_7 6
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#define IRQ_ORION_GPIO_8_15 7
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#define IRQ_ORION_GPIO_16_23 8
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#define IRQ_ORION_GPIO_24_31 9
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#define IRQ_ORION_PCIE0_ERR 10
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#define IRQ_ORION_PCIE0_INT 11
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#define IRQ_ORION_USB1_CTRL 12
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#define IRQ_ORION_DEV_BUS_ERR 14
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#define IRQ_ORION_PCI_ERR 15
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#define IRQ_ORION_USB_BR_ERR 16
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#define IRQ_ORION_USB0_CTRL 17
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#define IRQ_ORION_ETH_RX 18
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#define IRQ_ORION_ETH_TX 19
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#define IRQ_ORION_ETH_MISC 20
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#define IRQ_ORION_ETH_SUM 21
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#define IRQ_ORION_ETH_ERR 22
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#define IRQ_ORION_IDMA_ERR 23
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#define IRQ_ORION_IDMA_0 24
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#define IRQ_ORION_IDMA_1 25
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#define IRQ_ORION_IDMA_2 26
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#define IRQ_ORION_IDMA_3 27
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#define IRQ_ORION_CESA 28
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#define IRQ_ORION_SATA 29
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#define IRQ_ORION_XOR0 30
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#define IRQ_ORION_XOR1 31
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/*
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* Orion General Purpose Pins
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*/
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#define IRQ_ORION_GPIO_START 32
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#define NR_GPIO_IRQS GPIO_MAX
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#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
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#endif /* __ASM_ARCH_IRQS_H__ */
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15
include/asm-arm/arch-orion/memory.h
Normal file
15
include/asm-arm/arch-orion/memory.h
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@ -0,0 +1,15 @@
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/*
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* include/asm-arm/arch-orion/memory.h
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*
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* Marvell Orion memory definitions
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*/
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#ifndef __ASM_ARCH_MMU_H
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#define __ASM_ARCH_MMU_H
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#define PHYS_OFFSET UL(0x00000000)
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#define __virt_to_bus(x) __virt_to_phys(x)
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#define __bus_to_virt(x) __phys_to_virt(x)
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#endif
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143
include/asm-arm/arch-orion/orion.h
Normal file
143
include/asm-arm/arch-orion/orion.h
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@ -0,0 +1,143 @@
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/*
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* include/asm-arm/arch-orion/orion.h
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*
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* Generic definitions of Orion SoC flavors:
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* Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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||||
*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_ORION_H__
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#define __ASM_ARCH_ORION_H__
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/*******************************************************************************
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* Orion Address Map
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* Use the same mapping (1:1 virtual:physical) of internal registers and
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* PCI system (PCI+PCIE) for all machines.
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* Each machine defines the rest of its mapping (e.g. device bus flashes)
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******************************************************************************/
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#define ORION_REGS_BASE 0xf1000000
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#define ORION_REGS_SIZE SZ_1M
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#define ORION_PCI_SYS_MEM_BASE 0xe0000000
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#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
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#define ORION_PCIE_MEM_SIZE SZ_128M
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#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
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#define ORION_PCI_MEM_SIZE SZ_128M
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#define ORION_PCI_SYS_IO_BASE 0xf2000000
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#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
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#define ORION_PCIE_IO_SIZE SZ_1M
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#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
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#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
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#define ORION_PCI_IO_SIZE SZ_1M
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#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
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/* Relevant only for Orion-NAS */
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#define ORION_PCIE_WA_BASE 0xf0000000
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#define ORION_PCIE_WA_SIZE SZ_16M
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/*******************************************************************************
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* Supported Devices & Revisions
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******************************************************************************/
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/* Orion-1 (88F5181) */
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#define MV88F5181_DEV_ID 0x5181
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#define MV88F5181_REV_B1 3
|
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/* Orion-NAS (88F5182) */
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#define MV88F5182_DEV_ID 0x5182
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#define MV88F5182_REV_A2 2
|
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/* Orion-2 (88F5281) */
|
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#define MV88F5281_DEV_ID 0x5281
|
||||
#define MV88F5281_REV_D1 5
|
||||
#define MV88F5281_REV_D2 6
|
||||
|
||||
/*******************************************************************************
|
||||
* Orion Registers Map
|
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******************************************************************************/
|
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#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
|
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#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
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#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
|
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#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
|
||||
#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
|
||||
#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
|
||||
#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
|
||||
#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
|
||||
#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
|
||||
|
||||
#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
|
||||
#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
|
||||
#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
|
||||
#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
|
||||
#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
|
||||
#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
|
||||
#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
|
||||
#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
|
||||
#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
|
||||
|
||||
/*******************************************************************************
|
||||
* Device Bus Registers
|
||||
******************************************************************************/
|
||||
#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
|
||||
#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
|
||||
#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
|
||||
#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
|
||||
#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
|
||||
#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
|
||||
#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
|
||||
#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
|
||||
#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
|
||||
#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
|
||||
#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
|
||||
#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
|
||||
#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
|
||||
#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
|
||||
#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
|
||||
#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
|
||||
#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
|
||||
#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
|
||||
#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
|
||||
#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
|
||||
#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
|
||||
#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
|
||||
#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
|
||||
#define GPIO_MAX 32
|
||||
|
||||
/***************************************************************************
|
||||
* Orion CPU Bridge Registers
|
||||
**************************************************************************/
|
||||
#define CPU_CONF ORION_BRIDGE_REG(0x100)
|
||||
#define CPU_CTRL ORION_BRIDGE_REG(0x104)
|
||||
#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
|
||||
#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
|
||||
#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
|
||||
#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
|
||||
#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
|
||||
#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
|
||||
#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
|
||||
#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
|
||||
#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
|
||||
#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*******************************************************************************
|
||||
* Helpers to access Orion registers
|
||||
******************************************************************************/
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define orion_read(r) __raw_readl(r)
|
||||
#define orion_write(r, val) __raw_writel(val, r)
|
||||
|
||||
/*
|
||||
* These are not preempt safe. Locks, if needed, must be taken care by caller.
|
||||
*/
|
||||
#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
|
||||
#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ASM_ARCH_ORION_H__ */
|
||||
25
include/asm-arm/arch-orion/platform.h
Normal file
25
include/asm-arm/arch-orion/platform.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* asm-arm/arch-orion/platform.h
|
||||
*
|
||||
* Tzachi Perelstein <tzachi@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_PLATFORM_H__
|
||||
#define __ASM_ARCH_PLATFORM_H__
|
||||
|
||||
/*
|
||||
* Device bus NAND private data
|
||||
*/
|
||||
struct orion_nand_data {
|
||||
struct mtd_partition *parts;
|
||||
u32 nr_parts;
|
||||
u8 ale; /* address line number connected to ALE */
|
||||
u8 cle; /* address line number connected to CLE */
|
||||
u8 width; /* buswidth */
|
||||
};
|
||||
|
||||
#endif
|
||||
31
include/asm-arm/arch-orion/system.h
Normal file
31
include/asm-arm/arch-orion/system.h
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* include/asm-arm/arch-orion/system.h
|
||||
*
|
||||
* Tzachi Perelstein <tzachi@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/orion.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
/*
|
||||
* Enable and issue soft reset
|
||||
*/
|
||||
orion_setbits(CPU_RESET_MASK, (1 << 2));
|
||||
orion_setbits(CPU_SOFT_RESET, 1);
|
||||
}
|
||||
|
||||
#endif
|
||||
12
include/asm-arm/arch-orion/timex.h
Normal file
12
include/asm-arm/arch-orion/timex.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* include/asm-arm/arch-orion/timex.h
|
||||
*
|
||||
* Tzachi Perelstein <tzachi@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#define ORION_TCLK 166666667
|
||||
#define CLOCK_TICK_RATE ORION_TCLK
|
||||
44
include/asm-arm/arch-orion/uncompress.h
Normal file
44
include/asm-arm/arch-orion/uncompress.h
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* include/asm-arm/arch-orion/uncompress.h
|
||||
*
|
||||
* Tzachi Perelstein <tzachi@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <asm/arch/orion.h>
|
||||
|
||||
#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
|
||||
#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
|
||||
|
||||
#define LSR_THRE 0x20
|
||||
|
||||
static void putc(const char c)
|
||||
{
|
||||
int j = 0x1000;
|
||||
while (--j && !(*MV_UART_LSR & LSR_THRE))
|
||||
barrier();
|
||||
*MV_UART_THR = c;
|
||||
}
|
||||
|
||||
static void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void orion_early_putstr(const char *ptr)
|
||||
{
|
||||
char c;
|
||||
while ((c = *ptr++) != '\0') {
|
||||
if (c == '\n')
|
||||
putc('\r');
|
||||
putc(c);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
#define arch_decomp_wdog()
|
||||
5
include/asm-arm/arch-orion/vmalloc.h
Normal file
5
include/asm-arm/arch-orion/vmalloc.h
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
/*
|
||||
* include/asm-arm/arch-orion/vmalloc.h
|
||||
*/
|
||||
|
||||
#define VMALLOC_END 0xf0000000
|
||||
|
|
@ -94,6 +94,14 @@
|
|||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_FEROCEON)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
# else
|
||||
# define _CACHE feroceon
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_V6)
|
||||
//# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
|
|
|
|||
|
|
@ -185,6 +185,14 @@
|
|||
# define CPU_NAME cpu_xsc3
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_FEROCEON
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
# define MULTI_CPU
|
||||
# else
|
||||
# define CPU_NAME cpu_feroceon
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_V6
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
|
||||
#include <asm/types.h>
|
||||
#include <linux/mv643xx_eth.h>
|
||||
#include <linux/mv643xx_i2c.h>
|
||||
|
||||
/****************************************/
|
||||
/* Processor Address Space */
|
||||
|
|
@ -863,7 +864,6 @@
|
|||
/* I2C Registers */
|
||||
/****************************************/
|
||||
|
||||
#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c"
|
||||
#define MV64XXX_I2C_OFFSET 0xc000
|
||||
#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020
|
||||
|
||||
|
|
@ -968,14 +968,6 @@ struct mpsc_pdata {
|
|||
u32 brg_clk_freq;
|
||||
};
|
||||
|
||||
/* i2c Platform Device, Driver Data */
|
||||
struct mv64xxx_i2c_pdata {
|
||||
u32 freq_m;
|
||||
u32 freq_n;
|
||||
u32 timeout; /* In milliseconds */
|
||||
u32 retries;
|
||||
};
|
||||
|
||||
/* Watchdog Platform Device, Driver Data */
|
||||
#define MV64x60_WDT_NAME "mv64x60_wdt"
|
||||
|
||||
|
|
|
|||
22
include/linux/mv643xx_i2c.h
Normal file
22
include/linux/mv643xx_i2c.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _MV64XXX_I2C_H_
|
||||
#define _MV64XXX_I2C_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c"
|
||||
|
||||
/* i2c Platform Device, Driver Data */
|
||||
struct mv64xxx_i2c_pdata {
|
||||
u32 freq_m;
|
||||
u32 freq_n;
|
||||
u32 timeout; /* In milliseconds */
|
||||
};
|
||||
|
||||
#endif /*_MV64XXX_I2C_H_*/
|
||||
Loading…
Reference in a new issue