mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
Allwinner clock changes for 3.12
These patches mostly do some cleanup to introduce the basic gated clocks for the Allwinner A10s, A20 and A31 SoCs. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJSGxj+AAoJEBx+YmzsjxAgTgAP/0eiUlXaqfeDmR9f68S3idD4 zqAl3KJNOrfuAVMgfO35UrUtgvToKN4gL1MRKfobhami5gtp6aWGtss34FMnVUyt f7nRfnyDlG9w6nkZspoh/mJf/IG7g+SCHZN0ywZ5W5yBtYvcwBWPpbpiVFOcOzFY jJov0MwkKkqqjcP5PxQOe8xW7tf8BPKcMRj7Edzb//z98Tr9XjjgJQmpJoKQIzW2 sSfBY7mJgwN4P1mvmTly0ZIIHQ7hPqf0eRLJuh2p1cfv5KvtHR5RU9TZJHbk4qZF DeSBaFO5QeYbixKKbdJvQmBjf3uwIp41xl38h9S1PnSKF1cVmSUGL/ZrjdDIboGy woRhT3cU+jKf3GvioeqzShfYziHacfORmWiJn4M5zFEfVpna0iW/Sr5LVzOdyPVU SG9VldCnzeF0W3ihFednb6BJn02zMa3kO+zozWKXaIByfOkJIL5E6FOYmulYB6RA jJXfRUbZeG+G3fKKLNc24Gho57kYhRJIf2OwNJRSfhEuCR76lR3KhceLoUIzMJ3o 08D8GsbXtYEDlDe422qjXh9zCor16mI41wGgXxSS2AaELB+ZuExy8WFutkdPNOFT 377cQiZLjypa5bZHHco5Z5leqVi22iMN4I+r7fesIfk/zTvl7XdceM10W4+m3ic6 n8ONpb7ZrZlUwGZGZiwz =q+yI -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-3.12' of https://github.com/mripard/linux into clk-next-sunxi Allwinner clock changes for 3.12 These patches mostly do some cleanup to introduce the basic gated clocks for the Allwinner A10s, A20 and A31 SoCs. Conflicts: drivers/clk/sunxi/clk-sunxi.c
This commit is contained in:
Mike Turquette
commit
c045ddeb38
5 changed files with 462 additions and 38 deletions
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@ -25,12 +25,12 @@
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static DEFINE_SPINLOCK(clk_lock);
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/**
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* sunxi_osc_clk_setup() - Setup function for gatable oscillator
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* sun4i_osc_clk_setup() - Setup function for gatable oscillator
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*/
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#define SUNXI_OSC24M_GATE 0
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static void __init sunxi_osc_clk_setup(struct device_node *node)
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static void __init sun4i_osc_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_fixed_rate *fixed;
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@ -69,18 +69,18 @@ static void __init sunxi_osc_clk_setup(struct device_node *node)
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clk_register_clkdev(clk, clk_name, NULL);
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}
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}
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CLK_OF_DECLARE(sunxi_osc, "allwinner,sun4i-osc-clk", sunxi_osc_clk_setup);
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CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
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/**
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* sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1
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* sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
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* PLL1 rate is calculated as follows
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* rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
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* parent_rate is always 24Mhz
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*/
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static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate,
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static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 div;
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@ -125,15 +125,97 @@ static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate,
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*n = div / 4;
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}
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/**
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* sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
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* PLL1 rate is calculated as follows
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* rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
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* parent_rate should always be 24MHz
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*/
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static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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/*
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* We can operate only on MHz, this will make our life easier
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* later.
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*/
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u32 freq_mhz = *freq / 1000000;
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u32 parent_freq_mhz = parent_rate / 1000000;
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/*
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* Round down the frequency to the closest multiple of either
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* 6 or 16
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*/
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u32 round_freq_6 = round_down(freq_mhz, 6);
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u32 round_freq_16 = round_down(freq_mhz, 16);
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if (round_freq_6 > round_freq_16)
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freq_mhz = round_freq_6;
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else
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freq_mhz = round_freq_16;
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*freq = freq_mhz * 1000000;
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/*
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* If the factors pointer are null, we were just called to
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* round down the frequency.
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* Exit.
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*/
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if (n == NULL)
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return;
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/* If the frequency is a multiple of 32 MHz, k is always 3 */
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if (!(freq_mhz % 32))
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*k = 3;
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/* If the frequency is a multiple of 9 MHz, k is always 2 */
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else if (!(freq_mhz % 9))
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*k = 2;
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/* If the frequency is a multiple of 8 MHz, k is always 1 */
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else if (!(freq_mhz % 8))
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*k = 1;
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/* Otherwise, we don't use the k factor */
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else
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*k = 0;
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/*
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* If the frequency is a multiple of 2 but not a multiple of
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* 3, m is 3. This is the first time we use 6 here, yet we
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* will use it on several other places.
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* We use this number because it's the lowest frequency we can
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* generate (with n = 0, k = 0, m = 3), so every other frequency
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* somehow relates to this frequency.
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*/
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if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
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*m = 2;
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/*
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* If the frequency is a multiple of 6MHz, but the factor is
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* odd, m will be 3
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*/
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else if ((freq_mhz / 6) & 1)
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*m = 3;
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/* Otherwise, we end up with m = 1 */
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else
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*m = 1;
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/* Calculate n thanks to the above factors we already got */
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*n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
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/*
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* If n end up being outbound, and that we can still decrease
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* m, do it.
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*/
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if ((*n + 1) > 31 && (*m + 1) > 1) {
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*n = (*n + 1) / 2 - 1;
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*m = (*m + 1) / 2 - 1;
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}
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}
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/**
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* sunxi_get_apb1_factors() - calculates m, p factors for APB1
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1
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* APB1 rate is calculated as follows
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate,
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static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u8 calcm, calcp;
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@ -179,7 +261,7 @@ struct factors_data {
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
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};
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static struct clk_factors_config pll1_config = {
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static struct clk_factors_config sun4i_pll1_config = {
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.nshift = 8,
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.nwidth = 5,
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.kshift = 4,
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@ -190,21 +272,35 @@ static struct clk_factors_config pll1_config = {
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.pwidth = 2,
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};
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static struct clk_factors_config apb1_config = {
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static struct clk_factors_config sun6i_a31_pll1_config = {
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.nshift = 8,
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.nwidth = 5,
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.kshift = 4,
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.kwidth = 2,
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.mshift = 0,
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.mwidth = 2,
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};
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static struct clk_factors_config sun4i_apb1_config = {
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.mshift = 0,
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.mwidth = 5,
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.pshift = 16,
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.pwidth = 2,
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};
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static const __initconst struct factors_data pll1_data = {
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.table = &pll1_config,
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.getter = sunxi_get_pll1_factors,
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static const __initconst struct factors_data sun4i_pll1_data = {
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.table = &sun4i_pll1_config,
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.getter = sun4i_get_pll1_factors,
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};
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static const __initconst struct factors_data apb1_data = {
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.table = &apb1_config,
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.getter = sunxi_get_apb1_factors,
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static const __initconst struct factors_data sun6i_a31_pll1_data = {
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.table = &sun6i_a31_pll1_config,
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.getter = sun6i_a31_get_pll1_factors,
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};
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static const __initconst struct factors_data sun4i_apb1_data = {
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.table = &sun4i_apb1_config,
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.getter = sun4i_get_apb1_factors,
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};
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static void __init sunxi_factors_clk_setup(struct device_node *node,
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@ -240,11 +336,15 @@ struct mux_data {
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u8 shift;
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};
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static const __initconst struct mux_data cpu_mux_data = {
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static const __initconst struct mux_data sun4i_cpu_mux_data = {
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.shift = 16,
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};
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static const __initconst struct mux_data apb1_mux_data = {
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static const __initconst struct mux_data sun6i_a31_ahb1_mux_data = {
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.shift = 12,
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};
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static const __initconst struct mux_data sun4i_apb1_mux_data = {
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.shift = 24,
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};
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@ -279,26 +379,34 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
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* sunxi_divider_clk_setup() - Setup function for simple divider clocks
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*/
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#define SUNXI_DIVISOR_WIDTH 2
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struct div_data {
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u8 shift;
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u8 pow;
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u8 shift;
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u8 pow;
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u8 width;
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};
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static const __initconst struct div_data axi_data = {
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.shift = 0,
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.pow = 0,
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static const __initconst struct div_data sun4i_axi_data = {
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.shift = 0,
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.pow = 0,
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.width = 2,
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};
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static const __initconst struct div_data ahb_data = {
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.shift = 4,
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.pow = 1,
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static const __initconst struct div_data sun4i_ahb_data = {
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.shift = 4,
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.pow = 1,
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.width = 2,
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};
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static const __initconst struct div_data apb0_data = {
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.shift = 8,
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.pow = 1,
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static const __initconst struct div_data sun4i_apb0_data = {
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.shift = 8,
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.pow = 1,
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.width = 2,
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};
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static const __initconst struct div_data sun6i_a31_apb2_div_data = {
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.shift = 0,
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.pow = 0,
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.width = 4,
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};
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static void __init sunxi_divider_clk_setup(struct device_node *node,
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@ -314,7 +422,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
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clk_parent = of_clk_get_parent_name(node, 0);
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clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
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reg, data->shift, SUNXI_DIVISOR_WIDTH,
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reg, data->shift, data->width,
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data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
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&clk_lock);
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if (clk) {
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@ -343,26 +451,62 @@ static const __initconst struct gates_data sun4i_ahb_gates_data = {
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.mask = {0x7F77FFF, 0x14FB3F},
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};
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static const __initconst struct gates_data sun5i_a10s_ahb_gates_data = {
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.mask = {0x147667e7, 0x185915},
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};
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static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
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.mask = {0x107067e7, 0x185111},
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};
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static const __initconst struct gates_data sun6i_a31_ahb1_gates_data = {
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.mask = {0xEDFE7F62, 0x794F931},
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};
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static const __initconst struct gates_data sun7i_a20_ahb_gates_data = {
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.mask = { 0x12f77fff, 0x16ff3f },
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};
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static const __initconst struct gates_data sun4i_apb0_gates_data = {
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.mask = {0x4EF},
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};
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static const __initconst struct gates_data sun5i_a10s_apb0_gates_data = {
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.mask = {0x469},
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};
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static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
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.mask = {0x61},
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};
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static const __initconst struct gates_data sun7i_a20_apb0_gates_data = {
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.mask = { 0x4ff },
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};
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static const __initconst struct gates_data sun4i_apb1_gates_data = {
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.mask = {0xFF00F7},
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};
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static const __initconst struct gates_data sun5i_a10s_apb1_gates_data = {
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.mask = {0xf0007},
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};
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static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
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.mask = {0xa0007},
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};
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static const __initconst struct gates_data sun6i_a31_apb1_gates_data = {
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.mask = {0x3031},
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};
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static const __initconst struct gates_data sun6i_a31_apb2_gates_data = {
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.mask = {0x3F000F},
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};
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static const __initconst struct gates_data sun7i_a20_apb1_gates_data = {
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.mask = { 0xff80ff },
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};
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static void __init sunxi_gates_clk_setup(struct device_node *node,
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struct gates_data *data)
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{
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@ -414,23 +558,26 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
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/* Matches for factors clocks */
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static const __initconst struct of_device_id clk_factors_match[] = {
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{.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,},
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{.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,},
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{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
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{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
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{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
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{}
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};
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/* Matches for divider clocks */
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static const __initconst struct of_device_id clk_div_match[] = {
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{.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,},
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{.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,},
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{.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,},
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{.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
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{.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
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{.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
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{.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
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{}
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};
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/* Matches for mux clocks */
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static const __initconst struct of_device_id clk_mux_match[] = {
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{.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_mux_data,},
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{.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,},
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{.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
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{.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
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{.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
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{}
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};
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@ -438,11 +585,20 @@ static const __initconst struct of_device_id clk_mux_match[] = {
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static const __initconst struct of_device_id clk_gates_match[] = {
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{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
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{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
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{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
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{.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
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{.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
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{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
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{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
|
||||
{.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
|
||||
{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
|
||||
{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue