From c07590dcaa7a3d5e5af60e5266e80a4e7571fdc2 Mon Sep 17 00:00:00 2001
From: Srinivas Rao L <lsrao@qti.qualcomm.com>
Date: Mon, 24 Feb 2020 17:13:45 +0530
Subject: [PATCH] ARM: dts: msm: Add RSC device bindings for Shima

Add Apps and Display RSC device bindings for Shima.

Change-Id: I18957f0ef47ee82f747d1c03c0e4c8019f187cb9
---
 qcom/shima.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 7705ae073cb2..ba8c56b6c2d6 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/qcom,videocc-shima.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Shima";
@@ -798,6 +799,38 @@
 		mboxes = <&qmp_aop 0>;
 		mbox-names = "aop";
 	};
+
+	apps_rsc: rsc@18200000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x18200000 0x10000>,
+		      <0x18210000 0x10000>,
+		      <0x18220000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0xd00>;
+		qcom,drv-id = <2>;
+		qcom,tcs-config = <ACTIVE_TCS  2>,
+				  <SLEEP_TCS   3>,
+				  <WAKE_TCS    3>,
+				  <CONTROL_TCS 1>;
+	};
+
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0x1c00>;
+		qcom,drv-id = <0>;
+		qcom,tcs-config = <ACTIVE_TCS  0>,
+				  <SLEEP_TCS   1>,
+				  <WAKE_TCS    1>,
+				  <CONTROL_TCS 0>;
+	};
 };
 
 #include "shima-pinctrl.dtsi"