mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-07 12:25:00 -04:00
Merge "msm: pcie: add support to manage PCIe PHY PLL block"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
c09480d98d
1 changed files with 240 additions and 97 deletions
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@ -160,6 +160,8 @@
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#define IPC_TIMEOUT_MS (250)
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#define PHY_C_READY (BIT(0))
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#define PHY_READY_TIMEOUT_COUNT (10)
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#define XMLH_LINK_UP (0x400)
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#define MAX_PROP_SIZE (32)
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@ -575,6 +577,8 @@ struct msm_pcie_device_info {
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enum msm_pcie_drv_cmds {
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MSM_PCIE_DRV_CMD_ENABLE = 0xc0000000,
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MSM_PCIE_DRV_CMD_DISABLE = 0xc0000001,
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MSM_PCIE_DRV_CMD_ENABLE_L1SS_SLEEP = 0xc0000005,
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MSM_PCIE_DRV_CMD_DISABLE_L1SS_SLEEP = 0xc0000006,
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};
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/* DRV IPC message type */
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@ -606,18 +610,6 @@ struct __packed msm_pcie_drv_msg {
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struct msm_pcie_drv_tre pkt;
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};
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struct msm_pcie_drv_info {
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bool ep_connected; /* drv supports only one endpoint (no switch) */
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struct msm_pcie_drv_msg drv_enable; /* hand off payload */
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struct msm_pcie_drv_msg drv_disable; /* payload to request back */
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int dev_id;
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u16 seq;
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u16 reply_seq;
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u32 timeout_ms; /* IPC command timeout */
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u32 l1ss_timeout_us;
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struct completion completion;
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};
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/* msm pcie device structure */
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struct msm_pcie_dev_t {
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struct platform_device *pdev;
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@ -762,6 +754,27 @@ struct msm_root_dev_t {
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struct pci_dev *pci_dev;
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};
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struct msm_pcie_drv_info {
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bool ep_connected; /* drv supports only one endpoint (no switch) */
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struct msm_pcie_drv_msg drv_enable; /* hand off payload */
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struct msm_pcie_drv_msg drv_disable; /* payload to request back */
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struct msm_pcie_drv_msg drv_enable_l1ss_sleep; /* enable l1ss sleep */
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struct msm_pcie_drv_msg drv_disable_l1ss_sleep; /* disable l1ss sleep */
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int dev_id;
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u16 seq;
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u16 reply_seq;
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u32 timeout_ms; /* IPC command timeout */
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u32 l1ss_timeout_us;
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struct completion completion;
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/* for DRV SSR */
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void (*manage_pll_power_on)(struct msm_pcie_dev_t *pcie_dev,
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struct msm_pcie_drv_info *drv_info);
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u32 phy_resetsm_cntrl2;
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u32 phy_core_pll_en_mux;
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u32 phy_c_ready_status;
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};
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static u32 msm_pcie_keep_resources_on;
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/* debugfs values */
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@ -5548,14 +5561,96 @@ static void msm_pcie_check_l1ss_support_all(struct msm_pcie_dev_t *dev)
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pci_walk_bus(dev->dev->bus, msm_pcie_check_l1ss_support, dev);
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}
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static void msm_pcie_drv_manage_pll_power_on(struct msm_pcie_dev_t *pcie_dev,
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struct msm_pcie_drv_info *drv_info)
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{
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u32 cnt = 0;
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u32 cnt_max = 20; /* 1ms */
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PCIE_DBG(pcie_dev, "PCIe: RC%d: manually power on PHY PLL\n",
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pcie_dev->rc_idx);
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msm_pcie_write_mask(pcie_dev->phy + drv_info->phy_resetsm_cntrl2,
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BIT(drv_info->phy_core_pll_en_mux), 0);
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while (!(readl_relaxed(pcie_dev->phy + drv_info->phy_c_ready_status) &
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PHY_C_READY)) {
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if (unlikely(cnt++ >= cnt_max)) {
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PCIE_ERR(pcie_dev,
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"PCIe: RC%d: failed to manually power on PHY PLL\n",
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pcie_dev->rc_idx);
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return;
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}
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usleep_range(50, 55);
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}
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PCIE_DBG(pcie_dev, "PCIe: RC%d: successfully powered on PHY PLL\n",
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pcie_dev->rc_idx);
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}
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static int msm_pcie_setup_drv_manage_pll(struct msm_pcie_dev_t *pcie_dev,
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struct device_node *of_node,
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struct msm_pcie_drv_info *drv_info)
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{
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int ret;
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PCIE_DBG(pcie_dev, "PCIe: RC%d: enter\n", pcie_dev->rc_idx);
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ret = of_property_read_u32(of_node, "qcom,phy-resetsm-cntrl2",
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&drv_info->phy_resetsm_cntrl2);
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if (ret) {
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PCIE_ERR(pcie_dev,
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"PCIe: RC%d failed to get qcom,phy-resetsm-cntrl2\n",
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pcie_dev->rc_idx);
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return ret;
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}
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ret = of_property_read_u32(of_node, "qcom,phy-core-pll-en-mux",
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&drv_info->phy_core_pll_en_mux);
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if (ret) {
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PCIE_ERR(pcie_dev,
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"PCIe: RC%d failed to get qcom,phy-core-pll-en-mux\n",
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pcie_dev->rc_idx);
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return ret;
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}
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ret = of_property_read_u32(of_node, "qcom,phy-c-ready-status",
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&drv_info->phy_c_ready_status);
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if (ret) {
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PCIE_ERR(pcie_dev,
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"PCIe: RC%d failed to get qcom,phy-c-ready-status\n",
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pcie_dev->rc_idx);
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return ret;
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}
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drv_info->manage_pll_power_on = msm_pcie_drv_manage_pll_power_on;
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return 0;
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}
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static void msm_pcie_setup_drv_msg(struct msm_pcie_drv_msg *msg, u32 dev_id,
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enum msm_pcie_drv_cmds cmd)
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{
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struct msm_pcie_drv_tre *pkt = &msg->pkt;
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struct msm_pcie_drv_header *hdr = &msg->hdr;
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hdr->major_ver = MSM_PCIE_DRV_MAJOR_VERSION;
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hdr->minor_ver = MSM_PCIE_DRV_MINOR_VERSION;
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hdr->msg_id = MSM_PCIE_DRV_MSG_ID_CMD;
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hdr->payload_size = sizeof(*pkt);
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hdr->dev_id = dev_id;
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pkt->dword[0] = cmd;
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pkt->dword[1] = hdr->dev_id;
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}
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static int msm_pcie_setup_drv(struct msm_pcie_dev_t *pcie_dev,
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struct device_node *of_node)
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{
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struct msm_pcie_drv_info *drv_info;
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struct msm_pcie_drv_msg *msg;
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struct msm_pcie_drv_tre *pkt;
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struct msm_pcie_drv_header *hdr;
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int ret;
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u32 phy_manage_pll = 0;
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drv_info = devm_kzalloc(&pcie_dev->pdev->dev, sizeof(*drv_info),
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GFP_KERNEL);
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@ -5572,31 +5667,30 @@ static int msm_pcie_setup_drv(struct msm_pcie_dev_t *pcie_dev,
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drv_info->dev_id = pcie_dev->rc_idx;
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/* cache frequent command for communication */
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msg = &drv_info->drv_enable;
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pkt = &msg->pkt;
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hdr = &msg->hdr;
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hdr->major_ver = MSM_PCIE_DRV_MAJOR_VERSION;
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hdr->minor_ver = MSM_PCIE_DRV_MINOR_VERSION;
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hdr->msg_id = MSM_PCIE_DRV_MSG_ID_CMD;
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hdr->payload_size = sizeof(*pkt);
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hdr->dev_id = drv_info->dev_id;
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ret = of_property_read_u32(of_node, "qcom,phy-manage-pll",
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&phy_manage_pll);
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if (!ret && phy_manage_pll) {
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ret = msm_pcie_setup_drv_manage_pll(pcie_dev, of_node,
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drv_info);
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if (ret)
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return ret;
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}
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pkt->dword[0] = MSM_PCIE_DRV_CMD_ENABLE;
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pkt->dword[1] = hdr->dev_id;
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pkt->dword[2] = drv_info->l1ss_timeout_us / 1000;
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msm_pcie_setup_drv_msg(&drv_info->drv_enable, drv_info->dev_id,
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MSM_PCIE_DRV_CMD_ENABLE);
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msg = &drv_info->drv_disable;
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pkt = &msg->pkt;
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hdr = &msg->hdr;
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hdr->major_ver = MSM_PCIE_DRV_MAJOR_VERSION;
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hdr->minor_ver = MSM_PCIE_DRV_MINOR_VERSION;
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hdr->msg_id = MSM_PCIE_DRV_MSG_ID_CMD;
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hdr->payload_size = sizeof(*pkt);
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hdr->dev_id = drv_info->dev_id;
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msm_pcie_setup_drv_msg(&drv_info->drv_disable, drv_info->dev_id,
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MSM_PCIE_DRV_CMD_DISABLE);
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pkt->dword[0] = MSM_PCIE_DRV_CMD_DISABLE;
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pkt->dword[1] = hdr->dev_id;
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msm_pcie_setup_drv_msg(&drv_info->drv_enable_l1ss_sleep,
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drv_info->dev_id,
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MSM_PCIE_DRV_CMD_ENABLE_L1SS_SLEEP);
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drv_info->drv_enable_l1ss_sleep.pkt.dword[2] =
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drv_info->l1ss_timeout_us / 1000;
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msm_pcie_setup_drv_msg(&drv_info->drv_disable_l1ss_sleep,
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drv_info->dev_id,
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MSM_PCIE_DRV_CMD_DISABLE_L1SS_SLEEP);
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init_completion(&drv_info->completion);
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drv_info->timeout_ms = IPC_TIMEOUT_MS;
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@ -6825,18 +6919,65 @@ static void msm_pcie_fixup_resume_early(struct pci_dev *dev)
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DECLARE_PCI_FIXUP_RESUME_EARLY(PCIE_VENDOR_ID_QCOM, PCI_ANY_ID,
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msm_pcie_fixup_resume_early);
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static int msm_pcie_drv_send_rpmsg(struct msm_pcie_dev_t *pcie_dev,
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struct rpmsg_device *rpdev,
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struct msm_pcie_drv_msg *msg)
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{
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struct msm_pcie_drv_info *drv_info = pcie_dev->drv_info;
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int ret;
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reinit_completion(&drv_info->completion);
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drv_info->reply_seq = drv_info->seq++;
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msg->hdr.seq = drv_info->reply_seq;
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if (unlikely(drv_info->seq == MSM_PCIE_DRV_SEQ_RESV))
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drv_info->seq = 0;
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PCIE_DBG(pcie_dev, "PCIe: RC%d: DRV: sending rpmsg: command: 0x%x\n",
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pcie_dev->rc_idx, msg->pkt.dword[0]);
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ret = rpmsg_trysend(rpdev->ept, msg, sizeof(*msg));
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if (ret) {
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PCIE_ERR(pcie_dev, "PCIe: RC%d: DRV: failed to send rpmsg\n",
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pcie_dev->rc_idx);
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return ret;
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}
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ret = wait_for_completion_timeout(&drv_info->completion,
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msecs_to_jiffies(drv_info->timeout_ms));
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if (!ret) {
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PCIE_ERR(pcie_dev,
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"PCIe: RC%d: DRV: completion timeout for rpmsg\n",
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pcie_dev->rc_idx);
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return -ETIMEDOUT;
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}
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PCIE_DBG(pcie_dev, "PCIe: RC%d: DRV: rpmsg successfully sent\n",
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pcie_dev->rc_idx);
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return 0;
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}
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static int msm_pcie_drv_resume(struct msm_pcie_dev_t *pcie_dev)
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{
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struct rpmsg_device *rpdev = pcie_drv.rpdev;
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struct msm_pcie_drv_info *drv_info = pcie_dev->drv_info;
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struct msm_pcie_drv_msg *drv_disable = &drv_info->drv_disable;
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struct msm_pcie_clk_info_t *clk_info;
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u32 current_link_speed;
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u32 current_link_speed, clkreq_override_en = 0;
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int ret, i;
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mutex_lock(&pcie_dev->recovery_lock);
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mutex_lock(&pcie_dev->setup_lock);
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/* if rpdev is NULL then DRV subsystem is powered down */
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if (rpdev) {
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ret = msm_pcie_drv_send_rpmsg(pcie_dev, rpdev,
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&drv_info->drv_disable_l1ss_sleep);
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if (ret)
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rpdev = NULL;
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}
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msm_pcie_vreg_init(pcie_dev);
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regulator_enable(pcie_dev->gdsc);
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@ -6855,37 +6996,68 @@ static int msm_pcie_drv_resume(struct msm_pcie_dev_t *pcie_dev)
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if (clk_info->hdl && !clk_info->suppressible)
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clk_prepare_enable(clk_info->hdl);
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/*
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* if DRV subsystem did not respond to previous rpmsg command, check if
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* PCIe CLKREQ override is still enabled
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*/
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if (!rpdev) {
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clkreq_override_en = readl_relaxed(pcie_dev->parf +
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PCIE20_PARF_CLKREQ_OVERRIDE) &
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PCIE20_PARF_CLKREQ_IN_ENABLE;
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if (clkreq_override_en)
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: CLKREQ Override detected\n",
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pcie_dev->rc_idx);
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}
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/*
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* if PCIe CLKREQ override is still enabled, then make sure PCIe mux is
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* set to PCIe PIPE before enabling PCIe PIPE CLK.
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* APPS votes for mux was PCIe PIPE before DRV suspend. In order to vote
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* for PCIe PIPE, need to first set mux to XO then PCIe PIPE or else
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* clock driver will short the request.
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*/
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if (clkreq_override_en && pcie_dev->pipe_clk_mux) {
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if (pcie_dev->ref_clk_src) {
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: setting PCIe PIPE MUX to XO\n",
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pcie_dev->rc_idx);
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clk_set_parent(pcie_dev->pipe_clk_mux,
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pcie_dev->ref_clk_src);
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}
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if (pcie_dev->pipe_clk_ext_src) {
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PCIE_DBG(pcie_dev,
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"PCIe: RC%d: setting PCIe PIPE MUX to PCIe PIPE\n",
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pcie_dev->rc_idx);
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clk_set_parent(pcie_dev->pipe_clk_mux,
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pcie_dev->pipe_clk_ext_src);
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}
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}
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clk_info = pcie_dev->pipeclk;
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for (i = 0; i < MSM_PCIE_MAX_PIPE_CLK; i++, clk_info++)
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if (clk_info->hdl && !clk_info->suppressible)
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clk_prepare_enable(clk_info->hdl);
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/* if rpdev is NULL then DRV subsystem is powered down */
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if (rpdev) {
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reinit_completion(&drv_info->completion);
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if (clkreq_override_en) {
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if (drv_info->manage_pll_power_on)
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drv_info->manage_pll_power_on(pcie_dev, drv_info);
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drv_info->reply_seq = drv_info->seq++;
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drv_disable->hdr.seq = drv_info->reply_seq;
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if (unlikely(drv_info->seq == MSM_PCIE_DRV_SEQ_RESV))
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drv_info->seq = 0;
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ret = rpmsg_trysend(rpdev->ept, drv_disable,
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sizeof(*drv_disable));
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if (!ret) {
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ret = wait_for_completion_timeout(&drv_info->completion,
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msecs_to_jiffies(drv_info->timeout_ms));
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if (!ret)
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PCIE_ERR(pcie_dev,
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"PCIe: RC%d: DRV: completion timeout for rpmsg\n",
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pcie_dev->rc_idx);
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} else {
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PCIE_ERR(pcie_dev,
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"PCIe: RC%d: DRV: failed to send rpmsg\n",
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pcie_dev->rc_idx);
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}
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/* remove CLKREQ override */
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msm_pcie_write_reg_field(pcie_dev->parf,
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PCIE20_PARF_CLKREQ_OVERRIDE,
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PCIE20_PARF_CLKREQ_IN_ENABLE, 0);
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msm_pcie_write_reg_field(pcie_dev->parf,
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PCIE20_PARF_CLKREQ_OVERRIDE,
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PCIE20_PARF_CLKREQ_IN_VALUE, 0);
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}
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/* if rpdev is NULL then DRV subsystem is powered down */
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if (rpdev)
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msm_pcie_drv_send_rpmsg(pcie_dev, rpdev,
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&drv_info->drv_disable);
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/* scale CX and rate change based on current GEN speed */
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current_link_speed = readl_relaxed(pcie_dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS);
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|
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@ -6894,14 +7066,6 @@ static int msm_pcie_drv_resume(struct msm_pcie_dev_t *pcie_dev)
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msm_pcie_scale_link_bandwidth(pcie_dev, current_link_speed);
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/* always ungate clkreq */
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msm_pcie_write_reg_field(pcie_dev->parf,
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PCIE20_PARF_CLKREQ_OVERRIDE,
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PCIE20_PARF_CLKREQ_IN_ENABLE, 0);
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msm_pcie_write_reg_field(pcie_dev->parf,
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PCIE20_PARF_CLKREQ_OVERRIDE,
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PCIE20_PARF_CLKREQ_IN_VALUE, 0);
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pcie_dev->user_suspend = false;
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spin_lock_irq(&pcie_dev->cfg_lock);
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pcie_dev->cfg_access = true;
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|
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@ -6921,8 +7085,6 @@ static int msm_pcie_drv_suspend(struct msm_pcie_dev_t *pcie_dev,
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{
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struct rpmsg_device *rpdev = pcie_drv.rpdev;
|
||||
struct msm_pcie_drv_info *drv_info = pcie_dev->drv_info;
|
||||
struct msm_pcie_drv_msg *drv_enable = &drv_info->drv_enable;
|
||||
struct msm_pcie_drv_tre *pkt = &drv_enable->pkt;
|
||||
struct msm_pcie_clk_info_t *clk_info;
|
||||
int ret, i;
|
||||
|
||||
|
|
@ -6940,36 +7102,12 @@ static int msm_pcie_drv_suspend(struct msm_pcie_dev_t *pcie_dev,
|
|||
}
|
||||
|
||||
mutex_lock(&pcie_dev->recovery_lock);
|
||||
reinit_completion(&drv_info->completion);
|
||||
|
||||
/* disable global irq - no more linkdown/aer detection */
|
||||
disable_irq(pcie_dev->irq[MSM_PCIE_INT_GLOBAL_INT].num);
|
||||
|
||||
if (options & MSM_PCIE_CONFIG_NO_L1SS_TO)
|
||||
pkt->dword[2] = 0;
|
||||
else
|
||||
pkt->dword[2] = drv_info->l1ss_timeout_us / 1000;
|
||||
|
||||
drv_info->reply_seq = drv_info->seq++;
|
||||
drv_enable->hdr.seq = drv_info->reply_seq;
|
||||
|
||||
if (unlikely(drv_info->seq == MSM_PCIE_DRV_SEQ_RESV))
|
||||
drv_info->seq = 0;
|
||||
|
||||
ret = rpmsg_trysend(rpdev->ept, drv_enable, sizeof(*drv_enable));
|
||||
ret = msm_pcie_drv_send_rpmsg(pcie_dev, rpdev, &drv_info->drv_enable);
|
||||
if (ret) {
|
||||
PCIE_ERR(pcie_dev, "PCIe: RC%d: DRV: failed to send rpmsg\n",
|
||||
pcie_dev->rc_idx);
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = wait_for_completion_timeout(&drv_info->completion,
|
||||
msecs_to_jiffies(drv_info->timeout_ms));
|
||||
if (!ret) {
|
||||
PCIE_ERR(pcie_dev,
|
||||
"PCIe: RC%d: DRV: completion timeout for rpmsg\n",
|
||||
pcie_dev->rc_idx);
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
|
@ -7007,6 +7145,11 @@ static int msm_pcie_drv_suspend(struct msm_pcie_dev_t *pcie_dev,
|
|||
|
||||
msm_pcie_vreg_deinit(pcie_dev);
|
||||
|
||||
/* enable L1ss sleep if client allows it */
|
||||
if (!(options & MSM_PCIE_CONFIG_NO_L1SS_TO))
|
||||
msm_pcie_drv_send_rpmsg(pcie_dev, rpdev,
|
||||
&drv_info->drv_enable_l1ss_sleep);
|
||||
|
||||
mutex_unlock(&pcie_dev->setup_lock);
|
||||
mutex_unlock(&pcie_dev->recovery_lock);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue