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Merge "ARM: dts: msm: Add jtagv8 devices for yupik"

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qctecmdr 2020-12-20 00:48:53 -08:00 • committed by Gerrit - the friendly Code Review server
commit c094ecd586
1 changed files with 88 additions and 0 deletions
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88
qcom/yupik.dtsi
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@ -581,6 +581,94 @@
};
};
jtag_mm0: jtagmm@7040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7040000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@7140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7140000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@7240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7240000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@7340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7340000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@7440000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7440000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@7540000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7540000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@7640000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7640000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@7740000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7740000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";