mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: DT updates for v4.4
As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here.) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWQT2WAAoJEIwa5zzehBx37tgQAIBe5eDJFXFihTlyOQ2plL3q vVH4OCzXIHELfM1J8CGZNah1wCQqNOts8RAmDCzxr+zSYuLOwJOEDZ6NKmErMxl0 NTj3+BsqKO3NRym970ofPqU9JRLQmpZ8K7dzk8Nwj2+r1WZHFu/j6Jv44n/Ns0lw 7+wxnG322lTm7SnvALCMD5lD4Y7VpThooWy5SdFtRoAetn+cLbVCJIeeQvO6Vxkp NooeJR0t2e8cpbAND5Jwu6eeWRcIbrvgjYDe0omhrIY05i9yNvIsC2HuQFGjF43z p2CnQvcKnhOXTZw3yse1Fx5igA7jqwVjjC/lVeDyxhusAtLpmuB6qbSaj7DpqkSQ nJxX1d49WKm68K+aknmee1kYRrvc4DE/kORI4IxXnsVNMu16ifTVLnxKgUhwzukb eZdTP6rsqgNozaYvh0k1vfSFd+CNSkBg+E9nrI3tU95yo3LOIhobVBCvBcWlmUvQ JdavRztqosChjIx3a9i1eCNKJtCg9p4m+gWjUqVVWsxBHe/3HojzjZnsBSynIQMA uGIVm0TKhNl1Svxl3oJo9257UCUK7+5PqJHK9IHrcWDULYx05JGSjuZcyvNS6Fo+ u1DMf0ud4gXJYhecFBa7b3zRjk5YxptgCCTjeEEOTUJbbhZqDjGFZlNuFi6dmqD3 ILJ2QMe/DGiPIlUmCfsx =qY1q -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
This commit is contained in:
Linus Torvalds
commit
c0d6fe2f01
433 changed files with 20755 additions and 3428 deletions
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@ -9,6 +9,12 @@ Boards with the Amlogic Meson8 SoC shall have the following properties:
|
|||
Required root node property:
|
||||
compatible: "amlogic,meson8";
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||||
|
||||
Boards with the Amlogic Meson8b SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible: "amlogic,meson8b";
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||||
|
||||
Board compatible values:
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||||
- "geniatech,atv1200"
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||||
- "minix,neo-x8"
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||||
- "geniatech,atv1200" (Meson6)
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- "minix,neo-x8" (Meson8)
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||||
- "tronfy,mxq" (Meson8b)
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- "hardkernel,odroid-c1" (Meson8b)
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17
Documentation/devicetree/bindings/arm/apm/scu.txt
Normal file
17
Documentation/devicetree/bindings/arm/apm/scu.txt
Normal file
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@ -0,0 +1,17 @@
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APM X-GENE SoC series SCU Registers
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|
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This system clock unit contain various register that control block resets,
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clock enable/disables, clock divisors and other deepsleep registers.
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Properties:
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- compatible : should contain two values. First value must be:
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- "apm,xgene-scu"
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second value must be always "syscon".
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- reg : offset and length of the register set.
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Example :
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scu: system-clk-controller@17000000 {
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compatible = "apm,xgene-scu","syscon";
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reg = <0x0 0x17000000 0x0 0x400>;
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};
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@ -20,6 +20,25 @@ system control is required:
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- compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
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- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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hif-cpubiuctrl node
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-------------------
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SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
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(BIU) block which controls and interfaces the CPU complex to the different
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Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
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offers a feature called Write Pairing which consists in collapsing two adjacent
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cache lines into a single (bursted) write transaction towards the memory
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controller (MEMC) to maximize write bandwidth.
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Required properties:
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- compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
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Optional properties:
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- brcm,write-pairing:
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Boolean property, which when present indicates that the chip
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supports write-pairing.
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example:
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rdb {
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#address-cells = <1>;
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@ -35,6 +54,7 @@ example:
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hif_cpubiuctrl: syscon@3e2400 {
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compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
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reg = <0x3e2400 0x5b4>;
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brcm,write-pairing;
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};
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hif_continuation: syscon@452000 {
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@ -43,8 +63,7 @@ example:
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};
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};
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Lastly, nodes that allow for support of SMP initialization and reboot are
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required:
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Nodes that allow for support of SMP initialization and reboot are required:
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smpboot
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-------
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@ -95,3 +114,142 @@ example:
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compatible = "brcm,brcmstb-reboot";
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syscon = <&sun_top_ctrl 0x304 0x308>;
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};
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|
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Power management
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----------------
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For power management (particularly, S2/S3/S5 system suspend), the following SoC
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components are needed:
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= Always-On control block (AON CTRL)
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|
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This hardware provides control registers for the "always-on" (even in low-power
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modes) hardware, such as the Power Management State Machine (PMSM).
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|
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Required properties:
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- compatible : should contain "brcm,brcmstb-aon-ctrl"
|
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- reg : the register start and length for the AON CTRL block
|
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|
||||
Example:
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||||
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aon-ctrl@410000 {
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compatible = "brcm,brcmstb-aon-ctrl";
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reg = <0x410000 0x400>;
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};
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= Memory controllers
|
||||
|
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A Broadcom STB SoC typically has a number of independent memory controllers,
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each of which may have several associated hardware blocks, which are versioned
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independently (control registers, DDR PHYs, etc.). One might consider
|
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describing these controllers as a parent "memory controllers" block, which
|
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contains N sub-nodes (one for each controller in the system), each of which is
|
||||
associated with a number of hardware register resources (e.g., its PHY). See
|
||||
the example device tree snippet below.
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|
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== MEMC (MEMory Controller)
|
||||
|
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Represents a single memory controller instance.
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|
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Required properties:
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- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
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|
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Should contain subnodes for any of the following relevant hardware resources:
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||||
|
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== DDR PHY control
|
||||
|
||||
Control registers for this memory controller's DDR PHY.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one of these
|
||||
"brcm,brcmstb-ddr-phy-v225.1"
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"brcm,brcmstb-ddr-phy-v240.1"
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"brcm,brcmstb-ddr-phy-v240.2"
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|
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- reg : the DDR PHY register range
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|
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== DDR SHIMPHY
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|
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Control registers for this memory controller's DDR SHIMPHY.
|
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|
||||
Required properties:
|
||||
- compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
|
||||
- reg : the DDR SHIMPHY register range
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||||
|
||||
== MEMC DDR control
|
||||
|
||||
Sequencer DRAM parameters and control registers. Used for Self-Refresh
|
||||
Power-Down (SRPD), among other things.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "brcm,brcmstb-memc-ddr"
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- reg : the MEMC DDR register range
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Example:
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memory_controllers {
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ranges;
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compatible = "simple-bus";
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memc@0 {
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compatible = "brcm,brcmstb-memc", "simple-bus";
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ranges;
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|
||||
ddr-phy@f1106000 {
|
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compatible = "brcm,brcmstb-ddr-phy-v240.1";
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||||
reg = <0xf1106000 0x21c>;
|
||||
};
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||||
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||||
shimphy@f1108000 {
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
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reg = <0xf1108000 0xe4>;
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||||
};
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||||
|
||||
memc-ddr@f1102000 {
|
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reg = <0xf1102000 0x800>;
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
};
|
||||
};
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||||
|
||||
memc@1 {
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compatible = "brcm,brcmstb-memc", "simple-bus";
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ranges;
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||||
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ddr-phy@f1186000 {
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compatible = "brcm,brcmstb-ddr-phy-v240.1";
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reg = <0xf1186000 0x21c>;
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};
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shimphy@f1188000 {
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
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reg = <0xf1188000 0xe4>;
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};
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||||
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memc-ddr@f1182000 {
|
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reg = <0xf1182000 0x800>;
|
||||
compatible = "brcm,brcmstb-memc-ddr";
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||||
};
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||||
};
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||||
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||||
memc@2 {
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compatible = "brcm,brcmstb-memc", "simple-bus";
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ranges;
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ddr-phy@f1206000 {
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compatible = "brcm,brcmstb-ddr-phy-v240.1";
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||||
reg = <0xf1206000 0x21c>;
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||||
};
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shimphy@f1208000 {
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
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||||
reg = <0xf1208000 0xe4>;
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||||
};
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||||
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memc-ddr@f1202000 {
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reg = <0xf1202000 0x800>;
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||||
compatible = "brcm,brcmstb-memc-ddr";
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||||
};
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||||
};
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||||
};
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||||
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34
Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt
Normal file
34
Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt
Normal file
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@ -0,0 +1,34 @@
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Broadcom Northstar Plus device tree bindings
|
||||
--------------------------------------------
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||||
|
||||
Broadcom Northstar Plus family of SoCs are used for switching control
|
||||
and management applications as well as residential router/gateway
|
||||
applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
|
||||
several peripheral interfaces including multiple Gigabit Ethernet PHYs,
|
||||
DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
|
||||
SATA and several other IO controllers.
|
||||
|
||||
Boards with Northstar Plus SoCs shall have the following properties:
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||||
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Required root node property:
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||||
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BCM58522
|
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compatible = "brcm,bcm58522", "brcm,nsp";
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||||
|
||||
BCM58525
|
||||
compatible = "brcm,bcm58525", "brcm,nsp";
|
||||
|
||||
BCM58535
|
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compatible = "brcm,bcm58535", "brcm,nsp";
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||||
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||||
BCM58622
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compatible = "brcm,bcm58622", "brcm,nsp";
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||||
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||||
BCM58623
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compatible = "brcm,bcm58623", "brcm,nsp";
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BCM58625
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compatible = "brcm,bcm58625", "brcm,nsp";
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BCM88312
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compatible = "brcm,bcm88312", "brcm,nsp";
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@ -195,6 +195,8 @@ nodes to be present and contain the properties described below.
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"marvell,armada-380-smp"
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||||
"marvell,armada-390-smp"
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"marvell,armada-xp-smp"
|
||||
"mediatek,mt6589-smp"
|
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"mediatek,mt81xx-tz-smp"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,kpss-acc-v1"
|
||||
"qcom,kpss-acc-v2"
|
||||
|
|
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|||
|
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@ -128,10 +128,18 @@ Example:
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|||
reg = <0x0 0x1ee0000 0x0 0x10000>;
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||||
};
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||||
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Freescale LS2085A SoC Device Tree Bindings
|
||||
------------------------------------------
|
||||
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
|
||||
----------------------------------------------------------------
|
||||
|
||||
LS2085A ARMv8 based Simulator model
|
||||
LS2080A ARMv8 based Simulator model
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
|
||||
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
|
||||
|
||||
LS2080A ARMv8 based QDS Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
|
||||
|
||||
LS2080A ARMv8 based RDB Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,10 @@ HiKey Board
|
|||
Required root node properties:
|
||||
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
|
||||
|
||||
HiP05 D02 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip05-d02";
|
||||
|
||||
Hisilicon system controller
|
||||
|
||||
Required properties:
|
||||
|
|
|
|||
|
|
@ -9,12 +9,26 @@ Required properties:
|
|||
the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
|
||||
type UART should use the specified compatible for those devices.
|
||||
|
||||
SoC families:
|
||||
|
||||
- Keystone 2 generic SoC:
|
||||
compatible = "ti,keystone"
|
||||
|
||||
SoCs:
|
||||
|
||||
- Keystone 2 Hawking/Kepler
|
||||
compatible = "ti,k2hk", "ti,keystone"
|
||||
- Keystone 2 Lamarr
|
||||
compatible = "ti,k2l", "ti,keystone"
|
||||
- Keystone 2 Edison
|
||||
compatible = "ti,k2e", "ti,keystone"
|
||||
|
||||
Boards:
|
||||
- Keystone 2 Hawking/Kepler EVM
|
||||
compatible = "ti,k2hk-evm","ti,keystone"
|
||||
compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"
|
||||
|
||||
- Keystone 2 Lamarr EVM
|
||||
compatible = "ti,k2l-evm","ti,keystone"
|
||||
compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone"
|
||||
|
||||
- Keystone 2 Edison EVM
|
||||
compatible = "ti,k2e-evm","ti,keystone"
|
||||
compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ representation in the device tree should be done as under:-
|
|||
Required properties:
|
||||
|
||||
- compatible : should be one of
|
||||
"apm,potenza-pmu"
|
||||
"arm,armv8-pmuv3"
|
||||
"arm.cortex-a57-pmu"
|
||||
"arm.cortex-a53-pmu"
|
||||
|
|
|
|||
|
|
@ -17,6 +17,10 @@ Rockchip platforms device tree bindings
|
|||
Required root node properties:
|
||||
- compatible = "radxa,rock", "rockchip,rk3188";
|
||||
|
||||
- Radxa Rock2 Square board:
|
||||
Required root node properties:
|
||||
- compatible = "radxa,rock2-square", "rockchip,rk3288";
|
||||
|
||||
- Firefly Firefly-RK3288 board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
|
||||
|
|
@ -31,6 +35,13 @@ Rockchip platforms device tree bindings
|
|||
Required root node properties:
|
||||
- compatible = "netxeon,r89", "rockchip,rk3288";
|
||||
|
||||
- Google Jaq (Haier Chromebook 11 and more):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
|
||||
"google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
|
||||
"google,veyron-jaq-rev1", "google,veyron-jaq",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Jerry (Hisense Chromebook C11 and more):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
|
||||
|
|
|
|||
|
|
@ -1,27 +0,0 @@
|
|||
* Samsung's Exynos SoC based boards
|
||||
|
||||
Required root node properties:
|
||||
- compatible = should be one or more of the following.
|
||||
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
|
||||
- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
|
||||
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
|
||||
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
|
||||
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
|
||||
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
|
||||
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
|
||||
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
|
||||
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
|
||||
- "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
|
||||
- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
|
||||
- "samsung,sd5v1" - for Exynos5440-based Samsung board.
|
||||
- "samsung,ssdk5440" - for Exynos5440-based Samsung board.
|
||||
|
||||
Optional:
|
||||
- firmware node, specifying presence and type of secure firmware:
|
||||
- compatible: only "samsung,secure-firmware" is currently supported
|
||||
- reg: address of non-secure SYSRAM used for communication with firmware
|
||||
|
||||
firmware@0203F000 {
|
||||
compatible = "samsung,secure-firmware";
|
||||
reg = <0x0203F000 0x1000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
* Samsung's Exynos SoC based boards
|
||||
|
||||
Required root node properties:
|
||||
- compatible = should be one or more of the following.
|
||||
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
|
||||
- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
|
||||
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
|
||||
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
|
||||
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
|
||||
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
|
||||
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
|
||||
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
|
||||
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
|
||||
- "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
|
||||
- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
|
||||
- "samsung,sd5v1" - for Exynos5440-based Samsung board.
|
||||
- "samsung,ssdk5440" - for Exynos5440-based Samsung board.
|
||||
|
||||
* Other companies Exynos SoC based
|
||||
* FriendlyARM
|
||||
- "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
|
||||
TINY4412 board.
|
||||
|
||||
* Google
|
||||
- "google,pi" - for Exynos5800-based Google Peach Pi
|
||||
Rev 10+ board,
|
||||
also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14",
|
||||
"google,pi-rev13", "google,pi-rev12", "google,pi-rev11",
|
||||
"google,pi-rev10", "google,peach".
|
||||
|
||||
- "google,pit" - for Exynos5420-based Google Peach Pit
|
||||
Rev 6+ (Exynos5420),
|
||||
also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14",
|
||||
"google,pit-rev13", "google,pit-rev12", "google,pit-rev11",
|
||||
"google,pit-rev10", "google,pit-rev9", "google,pit-rev8",
|
||||
"google,pit-rev7", "google,pit-rev6", "google,peach".
|
||||
|
||||
- "google,snow-rev4" - for Exynos5250-based Google Snow board,
|
||||
also: "google,snow"
|
||||
- "google,snow-rev5" - for Exynos5250-based Google Snow
|
||||
Rev 5+ board.
|
||||
- "google,spring" - for Exynos5250-based Google Spring board.
|
||||
|
||||
* Hardkernel
|
||||
- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
|
||||
- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
|
||||
- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
|
||||
- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
|
||||
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
|
||||
Odroid XU3 Lite board.
|
||||
- "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
|
||||
|
||||
* Insignal
|
||||
- "insignal,arndale" - for Exynos5250-based Insignal Arndale board.
|
||||
- "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale
|
||||
Octa board.
|
||||
- "insignal,origen" - for Exynos4210-based Insignal Origen board.
|
||||
- "insignal,origen4412 - for Exynos4412-based Insignal Origen board.
|
||||
|
||||
|
||||
Optional nodes:
|
||||
- firmware node, specifying presence and type of secure firmware:
|
||||
- compatible: only "samsung,secure-firmware" is currently supported
|
||||
- reg: address of non-secure SYSRAM used for communication with firmware
|
||||
|
||||
firmware@0203F000 {
|
||||
compatible = "samsung,secure-firmware";
|
||||
reg = <0x0203F000 0x1000>;
|
||||
};
|
||||
|
|
@ -55,3 +55,7 @@ Boards:
|
|||
compatible = "renesas,lager", "renesas,r8a7790"
|
||||
- Marzen
|
||||
compatible = "renesas,marzen", "renesas,r8a7779"
|
||||
- Porter (M2-LCDP)
|
||||
compatible = "renesas,porter", "renesas,r8a7791"
|
||||
- SILK (RTP0RC7794LCB00011S)
|
||||
compatible = "renesas,silk", "renesas,r8a7794"
|
||||
|
|
|
|||
|
|
@ -21,11 +21,14 @@ Example:
|
|||
|
||||
This is the memory-mapped registers for on board FPGA.
|
||||
|
||||
Required properities:
|
||||
Required properties:
|
||||
- compatible: should be a board-specific string followed by a string
|
||||
indicating the type of FPGA. Example:
|
||||
"fsl,<board>-fpga", "fsl,fpga-pixis"
|
||||
"fsl,<board>-fpga", "fsl,fpga-pixis", or
|
||||
"fsl,<board>-fpga", "fsl,fpga-qixis"
|
||||
- reg: should contain the address and the length of the FPGA register set.
|
||||
|
||||
Optional properties:
|
||||
- interrupt-parent: should specify phandle for the interrupt controller.
|
||||
- interrupts: should specify event (wakeup) IRQ.
|
||||
|
||||
|
|
@ -38,6 +41,13 @@ Example (P1022DS):
|
|||
interrupts = <8 8 0 0>;
|
||||
};
|
||||
|
||||
Example (LS2080A-RDB):
|
||||
|
||||
cpld@3,0 {
|
||||
compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
|
||||
reg = <0x3 0 0x10000>;
|
||||
};
|
||||
|
||||
* Freescale BCSR GPIO banks
|
||||
|
||||
Some BCSR registers act as simple GPIO controllers, each such
|
||||
|
|
@ -18,10 +18,14 @@ Required properties :
|
|||
- #clock-cells : shall contain 1
|
||||
- #reset-cells : shall contain 1
|
||||
|
||||
Optional properties :
|
||||
- #power-domain-cells : shall contain 1
|
||||
|
||||
Example:
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,10 +14,14 @@ Required properties :
|
|||
- #clock-cells : shall contain 1
|
||||
- #reset-cells : shall contain 1
|
||||
|
||||
Optional properties :
|
||||
- #power-domain-cells : shall contain 1
|
||||
|
||||
Example:
|
||||
clock-controller@4000000 {
|
||||
compatible = "qcom,mmcc-msm8960";
|
||||
reg = <0x4000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
* Freescale MPC512x/MPC8xxx GPIO controller
|
||||
* Freescale MPC512x/MPC8xxx/Layerscape GPIO controller
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,<soc>-gpio"
|
||||
The following <soc>s are known to be supported:
|
||||
mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq
|
||||
mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq.
|
||||
- reg : Address and length of the register set for the device
|
||||
- interrupts : Should be the port interrupt shared by all 32 pins.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and
|
||||
|
|
|
|||
|
|
@ -3,10 +3,35 @@ Bindings for a fan connected to the PWM lines
|
|||
Required properties:
|
||||
- compatible : "pwm-fan"
|
||||
- pwms : the PWM that is used to control the PWM fan
|
||||
- cooling-levels : PWM duty cycle values in a range from 0 to 255
|
||||
which correspond to thermal cooling states
|
||||
|
||||
Example:
|
||||
pwm-fan {
|
||||
fan0: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
status = "okay";
|
||||
cooling-min-state = <0>;
|
||||
cooling-max-state = <3>;
|
||||
#cooling-cells = <2>;
|
||||
pwms = <&pwm 0 10000 0>;
|
||||
cooling-levels = <0 102 170 230>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
thermal-sensors = <&tmu 0>;
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
cpu_alert1: cpu-alert1 {
|
||||
temperature = <100000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert1>;
|
||||
cooling-device = <&fan0 0 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ Required properties:
|
|||
- clocks: Required if the System MMU is needed to gate its clock.
|
||||
- power-domains: Required if the System MMU is needed to gate its power.
|
||||
Please refer to the following document:
|
||||
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
|
||||
Documentation/devicetree/bindings/power/pd-samsung.txt
|
||||
|
||||
Examples:
|
||||
gsc_0: gsc@13e00000 {
|
||||
|
|
|
|||
|
|
@ -22,6 +22,10 @@ Optional properties:
|
|||
- samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled
|
||||
down. When the system is suspended it will always go down thus triggerring
|
||||
unwanted buck warm reset (setting buck voltages to default values).
|
||||
- samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is
|
||||
connected to the ground so the PMIC must manually set PWRHOLD bit in CTRL1
|
||||
register to turn off the power. Usually the ACOKB is pulled up to VBATT so
|
||||
when PWRHOLD pin goes low, the rising ACOKB will trigger power off.
|
||||
|
||||
Optional nodes:
|
||||
- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768
|
||||
|
|
|
|||
10
Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
Normal file
10
Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
* ARM Juno R1 PCIe interface
|
||||
|
||||
This PCIe host controller is based on PLDA XpressRICH3-AXI IP
|
||||
and thus inherits all the common properties defined in plda,xpressrich3-axi.txt
|
||||
as well as the base properties defined in host-generic-pci.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible: "arm,juno-r1-pcie"
|
||||
- dma-coherent: The host controller bridges the AXI transactions into PCIe bus
|
||||
in a manner that makes the DMA operations to appear coherent to the CPUs.
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
* PLDA XpressRICH3-AXI host controller
|
||||
|
||||
The PLDA XpressRICH3-AXI host controller can be configured in a manner that
|
||||
makes it compliant with the SBSA[1] standard published by ARM Ltd. For those
|
||||
scenarios, the host-generic-pci.txt bindings apply with the following additions
|
||||
to the compatible property:
|
||||
|
||||
Required properties:
|
||||
- compatible: should contain "plda,xpressrich3-axi" to identify the IP used.
|
||||
|
||||
|
||||
[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/
|
||||
|
|
@ -43,9 +43,8 @@ Example:
|
|||
mfc_pd: power-domain@10044060 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044060 0x20>;
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
|
||||
<&clock CLK_MOUT_USER_ACLK333>;
|
||||
clock-names = "oscclk", "pclk0", "clk0";
|
||||
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
|
||||
clock-names = "oscclk", "clk0";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -17,9 +17,9 @@ Required properties:
|
|||
- reg: Address range of the SCPSYS unit
|
||||
- infracfg: must contain a phandle to the infracfg controller
|
||||
- clock, clock-names: clocks according to the common clock binding.
|
||||
The clocks needed "mm" and "mfg". These are the
|
||||
clocks which hardware needs to be enabled before
|
||||
enabling certain power domains.
|
||||
The clocks needed "mm", "mfg", "venc" and "venc_lt".
|
||||
These are the clocks which hardware needs to be enabled
|
||||
before enabling certain power domains.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -30,7 +30,9 @@ Example:
|
|||
infracfg = <&infracfg>;
|
||||
clocks = <&clk26m>,
|
||||
<&topckgen CLK_TOP_MM_SEL>;
|
||||
clock-names = "mfg", "mm";
|
||||
<&topckgen CLK_TOP_VENC_SEL>,
|
||||
<&topckgen CLK_TOP_VENC_LT_SEL>;
|
||||
clock-names = "mfg", "mm", "venc", "venc_lt";
|
||||
};
|
||||
|
||||
Example consumer:
|
||||
|
|
|
|||
57
Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
Normal file
57
Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
Qualcomm Shared Memory Manager binding
|
||||
|
||||
This binding describes the Qualcomm Shared Memory Manager, used to share data
|
||||
between various subsystems and OSes in Qualcomm platforms.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: must be:
|
||||
"qcom,smem"
|
||||
|
||||
- memory-region:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: handle to memory reservation for main SMEM memory region.
|
||||
|
||||
- qcom,rpm-msg-ram:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: handle to RPM message memory resource
|
||||
|
||||
- hwlocks:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: reference to a hwspinlock used to protect allocations from
|
||||
the shared memory
|
||||
|
||||
= EXAMPLE
|
||||
The following example shows the SMEM setup for MSM8974, with a main SMEM region
|
||||
at 0xfa00000 and the RPM message ram at 0xfc428000:
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
smem_region: smem@fa00000 {
|
||||
reg = <0xfa00000 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
smem@fa00000 {
|
||||
compatible = "qcom,smem";
|
||||
|
||||
memory-region = <&smem_region>;
|
||||
qcom,rpm-msg-ram = <&rpm_msg_ram>;
|
||||
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
rpm_msg_ram: memory@fc428000 {
|
||||
compatible = "qcom,rpm-msg-ram";
|
||||
reg = <0xfc428000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -3,10 +3,12 @@ Mediatek MT6577, MT6572 and MT6589 Timers
|
|||
|
||||
Required properties:
|
||||
- compatible should contain:
|
||||
* "mediatek,mt6589-timer" for MT6589 compatible timers
|
||||
* "mediatek,mt6580-timer" for MT6580 compatible timers
|
||||
* "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580,
|
||||
MT6577)
|
||||
* "mediatek,mt6589-timer" for MT6589 compatible timers
|
||||
* "mediatek,mt8127-timer" for MT8127 compatible timers
|
||||
* "mediatek,mt8135-timer" for MT8135 compatible timers
|
||||
* "mediatek,mt8173-timer" for MT8173 compatible timers
|
||||
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers
|
||||
- reg: Should contain location and length for timers register.
|
||||
- clocks: Clocks driving the timer hardware. This list should include two
|
||||
clocks. The order is system clock and as second clock the RTC clock.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
synopsys DWC3 CORE
|
||||
|
||||
DWC3- USB3 CONTROLLER
|
||||
DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
|
||||
as described in 'usb/generic.txt'
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "snps,dwc3"
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ avago Avago Technologies
|
|||
avic Shanghai AVIC Optoelectronics Co., Ltd.
|
||||
axis Axis Communications AB
|
||||
bosch Bosch Sensortec GmbH
|
||||
boundary Boundary Devices Inc.
|
||||
brcm Broadcom Corporation
|
||||
buffalo Buffalo, Inc.
|
||||
calxeda Calxeda
|
||||
|
|
@ -171,6 +172,7 @@ pericom Pericom Technology Inc.
|
|||
phytec PHYTEC Messtechnik GmbH
|
||||
picochip Picochip Ltd
|
||||
plathome Plat'Home Co., Ltd.
|
||||
plda PLDA
|
||||
pixcir PIXCIR MICROELECTRONICS Co., Ltd
|
||||
pulsedlight PulsedLight, Inc
|
||||
powervr PowerVR (deprecated, use img)
|
||||
|
|
@ -228,6 +230,7 @@ toradex Toradex AG
|
|||
toshiba Toshiba Corporation
|
||||
toumaz Toumaz
|
||||
tplink TP-LINK Technologies Co., Ltd.
|
||||
tronfy Tronfy
|
||||
truly Truly Semiconductors Limited
|
||||
upisemi uPI Semiconductor Corp.
|
||||
usi Universal Scientific Industrial Co., Ltd.
|
||||
|
|
|
|||
Loading…
Reference in a new issue