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ARM: DT updates for v4.4

Browse source 
As usual, this is the massive branch we have for each release. Lots of
 various updates and additions of hardware descriptions on existing hardware,
 as well as the usual additions of new boards and SoCs.
 
 This is also the first release where we've started mixing 64- and 32-bit
 DT updates in one branch.
 
 (Specific details on what's actually here and new is pretty easy to tell
 from the diffstat, so there's little point in duplicating listing it here.)
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "As usual, this is the massive branch we have for each release.  Lots
  of various updates and additions of hardware descriptions on existing
  hardware, as well as the usual additions of new boards and SoCs.

  This is also the first release where we've started mixing 64- and
  32-bit DT updates in one branch.

  (Specific details on what's actually here and new is pretty easy to
  tell from the diffstat, so there's little point in duplicating listing
  it here)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits)
  ARM: dts: uniphier: add system-bus-controller nodes
  ARM64: juno: disable NOR flash node by default
  ARM: dts: uniphier: add outer cache controller nodes
  arm64: defconfig: Enable PCI generic host bridge by default
  arm64: Juno: Add support for the PCIe host bridge on Juno R1
  Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
  ARM: dts: uniphier: add I2C aliases for ProXstream2 boards
  dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
  dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
  dts/ls2080a: Update Simulator DTS to add support of various peripherals
  dts/ls2080a: Remove text about writing to Free Software Foundation
  dts/ls2080a: Update DTSI to add support of various peripherals
  doc: DTS: Update DWC3 binding to provide reference to generic bindings
  doc/bindings: Update GPIO devicetree binding documentation for LS2080A
  Documentation/dts: Move FSL board-specific bindings out of /powerpc
  Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards
  arm64: Rename FSL LS2085A SoC support code to LS2080A
  arm64: Use generic Layerscape SoC family naming
  ARM: dts: uniphier: add ProXstream2 Vodka board support
  ARM: dts: uniphier: add ProXstream2 Gentil board support
  ...
This commit is contained in:
Linus Torvalds 2015-11-10 15:06:26 -08:00
commit c0d6fe2f01
433 changed files with 20755 additions and 3428 deletions
Download patch file Download diff file Expand all files Collapse all files

54
arch/arm/boot/dts/Makefile
View file

@ -58,7 +58,9 @@ dtb-$(CONFIG_ARCH_AXXIA) += \
axm5516-amarillo.dtb
dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2835-rpi-b.dtb \
bcm2835-rpi-b-plus.dtb
bcm2835-rpi-b-rev2.dtb \
bcm2835-rpi-b-plus.dtb \
bcm2835-rpi-a-plus.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac56u.dtb \
bcm4708-asus-rt-ac68u.dtb \
@ -72,6 +74,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm47081-buffalo-wzr-900dhp.dtb \
bcm4709-asus-rt-ac87u.dtb \
bcm4709-buffalo-wxr-1900dhp.dtb \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
@ -83,6 +86,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
bcm28155-ap.dtb \
bcm21664-garnet.dtb
dtb-$(CONFIG_ARCH_BCM_NSP) += \
bcm958625k.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
berlin2cd-google-chromecast.dtb \
@ -115,6 +120,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5250-snow-rev5.dtb \
exynos5250-spring.dtb \
exynos5260-xyref5260.dtb \
exynos5410-smdk5410.dtb \
@ -123,6 +129,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5420-smdk5420.dtb \
exynos5422-odroidxu3.dtb \
exynos5422-odroidxu3-lite.dtb \
exynos5422-odroidxu4.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb \
exynos5800-peach-pi.dtb
@ -227,6 +234,9 @@ dtb-$(CONFIG_ARCH_MMP) += \
pxa168-aspenite.dtb \
pxa910-dkb.dtb \
mmp2-brownstone.dtb
dtb-$(CONFIG_MACH_MESON8B) += \
meson8b-mxq.dtb \
meson8b-odroidc1.dtb
dtb-$(CONFIG_ARCH_MOXART) += \
moxart-uc7112lx.dtb
dtb-$(CONFIG_SOC_IMX1) += \
@ -284,6 +294,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw551x.dtb \
imx6dl-gw552x.dtb \
imx6dl-hummingboard.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-pbab01.dtb \
imx6dl-rex-basic.dtb \
@ -313,6 +324,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw552x.dtb \
imx6q-hummingboard.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-rex-pro.dtb \
imx6q-sabreauto.dtb \
@ -446,6 +458,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-base0033.dtb \
am335x-bone.dtb \
am335x-boneblack.dtb \
am335x-bonegreen.dtb \
am335x-sl50.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
@ -470,6 +483,7 @@ dtb-$(CONFIG_SOC_AM43XX) += \
am437x-gp-evm.dtb
dtb-$(CONFIG_SOC_OMAP5) += \
omap5-cm-t54.dtb \
omap5-igep0050.dtb \
omap5-sbc-t54.dtb \
omap5-uevm.dtb
dtb-$(CONFIG_SOC_DRA7XX) += \
@ -506,7 +520,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-evb-rk808.dtb \
rk3288-firefly-beta.dtb \
rk3288-firefly.dtb \
rk3288-popmetal.dtb \
rk3288-r89.dtb \
rk3288-rock2-square.dtb \
rk3288-veyron-jaq.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
@ -532,6 +549,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7790-lager.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7791-porter.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
@ -574,7 +592,9 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-gemei-g9.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
sun4i-a10-inet1.dtb \
sun4i-a10-inet97fv2.dtb \
sun4i-a10-inet9f-rev03.dtb \
sun4i-a10-itead-iteaduino-plus.dtb \
sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \
@ -582,16 +602,23 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-mk802.dtb \
sun4i-a10-mk802ii.dtb \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb
sun4i-a10-pcduino.dtb \
sun4i-a10-pcduino2.dtb \
sun4i-a10-pov-protab2-ips9.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
sun5i-a10s-mk802.dtb \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a10s-wobo-i5.dtb \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-98v-rev2.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-utoo-p66.dtb
sun5i-a13-q8-tablet.dtb \
sun5i-a13-utoo-p66.dtb \
sun5i-r8-chip.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
@ -599,7 +626,11 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-i7.dtb \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31s-cs908.dtb
sun6i-a31s-cs908.dtb \
sun6i-a31s-primo81.dtb \
sun6i-a31s-sina31s.dtb \
sun6i-a31s-sinovoip-bpi-m2.dtb \
sun6i-a31s-yones-toptech-bs1078-v2.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-bananapi.dtb \
sun7i-a20-bananapro.dtb \
@ -609,6 +640,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-micro.dtb \
@ -616,14 +648,18 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-orangepi-mini.dtb \
sun7i-a20-pcduino3.dtb \
sun7i-a20-pcduino3-nano.dtb \
sun7i-a20-wexler-tab7200.dtb
sun7i-a20-wexler-tab7200.dtb \
sun7i-a20-wits-pro-a20-dkt.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-ippo-q8h-v1.2.dtb \
sun8i-a23-q8-tablet.dtb \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
@ -669,7 +705,9 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld6b-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-sld8-ref.dtb
uniphier-ph1-sld8-ref.dtb \
uniphier-proxstream2-gentil.dtb \
uniphier-proxstream2-vodka.dtb
dtb-$(CONFIG_ARCH_VERSATILE) += \
versatile-ab.dtb \
versatile-pb.dtb
@ -699,6 +737,10 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
armada-370-netgear-rn102.dtb \
armada-370-netgear-rn104.dtb \
armada-370-rd.dtb \
armada-370-seagate-nas-2bay.dtb \
armada-370-seagate-nas-4bay.dtb \
armada-370-seagate-personal-cloud.dtb \
armada-370-seagate-personal-cloud-2bay.dtb \
armada-370-synology-ds213j.dtb
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb

48
arch/arm/boot/dts/am335x-base0033.dts
View file

@ -46,39 +46,39 @@
&am33xx_pinmux {
nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
pinctrl-single,pins = <
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
>;
};
nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
pinctrl-single,pins = <
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
>;
};
leds_base_pins: pinmux_leds_base_pins {
pinctrl-single,pins = <
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
>;
};
};

3
arch/arm/boot/dts/am335x-bone-common.dtsi
View file

@ -383,8 +383,7 @@
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&aes {

53
arch/arm/boot/dts/am335x-bonegreen.dts Normal file
View file

@ -0,0 +1,53 @@
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
/ {
model = "TI AM335x BeagleBone Green";
compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
};
&ldo3_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
&mmc1 {
vmmc-supply = <&vmmcsd_fixed>;
};
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
status = "okay";
};
&am33xx_pinmux {
uart2_pins: uart2_pins {
pinctrl-single,pins = <
0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&rtc {
system-power-controller;
};

2
arch/arm/boot/dts/am335x-evm.dts
View file

@ -737,7 +737,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&mmc3 {

2
arch/arm/boot/dts/am335x-evmsk.dts
View file

@ -647,7 +647,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&sham {

40
arch/arm/boot/dts/am335x-igep0033.dtsi
View file

@ -56,41 +56,41 @@
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
>;
};
};

36
arch/arm/boot/dts/am335x-phycore-som.dtsi
View file

@ -29,8 +29,17 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulators {
compatible = "simple-bus";
vcc5v: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
};
@ -233,14 +242,14 @@
#include "tps65910.dtsi"
&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;
vcc1-supply = <&vcc5v>;
vcc2-supply = <&vcc5v>;
vcc3-supply = <&vcc5v>;
vcc4-supply = <&vcc5v>;
vcc5-supply = <&vcc5v>;
vcc6-supply = <&vcc5v>;
vcc7-supply = <&vcc5v>;
vccio-supply = <&vcc5v>;
regulators {
vrtc_reg: regulator@0 {
@ -311,13 +320,6 @@
};
};
&vbat {
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
/* SPI Busses */
&am33xx_pinmux {
spi0_pins: pinmux_spi0 {

13
arch/arm/boot/dts/am335x-wega.dtsi
View file

@ -11,6 +11,17 @@
model = "Phytec AM335x phyBOARD-WEGA";
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
regulators {
compatible = "simple-bus";
vcc3v3: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
/* CAN Busses */
@ -80,7 +91,7 @@
};
&mmc1 {
vmmc-supply = <&vmmc_reg>;
vmmc-supply = <&vcc3v3>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;

31
arch/arm/boot/dts/am437x-gp-evm.dts
View file

@ -304,6 +304,13 @@
>;
};
dcan0_sleep: dcan0_sleep_pins {
pinctrl-single,pins = <
0x178 (PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
0x17c (PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
>;
};
dcan1_default: dcan1_default_pins {
pinctrl-single,pins = <
0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
@ -311,6 +318,13 @@
>;
};
dcan1_sleep: dcan1_sleep_pins {
pinctrl-single,pins = <
0x180 (PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
0x184 (PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
>;
};
vpfe0_pins_default: vpfe0_pins_default {
pinctrl-single,pins = <
0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
@ -581,8 +595,17 @@
attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
/*
* 0x264 represents the offset of padconf register of
* gpio3_22 from am43xx_pinmux base.
*/
interrupts-extended = <&gpio3 22 IRQ_TYPE_NONE>,
<&am43xx_pinmux 0x264>;
interrupt-names = "tsc", "wakeup";
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
wakeup-source;
};
ov2659@30 {
@ -689,7 +712,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
/* eMMC sits on mmc2 */
@ -886,14 +909,16 @@
};
&dcan0 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcan0_default>;
pinctrl-1 = <&dcan0_sleep>;
status = "okay";
};
&dcan1 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcan1_default>;
pinctrl-1 = <&dcan1_sleep>;
status = "okay";
};

2
arch/arm/boot/dts/am437x-idk-evm.dts
View file

@ -325,7 +325,7 @@
pinctrl-1 = <&mmc1_pins_sleep>;
vmmc-supply = <&v3_3d>;
bus-width = <4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&qspi {

2
arch/arm/boot/dts/am437x-sk-evm.dts
View file

@ -563,7 +563,7 @@
vmmc-supply = <&dcdc4>;
bus-width = <4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&usb2_phy1 {

2
arch/arm/boot/dts/am43x-epos-evm.dts
View file

@ -376,7 +376,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&mac {

117
arch/arm/boot/dts/am57xx-beagle-x15.dts
View file

@ -35,6 +35,14 @@
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
compatible = "regulator-fixed";
regulator-name = "aic_dvdd_fixed";
vin-supply = <&vdd_3v3>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vtt_fixed: fixedregulator-vtt {
/* TPS51200 */
compatible = "regulator-fixed";
@ -142,6 +150,32 @@
};
};
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "BeagleBoard-X15";
simple-audio-card,widgets =
"Line", "Line Out",
"Line", "Line In";
simple-audio-card,routing =
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC2L", "Line In",
"MIC2R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp3>;
};
sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3104>;
clocks = <&clkout2_clk>;
};
};
};
&dra7_pmx_core {
@ -326,6 +360,36 @@
0x370 (PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */
>;
};
clkout2_pins_default: clkout2_pins_default {
pinctrl-single,pins = <
0x294 (PIN_OUTPUT_PULLDOWN | MUX_MODE9) /* xref_clk0.clkout2 */
>;
};
clkout2_pins_sleep: clkout2_pins_sleep {
pinctrl-single,pins = <
0x294 (PIN_INPUT | MUX_MODE15) /* xref_clk0.clkout2 */
>;
};
mcasp3_pins_default: mcasp3_pins_default {
pinctrl-single,pins = <
0x324 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
0x328 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
>;
};
mcasp3_pins_sleep: mcasp3_pins_sleep {
pinctrl-single,pins = <
0x324 (PIN_INPUT | MUX_MODE15)
0x328 (PIN_INPUT | MUX_MODE15)
0x32c (PIN_INPUT | MUX_MODE15)
0x330 (PIN_INPUT | MUX_MODE15)
>;
};
};
&i2c1 {
@ -511,6 +575,22 @@
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
tlv320aic3104: tlv320aic3104@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3104";
reg = <0x18>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&clkout2_pins_default>;
pinctrl-1 = <&clkout2_pins_sleep>;
status = "okay";
adc-settle-ms = <40>;
AVDD-supply = <&vdd_3v3>;
IOVDD-supply = <&vdd_3v3>;
DRVDD-supply = <&vdd_3v3>;
DVDD-supply = <&aic_dvdd>;
};
};
&i2c3 {
@ -586,7 +666,7 @@
vmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};
&mmc2 {
@ -709,3 +789,38 @@
&pcie1 {
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins_default>;
pinctrl-1 = <&mcasp3_pins_sleep>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};

3
arch/arm/boot/dts/armada-370-db.dts
View file

@ -74,7 +74,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
internal-regs {
serial@12000 {

3
arch/arm/boot/dts/armada-370-dlink-dns327l.dts
View file

@ -69,7 +69,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";

7
arch/arm/boot/dts/armada-370-mirabox.dts
View file

@ -61,7 +61,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
@ -138,6 +139,10 @@
phy-mode = "rgmii-id";
};
crypto@90000 {
status = "okay";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";

9
arch/arm/boot/dts/armada-370-netgear-rn102.dts
View file

@ -63,7 +63,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
@ -82,6 +83,12 @@
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
rtc@10300 {
status = "disabled";
};
serial@12000 {
status = "okay";
};

9
arch/arm/boot/dts/armada-370-netgear-rn104.dts
View file

@ -63,7 +63,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
@ -82,6 +83,12 @@
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
rtc@10300 {
status = "disabled";
};
serial@12000 {
status = "okay";
};

3
arch/arm/boot/dts/armada-370-rd.dts
View file

@ -74,7 +74,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";

36
arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts Normal file
View file

@ -0,0 +1,36 @@
/*
* Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* Here are some information allowing to identify the device:
*
* Product name : Seagate NAS 2-Bay
* Code name (board/PCB) : Dart 2-Bay
* Model name (case sticker) : SRPD20
* Material desc (product spec) : STCTxxxxxxx
*/
/dts-v1/;
#include "armada-370-seagate-nas-xbay.dtsi"
/ {
model = "Seagate NAS 2-Bay (Dart, SRPD20)";
compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp";
gpio-fan {
gpio-fan,speed-map =
< 0 3
950 2
1400 1
1800 0>;
};
};

133
arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts Normal file
View file

@ -0,0 +1,133 @@
/*
* Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* Here are some information allowing to identify the device:
*
* Product name : Seagate NAS 4-Bay
* Code name (board/PCB) : Dart 4-Bay
* Model name (case sticker) : SRPD40
* Material desc (product spec) : STCUxxxxxxx
*/
/dts-v1/;
#include "armada-370-seagate-nas-xbay.dtsi"
#include <dt-bindings/leds/leds-ns2.h>
/ {
model = "Seagate NAS 4-Bay (Dart, SRPD40)";
compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";
soc {
pcie-controller {
/* SATA AHCI controller 88SE9170 */
pcie@1,0 {
status = "okay";
};
};
internal-regs {
mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
i2c@11000 {
/* I2C GPIO expander (PCA9554A) */
pca9554: pca9554@21 {
compatible = "nxp,pca9554";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
};
};
};
};
regulators {
regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "SATA2 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>;
};
regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "SATA3 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>;
};
};
gpio-leds {
red-sata2 {
label = "dart:red:sata2";
gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
};
red-sata3 {
label = "dart:red:sata3";
gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
};
};
leds-ns2 {
compatible = "lacie,ns2-leds";
white-sata2 {
label = "dart:white:sata2";
cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>;
slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>;
num-modes = <4>;
modes-map = <NS_V2_LED_SATA 0 0
NS_V2_LED_OFF 0 1
NS_V2_LED_ON 1 0
NS_V2_LED_ON 1 1>;
};
white-sata3 {
label = "dart:white:sata3";
cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>;
num-modes = <4>;
modes-map = <NS_V2_LED_SATA 0 0
NS_V2_LED_OFF 0 1
NS_V2_LED_ON 1 0
NS_V2_LED_ON 1 1>;
};
};
gpio-fan {
gpio-fan,speed-map =
< 0 3
800 2
1050 1
1300 0>;
};
};

231
arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi Normal file
View file

@ -0,0 +1,231 @@
/*
* Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* TODO: add support for the white SATA LEDs associated with HDD 0 and 1.
*/
#include "armada-370.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* USB 3.0 bridge ASM1042A */
pcie@2,0 {
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
i2c@11000 {
status = "okay";
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
/* RTC - NXP 8563T (second source) */
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
interrupts = <110>;
};
/* RTC - MCP7940NT */
rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
interrupts = <110>;
};
};
nand@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "u-boot";
reg = <0x0 0x300000>;
};
partition@300000 {
label = "device-tree";
reg = <0x300000 0x20000>;
};
partition@320000 {
label = "linux";
reg = <0x320000 0x2000000>;
};
partition@2320000 {
label = "rootfs";
reg = <0x2320000 0xdce0000>;
};
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA0 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA1 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
};
gpio-fan {
compatible = "gpio-fan";
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH
&gpio2 1 GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@2 {
label = "Backup button";
linux,code = <KEY_OPTION>;
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@3 {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
};
gpio-leds {
compatible = "gpio-leds";
white-power {
label = "dart:white:power";
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
};
red-power {
label = "dart:red:power";
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
};
red-sata0 {
label = "dart:red:sata0";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
red-sata1 {
label = "dart:red:sata1";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
};
};
gpio_poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>;
pinctrl-names = "default";
hdd0_led_sata_pin: hdd0-led-sata-pin {
marvell,pins = "mpp48";
marvell,function = "sata1";
};
hdd0_led_gpio_pin: hdd0-led-gpio-pin {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
hdd1_led_sata_pin: hdd1-led-sata-pin {
marvell,pins = "mpp57";
marvell,function = "sata0";
};
hdd1_led_gpio_pin: hdd1-led-gpio-pin {
marvell,pins = "mpp57";
marvell,function = "gpio";
};
};

51
arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts Normal file
View file

@ -0,0 +1,51 @@
/*
* Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* Here are some information allowing to identify the device:
*
* Product name : Seagate Personal Cloud 2-Bay
* Code name (board/PCB) : Cumulus Max
* Model name (case sticker) : SRN22C
* Material desc (product spec) : STCSxxxxxxx
*/
/dts-v1/;
#include "armada-370-seagate-personal-cloud.dtsi"
/ {
model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)";
compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp";
soc {
internal-regs {
sata@a0000 {
status = "okay";
nr-ports = <2>;
};
};
};
regulators {
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA1 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
};
};

37
arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts Normal file
View file

@ -0,0 +1,37 @@
/*
* Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* Here are some information allowing to identify the device:
*
* Product name : Seagate Personal Cloud
* Code name (board/PCB) : Cumulus
* Model name (case sticker) : SRN21C
* Material desc (product spec) : STCRxxxxxxx
*/
/dts-v1/;
#include "armada-370-seagate-personal-cloud.dtsi"
/ {
model = "Seagate Personal Cloud (Cumulus, SRN21C)";
compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp";
soc {
internal-regs {
sata@a0000 {
status = "okay";
nr-ports = <1>;
};
};
};
};

178
arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi Normal file
View file

@ -0,0 +1,178 @@
/*
* Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay
* (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* TODO: add support for the white SATA LED.
*/
#include "armada-370.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* USB 3.0 Bridge ASM1042A */
pcie@1,0 {
status = "okay";
};
};
internal-regs {
coherency-fabric@20200 {
broken-idle;
};
serial@12000 {
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
spi@10600 {
status = "okay";
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
/* MX25L8006E */
compatible = "mxicy,mx25l8005", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
};
};
};
usb@50000 {
status = "okay";
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "USB Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
};
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA0 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
debounce-interval = <100>;
};
button@2 {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@3 {
label = "USB VBUS error";
linux,code = <KEY_UNKNOWN>;
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
};
gpio-leds {
compatible = "gpio-leds";
red-sata0 {
label = "cumulus:red:sata0";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
gpio_poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
};
};
&pinctrl {
pinctrl-0 = <&sata_led_pin>;
pinctrl-names = "default";
sata_led_pin: sata-led-pin {
marvell,pins = "mpp60";
marvell,function = "sata0";
};
gpio_led_pin: gpio-led-pin {
marvell,pins = "mpp60";
marvell,function = "gpio";
};
};

3
arch/arm/boot/dts/armada-370-synology-ds213j.dts
View file

@ -77,7 +77,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
internal-regs {

37
arch/arm/boot/dts/armada-370.dtsi
View file

@ -256,6 +256,11 @@
reg = <0x20800 0x8>;
};
cpu-config@21000 {
compatible = "marvell,armada-370-cpu-config";
reg = <0x21000 0x8>;
};
audio_controller: audio-controller@30000 {
#sound-dai-cells = <1>;
compatible = "marvell,armada370-audio";
@ -319,6 +324,38 @@
ethernet@74000 {
compatible = "marvell,armada-370-neta";
};
crypto@90000 {
compatible = "marvell,armada-370-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <48>;
clocks = <&gateclk 23>;
clock-names = "cesa0";
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x7e0>;
};
};
crypto_sram: sa-sram {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
reg-names = "sram";
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
/*
* The Armada 370 has an erratum preventing the use of
* the standard workflow for CPU idle support (relying
* on the BootROM code to enter/exit idle state).
* Reserve some amount of the crypto SRAM to put the
* cpuidle workaround.
*/
idle-sram@0 {
reg = <0x0 0x20>;
};
};
};
};

4
arch/arm/boot/dts/armada-375-db.dts
View file

@ -65,7 +65,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {

33
arch/arm/boot/dts/armada-375.dtsi
View file

@ -513,6 +513,21 @@
};
};
crypto@90000 {
compatible = "marvell,armada-375-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 30>, <&gateclk 31>,
<&gateclk 28>, <&gateclk 29>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
sata@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x5000>;
@ -619,5 +634,23 @@
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
clocks = <&gateclk 30>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
clocks = <&gateclk 31>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
};
};

4
arch/arm/boot/dts/armada-385-db-ap.dts
View file

@ -59,7 +59,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi1: spi@10680 {

4
arch/arm/boot/dts/armada-385-linksys.dtsi
View file

@ -57,7 +57,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs {

4
arch/arm/boot/dts/armada-388-db.dts
View file

@ -64,7 +64,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {

19
arch/arm/boot/dts/armada-388-gp.dts
View file

@ -58,7 +58,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
@ -205,8 +207,21 @@
sdhci@d8000 {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
no-1-8-v;
/*
* A388-GP board v1.5 and higher replace
* hitherto card detection method based on GPIO
* with the one using DAT3 pin. As they are
* incompatible, software-based polling is
* enabled with 'broken-cd' property. For boards
* older than v1.5 it can be replaced with:
* 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
* whereas for the newer ones following can be
* used instead:
* 'dat3-cd;'
* 'cd-inverted;'
*/
broken-cd;
wp-inverted;
bus-width = <8>;
status = "okay";

4
arch/arm/boot/dts/armada-388-rd.dts
View file

@ -65,7 +65,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {

33
arch/arm/boot/dts/armada-38x.dtsi
View file

@ -509,6 +509,21 @@
clocks = <&gateclk 4>;
};
crypto@90000 {
compatible = "marvell,armada-38x-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 23>, <&gateclk 21>,
<&gateclk 14>, <&gateclk 16>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
@ -584,6 +599,24 @@
status = "disabled";
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
clocks = <&gateclk 21>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};
};
clocks {

4
arch/arm/boot/dts/armada-xp-axpwifiap.dts
View file

@ -69,7 +69,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";

4
arch/arm/boot/dts/armada-xp-db.dts
View file

@ -75,7 +75,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
devbus-bootcs {
status = "okay";

4
arch/arm/boot/dts/armada-xp-gp.dts
View file

@ -94,7 +94,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
devbus-bootcs {
status = "okay";

4
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
View file

@ -64,7 +64,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";

4
arch/arm/boot/dts/armada-xp-linksys-mamba.dts
View file

@ -69,7 +69,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";

4
arch/arm/boot/dts/armada-xp-matrix.dts
View file

@ -67,7 +67,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
internal-regs {
serial@12000 {

90
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
View file

@ -63,7 +63,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";
@ -88,41 +90,10 @@
};
internal-regs {
/* Two rear eSATA ports */
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
serial@12000 {
status = "okay";
};
mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* Front USB 2.0 port */
usb@50000 {
status = "okay";
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
rtc@10300 {
status = "disabled";
};
i2c@11000 {
@ -130,12 +101,6 @@
clock-frequency = <400000>;
status = "okay";
isl12057: isl12057@68 {
compatible = "isil,isl12057";
reg = <0x68>;
isil,irq2-can-wakeup-machine;
};
/* Controller for rear fan #1 of 3 (Protechnic
* MGT4012XB-O20, 8000RPM) near eSATA port */
g762_fan1: g762@3e {
@ -172,6 +137,49 @@
compatible = "gmt,g751";
reg = <0x4c>;
};
isl12057: isl12057@68 {
compatible = "isil,isl12057";
reg = <0x68>;
isil,irq2-can-wakeup-machine;
};
};
serial@12000 {
status = "okay";
};
/* Front USB 2.0 port */
usb@50000 {
status = "okay";
};
mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* Two rear eSATA ports */
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
nand@d0000 {

4
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View file

@ -65,7 +65,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
devbus-bootcs {
status = "okay";

4
arch/arm/boot/dts/armada-xp-synology-ds414.dts
View file

@ -77,7 +77,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
pcie-controller {
status = "okay";

35
arch/arm/boot/dts/armada-xp.dtsi
View file

@ -184,6 +184,11 @@
reg = <0x20800 0x20>;
};
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
};
eth2: ethernet@30000 {
compatible = "marvell,armada-xp-neta";
reg = <0x30000 0x4000>;
@ -236,6 +241,18 @@
compatible = "marvell,armada-xp-neta";
};
crypto@90000 {
compatible = "marvell,armada-xp-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <48>, <49>;
clocks = <&gateclk 23>, <&gateclk 23>;
clock-names = "cesa0", "cesa1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
@ -256,6 +273,24 @@
};
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
};
clocks {

118
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View file

@ -44,6 +44,7 @@
*/
/dts-v1/;
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
/ {
model = "Atmel SAMA5D2 Xplained";
@ -92,6 +93,8 @@
apb {
spi0: spi@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
m25p80@0 {
@ -102,25 +105,92 @@
};
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default>;
phy-mode = "rmii";
status = "okay";
};
uart1: serial@f8020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
status = "okay";
};
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
status = "okay";
pmic: act8865@5b {
compatible = "active-semi,act8865";
reg = <0x5b>;
active-semi,vsel-high;
status = "okay";
regulators {
vdd_1v35_reg: DCDC_REG1 {
regulator-name = "VDD_1V35";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
vdd_1v2_reg: DCDC_REG2 {
regulator-name = "VDD_1V2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
vdd_3v3_reg: DCDC_REG3 {
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_fuse_reg: LDO_REG1 {
regulator-name = "VDD_FUSE";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
vdd_3v3_lp_reg: LDO_REG2 {
regulator-name = "VDD_3V3_LP";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_led_reg: LDO_REG3 {
regulator-name = "VDD_LED";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_sdhc_1v8_reg: LDO_REG4 {
regulator-name = "VDD_SDHC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
uart3: serial@fc008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_default>;
status = "okay";
};
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
at24@54 {
@ -129,6 +199,54 @@
pagesize = <16>;
};
};
pinctrl@fc038000 {
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_macb0_default: macb0_default {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_spi0_default: spi0_default {
pinmux = <PIN_PA14__SPI0_SPCK>,
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>,
<PIN_PA17__SPI0_NPCS0>;
bias-disable;
};
pinctrl_uart1_default: uart1_default {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
};
pinctrl_uart3_default: uart3_default {
pinmux = <PIN_PB11__URXD3>,
<PIN_PB12__UTXD3>;
bias-disable;
};
};
};
};
};

2
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View file

@ -76,7 +76,7 @@
pmic: act8865@5b {
compatible = "active-semi,act8865";
reg = <0x5b>;
status = "okay";
status = "disabled";
regulators {
vcc_1v8_reg: DCDC_REG1 {

2
arch/arm/boot/dts/at91-sama5d4_xplained.dts
View file

@ -246,7 +246,7 @@
d8 {
label = "d8";
gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
status = "disabled";
default-state = "on";
};
d10 {

27
arch/arm/boot/dts/at91-sama5d4ek.dts
View file

@ -148,6 +148,25 @@
clocks = <&pck2>;
clock-names = "mclk";
};
qt1070:keyboard@1b {
compatible = "qt1070";
reg = <0x1b>;
interrupt-parent = <&pioE>;
interrupts = <25 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qt1070_irq>;
wakeup-source;
};
atmel_mxt_ts@4c {
compatible = "atmel,atmel_mxt_ts";
reg = <0x4c>;
interrupt-parent = <&pioE>;
interrupts = <24 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mxt_ts>;
};
};
macb0: ethernet@f8020000 {
@ -204,6 +223,14 @@
atmel,pins =
<AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
};
pinctrl_qt1070_irq: qt1070_irq {
atmel,pins =
<AT91_PIOE 25 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mxt_ts: mxt_irq {
atmel,pins =
<AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
};

8
arch/arm/boot/dts/at91rm9200.dtsi
View file

@ -97,7 +97,7 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
compatible = "atmel,at91rm9200-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
@ -426,7 +426,7 @@
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
clocks = <&ssc0_clk>;
clock-names = "pclk";
status = "disable"
status = "disabled";
};
ssc1: ssc@fffd4000 {
@ -437,7 +437,7 @@
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
clocks = <&ssc1_clk>;
clock-names = "pclk";
status = "disable"
status = "disabled";
};
ssc2: ssc@fffd8000 {
@ -448,7 +448,7 @@
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
clocks = <&ssc2_clk>;
clock-names = "pclk";
status = "disable"
status = "disabled";
};
macb0: ethernet@fffbc000 {

2
arch/arm/boot/dts/at91sam9260.dtsi
View file

@ -100,7 +100,7 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9260-pmc";
compatible = "atmel,at91sam9260-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;

2
arch/arm/boot/dts/at91sam9261.dtsi
View file

@ -568,7 +568,7 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
compatible = "atmel,at91rm9200-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;

2
arch/arm/boot/dts/at91sam9263.dtsi
View file

@ -93,7 +93,7 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
compatible = "atmel,at91rm9200-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;

2
arch/arm/boot/dts/at91sam9g45.dtsi
View file

@ -114,7 +114,7 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9g45-pmc";
compatible = "atmel,at91sam9g45-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;

2
arch/arm/boot/dts/at91sam9m10g45ek.dts
View file

@ -198,6 +198,8 @@
isi_0: endpoint {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};

2
arch/arm/boot/dts/at91sam9n12.dtsi
View file

@ -97,7 +97,7 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9n12-pmc";
compatible = "atmel,at91sam9n12-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;

8
arch/arm/boot/dts/at91sam9n12ek.dts
View file

@ -71,10 +71,6 @@
};
};
i2c1: i2c@f8014000 {
status = "okay";
};
mmc0: mmc@f0008000 {
pinctrl-0 = <
&pinctrl_board_mmc0
@ -204,13 +200,13 @@
};
d9 {
label = "d6";
label = "d9";
gpios = <&pioB 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "nand-disk";
};
d10 {
label = "d7";
label = "d10";
gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};

2
arch/arm/boot/dts/at91sam9rl.dtsi
View file

@ -814,7 +814,7 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9g45-pmc";
compatible = "atmel,at91sam9g45-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;

5
arch/arm/boot/dts/at91sam9x5.dtsi
View file

@ -68,7 +68,7 @@
adc_op_clk: adc_op_clk{
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <5000000>;
clock-frequency = <1000000>;
};
};
@ -105,7 +105,7 @@
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9x5-pmc";
compatible = "atmel,at91sam9x5-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
@ -1043,6 +1043,7 @@
atmel,adc-channels-used = <0xffff>;
atmel,adc-vref = <3300>;
atmel,adc-startup-time = <40>;
atmel,adc-sample-hold-time = <11>;
atmel,adc-res = <8 10>;
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres";

8
arch/arm/boot/dts/at91sam9x5ek.dtsi
View file

@ -66,6 +66,8 @@
isi_0: endpoint@0 {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};
@ -100,6 +102,12 @@
};
};
adc0: adc@f804c000 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
pinctrl@fffff400 {
camera_sensor {
pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 {

5
arch/arm/boot/dts/axp209.dtsi
View file

@ -89,4 +89,9 @@
regulator-name = "ldo5";
};
};
usb_power_supply: usb_power_supply {
compatible = "x-powers,axp202-usb-power-supply";
status = "disabled";
};
};

143
arch/arm/boot/dts/axp22x.dtsi Normal file
View file

@ -0,0 +1,143 @@
/*
* Copyright 2015 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* AXP221/221s/223 Integrated Power Management Chip
* http://www.x-powers.com/product/AXP22X.php
* http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf
*/
&axp22x {
interrupt-controller;
#interrupt-cells = <1>;
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
reg_dcdc1: dcdc1 {
regulator-name = "dcdc1";
};
reg_dcdc2: dcdc2 {
regulator-name = "dcdc2";
};
reg_dcdc3: dcdc3 {
regulator-name = "dcdc3";
};
reg_dcdc4: dcdc4 {
regulator-name = "dcdc4";
};
reg_dcdc5: dcdc5 {
regulator-name = "dcdc5";
};
reg_dc1sw: dc1sw {
regulator-name = "dc1sw";
};
reg_dc5ldo: dc5ldo {
regulator-name = "dc5ldo";
};
reg_aldo1: aldo1 {
regulator-name = "aldo1";
};
reg_aldo2: aldo2 {
regulator-name = "aldo2";
};
reg_aldo3: aldo3 {
regulator-name = "aldo3";
};
reg_dldo1: dldo1 {
regulator-name = "dldo1";
};
reg_dldo2: dldo2 {
regulator-name = "dldo2";
};
reg_dldo3: dldo3 {
regulator-name = "dldo3";
};
reg_dldo4: dldo4 {
regulator-name = "dldo4";
};
reg_eldo1: eldo1 {
regulator-name = "eldo1";
};
reg_eldo2: eldo2 {
regulator-name = "eldo2";
};
reg_eldo3: eldo3 {
regulator-name = "eldo3";
};
reg_ldo_io0: ldo_io0 {
regulator-name = "ldo_io0";
};
reg_ldo_io1: ldo_io1 {
regulator-name = "ldo_io1";
};
reg_rtc_ldo: rtc_ldo {
/* RTC_LDO is a fixed, always-on regulator */
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "rtc_ldo";
};
};
};

386
arch/arm/boot/dts/bcm-cygnus.dtsi
View file

@ -32,6 +32,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-cygnus.h>
#include "skeleton.dtsi"
@ -54,197 +55,212 @@
/include/ "bcm-cygnus-clock.dtsi"
pinctrl: pinctrl@0x0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
<0x0301d24c 0x2c>;
};
gpio_crmu: gpio@03024800 {
compatible = "brcm,cygnus-crmu-gpio";
reg = <0x03024800 0x50>,
<0x03024008 0x18>;
#gpio-cells = <2>;
gpio-controller;
};
gpio_ccm: gpio@1800a000 {
compatible = "brcm,cygnus-ccm-gpio";
reg = <0x1800a000 0x50>,
<0x0301d164 0x20>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
gpio_asiu: gpio@180a5000 {
compatible = "brcm,cygnus-asiu-gpio";
reg = <0x180a5000 0x668>;
#gpio-cells = <2>;
gpio-controller;
pinmux = <&pinctrl>;
interrupt-controller;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
};
amba {
core {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x1000000>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus", "simple-bus";
interrupt-parent = <&gic>;
ranges;
wdt@18009000 {
compatible = "arm,sp805" , "arm,primecell";
reg = <0x18009000 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-names = "apb_pclk";
timer@20200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x20200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
};
gic: interrupt-controller@21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x21000 0x1000>,
<0x20100 0x100>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;
cache-level = <2>;
};
};
i2c0: i2c@18008000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
axi {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
#size-cells = <1>;
pinctrl: pinctrl@0x0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x30>,
<0x0301d24c 0x2c>;
};
gpio_crmu: gpio@03024800 {
compatible = "brcm,cygnus-crmu-gpio";
reg = <0x03024800 0x50>,
<0x03024008 0x18>;
#gpio-cells = <2>;
gpio-controller;
};
i2c0: i2c@18008000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
wdt0: wdt@18009000 {
compatible = "arm,sp805" , "arm,primecell";
reg = <0x18009000 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-names = "apb_pclk";
};
gpio_ccm: gpio@1800a000 {
compatible = "brcm,cygnus-ccm-gpio";
reg = <0x1800a000 0x50>,
<0x0301d164 0x20>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
i2c1: i2c@1800b000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x1800b000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
pcie0: pcie@18012000 {
compatible = "brcm,iproc-pcie";
reg = <0x18012000 0x1000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x28000000 0 0x00010000
0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
status = "disabled";
};
pcie1: pcie@18013000 {
compatible = "brcm,iproc-pcie";
reg = <0x18013000 0x1000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x48000000 0 0x00010000
0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
status = "disabled";
};
uart0: serial@18020000 {
compatible = "snps,dw-apb-uart";
reg = <0x18020000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-frequency = <100000000>;
status = "disabled";
};
uart1: serial@18021000 {
compatible = "snps,dw-apb-uart";
reg = <0x18021000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-frequency = <100000000>;
status = "disabled";
};
uart2: serial@18022000 {
compatible = "snps,dw-apb-uart";
reg = <0x18020000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-frequency = <100000000>;
status = "disabled";
};
uart3: serial@18023000 {
compatible = "snps,dw-apb-uart";
reg = <0x18023000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-frequency = <100000000>;
status = "disabled";
};
nand: nand@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
<0x18046f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
brcm,nand-has-wp;
};
gpio_asiu: gpio@180a5000 {
compatible = "brcm,cygnus-asiu-gpio";
reg = <0x180a5000 0x668>;
#gpio-cells = <2>;
gpio-controller;
pinmux = <&pinctrl>;
interrupt-controller;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
};
touchscreen: tsc@180a6000 {
compatible = "brcm,iproc-touchscreen";
reg = <0x180a6000 0x40>;
clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
clock-names = "tsc_clk";
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
i2c1: i2c@1800b000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x1800b000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
pcie0: pcie@18012000 {
compatible = "brcm,iproc-pcie";
reg = <0x18012000 0x1000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x28000000 0 0x00010000
0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
status = "disabled";
};
pcie1: pcie@18013000 {
compatible = "brcm,iproc-pcie";
reg = <0x18013000 0x1000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x48000000 0 0x00010000
0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
status = "disabled";
};
uart0: serial@18020000 {
compatible = "snps,dw-apb-uart";
reg = <0x18020000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-frequency = <100000000>;
status = "disabled";
};
uart1: serial@18021000 {
compatible = "snps,dw-apb-uart";
reg = <0x18021000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-frequency = <100000000>;
status = "disabled";
};
uart2: serial@18022000 {
compatible = "snps,dw-apb-uart";
reg = <0x18020000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-frequency = <100000000>;
status = "disabled";
};
uart3: serial@18023000 {
compatible = "snps,dw-apb-uart";
reg = <0x18023000 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&axi81_clk>;
clock-frequency = <100000000>;
status = "disabled";
};
nand: nand@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
brcm,nand-has-wp;
};
gic: interrupt-controller@19021000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x19021000 0x1000>,
<0x19020100 0x100>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x19022000 0x1000>;
cache-unified;
cache-level = <2>;
};
timer@19020200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x19020200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
};
};

119
arch/arm/boot/dts/bcm-nsp.dtsi Normal file
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@ -0,0 +1,119 @@
/*
* BSD LICENSE
*
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "skeleton.dtsi"
/ {
compatible = "brcm,nsp";
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <&gic>;
mpcore {
compatible = "simple-bus";
ranges = <0x00000000 0x19020000 0x00003000>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
};
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x2000 0x1000>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@19021000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x0100 0x100>;
};
timer@19020200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x0200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
periph_clk: periph_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
};
};
axi {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x00001000>;
#address-cells = <1>;
#size-cells = <1>;
uart0: serial@18000300 {
compatible = "ns16550a";
reg = <0x0300 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <62499840>;
status = "disabled";
};
uart1: serial@18000400 {
compatible = "ns16550a";
reg = <0x0400 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <62499840>;
status = "disabled";
};
};
};

30
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts Normal file
View file

@ -0,0 +1,30 @@
/dts-v1/;
#include "bcm2835-rpi.dtsi"
/ {
compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
model = "Raspberry Pi Model A+";
leds {
act {
gpios = <&gpio 47 0>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
/* I2S interface */
i2s_alt0: i2s_alt0 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
};

23
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts Normal file
View file

@ -0,0 +1,23 @@
/dts-v1/;
#include "bcm2835-rpi.dtsi"
/ {
compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
model = "Raspberry Pi Model B rev2";
leds {
act {
gpios = <&gpio 16 1>;
};
};
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
brcm,pins = <28 29 30 31>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
};

8
arch/arm/boot/dts/bcm2835-rpi-b.dts
View file

@ -13,11 +13,5 @@
};
&gpio {
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
/* I2S interface */
i2s_alt2: i2s_alt2 {
brcm,pins = <28 29 30 31>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
pinctrl-0 = <&gpioout &alt0 &alt3>;
};

4
arch/arm/boot/dts/bcm2835-rpi.dtsi
View file

@ -52,6 +52,10 @@
clock-frequency = <100000>;
};
&i2c2 {
status = "okay";
};
&sdhci {
status = "okay";
bus-width = <4>;

64
arch/arm/boot/dts/bcm2835.dtsi
View file

@ -1,4 +1,5 @@
#include <dt-bindings/pinctrl/bcm2835.h>
#include <dt-bindings/clock/bcm2835.h>
#include "skeleton.dtsi"
/ {
@ -21,6 +22,10 @@
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
/* This could be a reference to BCM2835_CLOCK_TIMER,
* but we don't have the driver using the common clock
* support yet.
*/
clock-frequency = <1000000>;
};
@ -57,6 +62,17 @@
reg = <0x7e100000 0x28>;
};
clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
reg = <0x7e101000 0x2000>;
/* CPRMAN derives everything from the platform's
* oscillator.
*/
clocks = <&clk_osc>;
};
rng@7e104000 {
compatible = "brcm,bcm2835-rng";
reg = <0x7e104000 0x10>;
@ -92,11 +108,13 @@
#interrupt-cells = <2>;
};
uart@7e201000 {
uart0: uart@7e201000 {
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
reg = <0x7e201000 0x1000>;
interrupts = <2 25>;
clock-frequency = <3000000>;
clocks = <&clocks BCM2835_CLOCK_UART>,
<&clocks BCM2835_CLOCK_VPU>;
clock-names = "uartclk", "apb_pclk";
arm,primecell-periphid = <0x00241011>;
};
@ -115,7 +133,7 @@
compatible = "brcm,bcm2835-spi";
reg = <0x7e204000 0x1000>;
interrupts = <2 22>;
clocks = <&clk_spi>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -125,7 +143,7 @@
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
clocks = <&clk_i2c>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -135,7 +153,7 @@
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
clocks = <&clk_mmc>;
clocks = <&clocks BCM2835_CLOCK_EMMC>;
status = "disabled";
};
@ -143,7 +161,17 @@
compatible = "brcm,bcm2835-i2c";
reg = <0x7e804000 0x1000>;
interrupts = <2 21>;
clocks = <&clk_i2c>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@7e805000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e805000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -165,28 +193,14 @@
#address-cells = <1>;
#size-cells = <0>;
clk_mmc: clock@0 {
/* The oscillator is the root of the clock tree. */
clk_osc: clock@3 {
compatible = "fixed-clock";
reg = <0>;
reg = <3>;
#clock-cells = <0>;
clock-output-names = "mmc";
clock-frequency = <100000000>;
clock-output-names = "osc";
clock-frequency = <19200000>;
};
clk_i2c: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-output-names = "i2c";
clock-frequency = <250000000>;
};
clk_spi: clock@2 {
compatible = "fixed-clock";
reg = <2>;
#clock-cells = <0>;
clock-output-names = "spi";
clock-frequency = <250000000>;
};
};
};

11
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View file

@ -24,6 +24,17 @@
reg = <0x00000000 0x08000000>;
};
axi@18000000 {
usb3@23000 {
reg = <0x00023000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";

1
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
View file

@ -10,6 +10,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708";

106
arch/arm/boot/dts/bcm4709-netgear-r7000.dts Normal file
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@ -0,0 +1,106 @@
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
* DTS for Netgear R7000
*
* Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708";
model = "Netgear R7000";
chosen {
bootargs = "console=ttyS0,115200";
};
memory {
reg = <0x00000000 0x08000000>;
};
leds {
compatible = "gpio-leds";
power-white {
label = "bcm53xx:white:power";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
power-amber {
label = "bcm53xx:amber:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
5ghz {
label = "bcm53xx:white:5ghz";
gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
2ghz {
label = "bcm53xx:white:2ghz";
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
wps {
label = "bcm53xx:white:wps";
gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-off";
};
wireless {
label = "bcm53xx:white:wireless";
gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-off";
};
usb3 {
label = "bcm53xx:white:usb3";
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
usb2 {
label = "bcm53xx:white:usb2";
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
};
restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
};
};
};
&uart0 {
status = "okay";
};

84
arch/arm/boot/dts/bcm7445.dtsi
View file

@ -143,6 +143,12 @@
brcm,irq-can-wake;
};
aon-ctrl@410000 {
compatible = "brcm,brcmstb-aon-ctrl";
reg = <0x410000 0x200>, <0x410200 0x400>;
reg-names = "aon-ctrl", "aon-sram";
};
nand: nand@3e2800 {
status = "disabled";
#address-cells = <1>;
@ -219,6 +225,84 @@
};
memory_controllers {
compatible = "simple-bus";
ranges = <0x0 0x0 0xf1100000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
memc@0 {
compatible = "brcm,brcmstb-memc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x80000>;
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x800>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy-v240.1";
reg = <0x6000 0x21c>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
reg = <0x8000 0xe4>;
};
};
memc@1 {
compatible = "brcm,brcmstb-memc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80000 0x80000>;
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x800>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy-v240.1";
reg = <0x6000 0x21c>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
reg = <0x8000 0xe4>;
};
};
memc@2 {
compatible = "brcm,brcmstb-memc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x100000 0x80000>;
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
reg = <0x2000 0x800>;
};
ddr-phy@6000 {
compatible = "brcm,brcmstb-ddr-phy-v240.1";
reg = <0x6000 0x21c>;
};
shimphy@8000 {
compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
reg = <0x8000 0xe4>;
};
};
};
sram@ffe00000 {
compatible = "brcm,boot-sram", "mmio-sram";
reg = <0x0 0xffe00000 0x0 0x10000>;
};
smpboot {
compatible = "brcm,brcmstb-smpboot";
syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;

28
arch/arm/boot/dts/bcm911360_entphn.dts
View file

@ -39,19 +39,11 @@
model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
compatible = "brcm,bcm11360", "brcm,cygnus";
aliases {
serial0 = &uart3;
};
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
uart3: serial@18023000 {
status = "okay";
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@ -64,3 +56,23 @@
};
};
};
&uart3 {
status = "okay";
};
&nand {
nandcs@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
};
};

11
arch/arm/boot/dts/bcm911360k.dts
View file

@ -43,11 +43,10 @@
};
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
uart3: serial@18023000 {
status = "okay";
stdout-path = "serial0:115200n8";
};
};
&uart3 {
status = "okay";
};

60
arch/arm/boot/dts/bcm958300k.dts
View file

@ -33,6 +33,7 @@
/dts-v1/;
#include "bcm-cygnus.dtsi"
#include "bcm9hmidc.dtsi"
/ {
model = "Cygnus SVK (BCM958300K)";
@ -43,35 +44,34 @@
};
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
pcie0: pcie@18012000 {
status = "okay";
};
pcie1: pcie@18013000 {
status = "okay";
};
uart3: serial@18023000 {
status = "okay";
};
nand: nand@18046000 {
nandcs@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
};
stdout-path = "serial0:115200n8";
};
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&uart3 {
status = "okay";
};
&nand {
nandcs@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
};
};

44
arch/arm/boot/dts/bcm958305k.dts
View file

@ -33,6 +33,7 @@
/dts-v1/;
#include "bcm-cygnus.dtsi"
#include "bcm9hmidc.dtsi"
/ {
model = "Cygnus Wireless Audio (BCM958305K)";
@ -43,11 +44,42 @@
};
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS0,115200";
};
uart3: serial@18023000 {
status = "okay";
stdout-path = "serial0:115200n8";
};
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&uart3 {
status = "okay";
};
&nand {
nandcs@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
};
};

57
arch/arm/boot/dts/bcm958625k.dts Normal file
View file

@ -0,0 +1,57 @@
/*
* BSD LICENSE
*
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm-nsp.dtsi"
/ {
model = "NorthStar Plus SVK (BCM958625K)";
compatible = "brcm,bcm58625", "brcm,nsp";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};

42
arch/arm/boot/dts/bcm9hmidc.dtsi Normal file
View file

@ -0,0 +1,42 @@
/*
* BSD LICENSE
*
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Broadcom human machine interface daughter card (bcm9hmidc) installed on
* bcm958300k/bcm958305k boards
*/
&touchscreen {
touchscreen-inverted-x;
touchscreen-inverted-y;
status = "okay";
};

3
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
View file

@ -45,7 +45,8 @@
compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {

23
arch/arm/boot/dts/berlin2.dtsi
View file

@ -47,6 +47,12 @@
model = "Marvell Armada 1500 (BG2) SoC";
compatible = "marvell,berlin2", "marvell,berlin";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -57,6 +63,16 @@
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
operating-points = <
/* kHz uV */
1200000 1200000
1000000 1200000
800000 1200000
600000 1200000
>;
};
cpu@1 {
@ -404,6 +420,13 @@
};
};
pwm: pwm@f20000 {
compatible = "marvell,berlin-pwm";
reg = <0xf20000 0x40>;
clocks = <&chip_clk CLKID_CFG>;
#pwm-cells = <3>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;

3
arch/arm/boot/dts/berlin2cd-google-chromecast.dts
View file

@ -46,7 +46,8 @@
compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {

20
arch/arm/boot/dts/berlin2cd.dtsi
View file

@ -47,6 +47,11 @@
model = "Marvell Armada 1500-mini (BG2CD) SoC";
compatible = "marvell,berlin2cd", "marvell,berlin";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -56,6 +61,14 @@
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
operating-points = <
/* kHz uV */
800000 1200000
600000 1200000
>;
};
};
@ -368,6 +381,13 @@
status = "disabled";
};
pwm: pwm@f20000 {
compatible = "marvell,berlin-pwm";
reg = <0xf20000 0x40>;
clocks = <&chip_clk CLKID_CFG>;
#pwm-cells = <3>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;

3
arch/arm/boot/dts/berlin2q-marvell-dmp.dts
View file

@ -49,7 +49,8 @@
};
choosen {
bootargs = "console=ttyS0,115200 earlyprintk";
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
regulators {

23
arch/arm/boot/dts/berlin2q.dtsi
View file

@ -43,6 +43,11 @@
model = "Marvell Armada 1500 pro (BG2-Q) SoC";
compatible = "marvell,berlin2q", "marvell,berlin";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -53,6 +58,17 @@
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
clocks = <&chip_clk CLKID_CPU>;
clock-latency = <100000>;
/* Can be modified by the bootloader */
operating-points = <
/* kHz uV */
1200000 1200000
1000000 1200000
800000 1200000
600000 1200000
>;
};
cpu@1 {
@ -477,6 +493,13 @@
status = "disabled";
};
pwm: pwm@f20000 {
compatible = "marvell,berlin-pwm";
reg = <0xf20000 0x40>;
clocks = <&chip_clk CLKID_CFG>;
#pwm-cells = <3>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;

7
arch/arm/boot/dts/cx92755.dtsi
View file

@ -95,6 +95,13 @@
timeout-sec = <15>;
};
pinctrl: pinctrl@f0000e20 {
compatible = "cnxt,cx92755-pinctrl";
reg = <0xf0000e20 0x100>;
gpio-controller;
#gpio-cells = <2>;
};
uc_regs: syscon@f00003a0 {
compatible = "cnxt,cx92755-uc", "syscon";
reg = <0xf00003a0 0x10>;

9
arch/arm/boot/dts/cx92755_equinox.dts
View file

@ -70,8 +70,17 @@
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&i2c {
status = "okay";
};
&pinctrl {
uart0_default: uart0_active {
pins = "GP_O0", "GP_O1";
function = "client_b";
};
};

17
arch/arm/boot/dts/dove.dtsi
View file

@ -263,12 +263,13 @@
};
crypto: crypto-engine@30000 {
compatible = "marvell,orion-crypto";
reg = <0x30000 0x10000>,
<0xffffe000 0x800>;
reg-names = "regs", "sram";
compatible = "marvell,dove-crypto";
reg = <0x30000 0x10000>;
reg-names = "regs";
interrupts = <31>;
clocks = <&gate_clk 15>;
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x800>;
status = "okay";
};
@ -767,6 +768,14 @@
interrupts = <47>;
status = "disabled";
};
crypto_sram: sa-sram@ffffe000 {
compatible = "mmio-sram";
reg = <0xffffe000 0x800>;
clocks = <&gate_clk 15>;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
};

222
arch/arm/boot/dts/dra7-evm.dts
View file

@ -9,6 +9,8 @@
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
/ {
model = "TI DRA742";
@ -28,13 +30,22 @@
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
mmc2_3v3: fixedregulator-mmc2 {
evm_3v3_sw: fixedregulator-evm_3v3_sw {
compatible = "regulator-fixed";
regulator-name = "mmc2_3v3";
regulator-name = "evm_3v3_sw";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&evm_3v3_sw>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
@ -55,6 +66,86 @@
enable-active-high;
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC3L", "Mic Jack",
"MIC3R", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
system-clock-frequency = <5644800>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&atl_clkin2_ck>;
};
};
leds {
compatible = "gpio-leds";
led@0 {
label = "dra7:usr1";
gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led@1 {
label = "dra7:usr2";
gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led@2 {
label = "dra7:usr3";
gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led@3 {
label = "dra7:usr4";
gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
USER1 {
label = "btnUser1";
linux,code = <BTN_0>;
gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
};
USER2 {
label = "btnUser2";
linux,code = <BTN_1>;
gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
};
};
};
&dra7_pmx_core {
@ -283,6 +374,31 @@
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
atl_pins: pinmux_atl_pins {
pinctrl-single,pins = <
0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
>;
};
mcasp3_pins: pinmux_mcasp3_pins {
pinctrl-single,pins = <
0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
>;
};
mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
pinctrl-single,pins = <
0x324 (MUX_MODE15)
0x328 (MUX_MODE15)
0x32c (MUX_MODE15)
0x330 (MUX_MODE15)
>;
};
};
&i2c1 {
@ -410,6 +526,17 @@
};
};
pcf_lcd: gpio@20 {
compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575";
reg = <0x21>;
@ -422,6 +549,20 @@
#interrupt-cells = <2>;
};
tlv320aic3106: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3_sw>;
IOVDD-supply = <&evm_3v3_sw>;
DRVDD-supply = <&evm_3v3_sw>;
DVDD-supply = <&aic_dvdd>;
};
};
&i2c2 {
@ -429,6 +570,20 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
pcf_hdmi: gpio@26 {
compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
p1 {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "vin6_sel_s0";
};
};
};
&i2c3 {
@ -479,12 +634,12 @@
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 0>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&mmc2_3v3>;
vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
};
@ -707,3 +862,62 @@
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
&atl {
pinctrl-names = "default";
pinctrl-0 = <&atl_pins>;
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins>;
pinctrl-1 = <&mcasp3_sleep_pins>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};

60
arch/arm/boot/dts/dra7.dtsi
View file

@ -292,6 +292,11 @@
#thermal-sensor-cells = <1>;
};
dsp1_system: dsp_system@40d00000 {
compatible = "syscon";
reg = <0x40d00000 0x100>;
};
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
@ -911,6 +916,46 @@
status = "disabled";
};
mmu0_dsp1: mmu@40d01000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x40d01000 0x100>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu0_dsp1";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
status = "disabled";
};
mmu1_dsp1: mmu@40d02000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x40d02000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu1_dsp1";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
status = "disabled";
};
mmu_ipu1: mmu@58882000 {
compatible = "ti,dra7-iommu";
reg = <0x58882000 0x100>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu1";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
status = "disabled";
};
mmu_ipu2: mmu@55082000 {
compatible = "ti,dra7-iommu";
reg = <0x55082000 0x100>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu2";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
status = "disabled";
};
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v3";
regulator-name = "abb_mpu";
@ -1404,6 +1449,21 @@
status = "disabled";
};
mcasp3: mcasp@48468000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp3";
reg = <0x48468000 0x2000>;
reg-names = "mpu";
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
dma-names = "tx", "rx";
clocks = <&mcasp3_ahclkx_mux>;
clock-names = "fck";
status = "disabled";
};
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;

162
arch/arm/boot/dts/dra72-evm.dts
View file

@ -9,6 +9,7 @@
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
/ {
model = "TI DRA722";
@ -30,6 +31,15 @@
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&evm_3v3>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
@ -93,6 +103,40 @@
};
};
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC3L", "Mic Jack",
"MIC3R", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
system-clock-frequency = <5644800>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&atl_clkin2_ck>;
};
};
};
&dra7_pmx_core {
@ -110,6 +154,13 @@
>;
};
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
>;
};
nand_default: nand_default {
pinctrl-single,pins = <
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
@ -220,6 +271,31 @@
0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
>;
};
atl_pins: pinmux_atl_pins {
pinctrl-single,pins = <
0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
>;
};
mcasp3_pins: pinmux_mcasp3_pins {
pinctrl-single,pins = <
0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
>;
};
mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
pinctrl-single,pins = <
0x324 (PIN_INPUT_PULLDOWN | MUX_MODE15)
0x328 (PIN_INPUT_PULLDOWN | MUX_MODE15)
0x32c (PIN_INPUT_PULLDOWN | MUX_MODE15)
0x330 (PIN_INPUT_PULLDOWN | MUX_MODE15)
>;
};
};
&i2c1 {
@ -353,12 +429,21 @@
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
cpsw_sel_s0 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
};
tlv320aic3106: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3>;
IOVDD-supply = <&evm_3v3>;
DRVDD-supply = <&evm_3v3>;
DVDD-supply = <&aic_dvdd>;
};
};
@ -380,6 +465,14 @@
* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
*/
lines-initial-states = <0x0f2b>;
p1 {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "vin6_sel_s0";
};
};
};
@ -514,7 +607,7 @@
* SDCD signal is not being used here - using the fact that GPIO mode
* is a viable alternative
*/
cd-gpios = <&gpio6 27 0>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <192000000>;
};
@ -590,6 +683,7 @@
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
slaves = <1>;
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
};
&cpsw_emac0 {
@ -695,3 +789,59 @@
};
};
};
&atl {
pinctrl-names = "default";
pinctrl-0 = <&atl_pins>;
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins>;
pinctrl-1 = <&mcasp3_sleep_pins>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
};

21
arch/arm/boot/dts/dra72x.dtsi
View file

@ -45,3 +45,24 @@
<&dss_video1_clk>;
clock-names = "fck", "video1_clk";
};
&mailbox5 {
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
};
};
&mailbox6 {
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
};

51
arch/arm/boot/dts/dra74x.dtsi
View file

@ -52,6 +52,11 @@
};
ocp {
dsp2_system: dsp_system@41500000 {
compatible = "syscon";
reg = <0x41500000 0x100>;
};
omap_dwc3_4: omap_dwc3_4@48940000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss4";
@ -76,6 +81,26 @@
dr_mode = "otg";
};
};
mmu0_dsp2: mmu@41501000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x41501000 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu0_dsp2";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
status = "disabled";
};
mmu1_dsp2: mmu@41502000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x41502000 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu1_dsp2";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
status = "disabled";
};
};
};
@ -93,3 +118,29 @@
<&dss_video2_clk>;
clock-names = "fck", "video1_clk", "video2_clk";
};
&mailbox5 {
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
};
};
&mailbox6 {
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
};
};

9
arch/arm/boot/dts/exynos3250-monk.dts
View file

@ -52,13 +52,13 @@
regulator-name = "V_EMMC_2.8V-fixed";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpk0 2 0>;
gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
i2c_max77836: i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&gpd0 2 0>, <&gpd0 3 0>;
gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -161,6 +161,7 @@
};
&exynos_usbphy {
vbus-supply = <&safeout_reg>;
status = "okay";
};
@ -266,14 +267,14 @@
regulator-name = "V_EMMC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
samsung,ext-control-gpios = <&gpk0 2 0>;
samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
};
ldo12_reg: LDO12 {
regulator-name = "V_EMMC_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
samsung,ext-control-gpios = <&gpk0 2 0>;
samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
};
ldo13_reg: LDO13 {

11
arch/arm/boot/dts/exynos3250-rinato.dts
View file

@ -49,7 +49,7 @@
i2c_max77836: i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&gpd0 2 0>, <&gpd0 3 0>;
gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -153,6 +153,7 @@
&exynos_usbphy {
status = "okay";
vbus-supply = <&safeout_reg>;
};
&hsotg {
@ -188,8 +189,8 @@
reg = <0>;
vdd3-supply = <&ldo16_reg>;
vci-supply = <&ldo20_reg>;
reset-gpios = <&gpe0 1 0>;
te-gpios = <&gpx0 6 0>;
reset-gpios = <&gpe0 1 GPIO_ACTIVE_HIGH>;
te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
power-on-delay= <30>;
power-off-delay= <120>;
reset-delay = <5>;
@ -368,14 +369,14 @@
regulator-name = "V_EMMC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
samsung,ext-control-gpios = <&gpk0 2 0>;
samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
};
ldo12_reg: LDO12 {
regulator-name = "V_EMMC_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
samsung,ext-control-gpios = <&gpk0 2 0>;
samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
};
ldo13_reg: LDO13 {

4
arch/arm/boot/dts/exynos3250.dtsi
View file

@ -333,7 +333,7 @@
};
mshc_0: mshc@12510000 {
compatible = "samsung,exynos5250-dw-mshc";
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12510000 0x1000>;
interrupts = <0 142 0>;
clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
@ -345,7 +345,7 @@
};
mshc_1: mshc@12520000 {
compatible = "samsung,exynos5250-dw-mshc";
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12520000 0x1000>;
interrupts = <0 143 0>;
clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;

8
arch/arm/boot/dts/exynos4.dtsi
View file

@ -431,6 +431,8 @@
interrupts = <0 52 0>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 15>, <&pdma0 16>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -440,6 +442,8 @@
interrupts = <0 53 0>;
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 15>, <&pdma1 16>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -449,6 +453,8 @@
interrupts = <0 54 0>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 17>, <&pdma0 18>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -458,6 +464,8 @@
interrupts = <0 55 0>;
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 17>, <&pdma1 18>;
dma-names = "rx", "tx";
status = "disabled";
};

15
arch/arm/boot/dts/exynos4210-origen.dts
View file

@ -16,6 +16,7 @@
/dts-v1/;
#include "exynos4210.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
@ -45,7 +46,7 @@
regulator-name = "VMEM_VDD_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpx1 1 0>;
gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@ -57,35 +58,35 @@
up {
label = "Up";
gpios = <&gpx2 0 1>;
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
gpio-key,wakeup;
};
down {
label = "Down";
gpios = <&gpx2 1 1>;
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
gpio-key,wakeup;
};
back {
label = "Back";
gpios = <&gpx1 7 1>;
gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
gpio-key,wakeup;
};
home {
label = "Home";
gpios = <&gpx1 6 1>;
gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
gpio-key,wakeup;
};
menu {
label = "Menu";
gpios = <&gpx1 5 1>;
gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
gpio-key,wakeup;
};
@ -94,7 +95,7 @@
leds {
compatible = "gpio-leds";
status {
gpios = <&gpx1 3 1>;
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};

3
arch/arm/boot/dts/exynos4210-smdkv310.dts
View file

@ -16,6 +16,7 @@
/dts-v1/;
#include "exynos4210.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Samsung smdkv310 evaluation board based on Exynos4210";
@ -182,7 +183,7 @@
};
&spi_2 {
cs-gpios = <&gpc1 2 0>;
cs-gpios = <&gpc1 2 GPIO_ACTIVE_HIGH>;
status = "okay";
w25x80@0 {

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