From 5c364b0dafb3c33df8ec63073addce8e6ea3d26c Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Sun, 30 May 2021 15:15:38 +0530 Subject: [PATCH] msm: kgsl: Allow access to QDSS only when coresight is enabled Allocate and map QDSS region only when coresight is enabled. Remove apb_pclk from the clock list when coresight is disabled. Change-Id: I9be6e1abeab26af3abe9196b87368ceba9a98d01 Signed-off-by: Harshitha Sai Neelati --- drivers/gpu/msm/adreno_a6xx_gmu.c | 17 +++++++++++++++-- drivers/gpu/msm/adreno_a6xx_rgmu.c | 17 +++++++++++++++-- drivers/gpu/msm/kgsl_iommu.c | 7 ++++--- drivers/gpu/msm/kgsl_pwrctrl.c | 3 +++ 4 files changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 13f8ea7e2c0e..8c7d4f1d05a2 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -2632,7 +2632,7 @@ int a6xx_gmu_probe(struct kgsl_device *device, struct adreno_device *adreno_dev = ADRENO_DEVICE(device); struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); struct resource *res; - int ret; + int ret, i; gmu->pdev = pdev; @@ -2662,7 +2662,20 @@ int a6xx_gmu_probe(struct kgsl_device *device, ret = devm_clk_bulk_get_all(&pdev->dev, &gmu->clks); if (ret < 0) return ret; - + /* + * Voting for apb_pclk will enable power and clocks required for + * QDSS path to function. However, if CORESIGHT is not enabled, + * QDSS is essentially unusable. Hence, if QDSS cannot be used, + * don't vote for this clock. + */ + if (!IS_ENABLED(CONFIG_CORESIGHT)) { + for (i = 0; i < ret; i++) { + if (!strcmp(gmu->clks[i].id, "apb_pclk")) { + gmu->clks[i].clk = NULL; + break; + } + } + } gmu->num_clks = ret; /* Set up GMU IOMMU and shared memory with GMU */ diff --git a/drivers/gpu/msm/adreno_a6xx_rgmu.c b/drivers/gpu/msm/adreno_a6xx_rgmu.c index 0778956378d7..b16399af6af9 100644 --- a/drivers/gpu/msm/adreno_a6xx_rgmu.c +++ b/drivers/gpu/msm/adreno_a6xx_rgmu.c @@ -1248,12 +1248,25 @@ static int a6xx_rgmu_regulators_probe(struct a6xx_rgmu_device *rgmu) static int a6xx_rgmu_clocks_probe(struct a6xx_rgmu_device *rgmu, struct device_node *node) { - int ret; + int ret, i; ret = devm_clk_bulk_get_all(&rgmu->pdev->dev, &rgmu->clks); if (ret < 0) return ret; - + /* + * Voting for apb_pclk will enable power and clocks required for + * QDSS path to function. However, if CORESIGHT is not enabled, + * QDSS is essentially unusable. Hence, if QDSS cannot be used, + * don't vote for this clock. + */ + if (!IS_ENABLED(CONFIG_CORESIGHT)) { + for (i = 0; i < ret; i++) { + if (!strcmp(rgmu->clks[i].id, "apb_pclk")) { + rgmu->clks[i].clk = NULL; + break; + } + } + } rgmu->num_clks = ret; rgmu->gpu_clk = kgsl_of_clk_by_name(rgmu->clks, ret, "core"); diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c index 38f8100e5fc2..945f2a3838e0 100644 --- a/drivers/gpu/msm/kgsl_iommu.c +++ b/drivers/gpu/msm/kgsl_iommu.c @@ -2511,9 +2511,10 @@ int kgsl_iommu_probe(struct kgsl_device *device) */ kgsl_iommu_map_globals(mmu, mmu->defaultpagetable); kgsl_iommu_map_globals(mmu, mmu->lpac_pagetable); - - device->qdss_desc = kgsl_allocate_global_fixed(device, - "qcom,gpu-qdss-stm", "gpu-qdss"); + /* QDSS is supported only when CORESIGHT is enabled */ + if (IS_ENABLED(CONFIG_CORESIGHT)) + device->qdss_desc = kgsl_allocate_global_fixed(device, + "qcom,gpu-qdss-stm", "gpu-qdss"); device->qtimer_desc = kgsl_allocate_global_fixed(device, "qcom,gpu-timer", "gpu-qtimer"); diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c index 2831803a1817..6b9e43ec330d 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.c +++ b/drivers/gpu/msm/kgsl_pwrctrl.c @@ -1426,6 +1426,9 @@ static int _get_clocks(struct kgsl_device *device) for (i = 0; i < KGSL_MAX_CLKS; i++) { if (pwr->grp_clks[i] || strcmp(clocks[i], name)) continue; + /* apb_pclk should only be enabled if CORESIGHT is enabled */ + if (!strcmp(name, "apb_pclk") && !IS_ENABLED(CONFIG_CORESIGHT)) + continue; pwr->grp_clks[i] = devm_clk_get(dev, name);