From c150d993f3e487cf1a3ebf3ac38ecac62f3ec488 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Tue, 11 May 2021 12:24:48 +0800 Subject: [PATCH] msm: ep-pcie: Correct two CAP reg offsets Correct the offsets of L1SUB_CAPABILITY_REG and L1SUB_CONTROL1_REG. Change-Id: I6130a7eab50d85e34d87c28bde3a48c058ee9eee Signed-off-by: Can Guo --- drivers/platform/msm/ep_pcie/ep_pcie_com.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index a9ad61a9f490..db676c486ea3 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -105,8 +105,8 @@ #define PCIE20_CAP_LINKCTRLSTATUS 0x80 #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 #define PCIE20_LINK_CONTROL2_LINK_STATUS2 0xA0 -#define PCIE20_L1SUB_CAPABILITY 0x154 -#define PCIE20_L1SUB_CONTROL1 0x158 +#define PCIE20_L1SUB_CAPABILITY 0x234 +#define PCIE20_L1SUB_CONTROL1 0x238 #define PCIE20_BUS_DISCONNECT_STATUS 0x68c #define PCIE20_ACK_F_ASPM_CTRL_REG 0x70C #define PCIE20_MASK_ACK_N_FTS 0xff00