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iio: adc: exynos_adc: Add support for exynos7

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The ADC on exynos7 is quite similar to ADCv2. The differences are as
follows:
	- exynos7-adc has 8 input channels (as against 10 in ADCv2).
	- exynos7 does not include an ADC PHY control register.
	- Some ADC_CON2 register bits being used in ADCv2 are listed as
	  reserved in exynos7-adc. This results in a different init_hw
	  function for exynos7.

Signed-off-by: Abhilash Kesavan <[email protected]>
Reviewed-by: Chanwoo Choi <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
This commit is contained in:
Abhilash Kesavan 2014-11-01 09:30:43 +05:30 • committed by Jonathan Cameron
commit c1b501564c
2 changed files with 34 additions and 0 deletions
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32
drivers/iio/adc/exynos_adc.c
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@ -390,6 +390,35 @@ static const struct exynos_adc_data exynos3250_adc_data = {
.start_conv = exynos_adc_v2_start_conv,
};
static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
if (info->data->needs_adc_phy)
regmap_write(info->pmu_map, info->data->phy_offset, 1);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info->regs));
con2 = readl(ADC_V2_CON2(info->regs));
con2 &= ~ADC_V2_CON2_C_TIME(7);
con2 |= ADC_V2_CON2_C_TIME(0);
writel(con2, ADC_V2_CON2(info->regs));
/* Enable interrupts */
writel(1, ADC_V2_INT_EN(info->regs));
}
static const struct exynos_adc_data exynos7_adc_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.init_hw = exynos_adc_exynos7_init_hw,
.exit_hw = exynos_adc_v2_exit_hw,
.clear_irq = exynos_adc_v2_clear_irq,
.start_conv = exynos_adc_v2_start_conv,
};
static const struct of_device_id exynos_adc_match[] = {
{
.compatible = "samsung,s3c2410-adc",
@ -415,6 +444,9 @@ static const struct of_device_id exynos_adc_match[] = {
}, {
.compatible = "samsung,exynos3250-adc",
.data = &exynos3250_adc_data,
}, {
.compatible = "samsung,exynos7-adc",
.data = &exynos7_adc_data,
},
{},
};