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- mt7622:
- add EINT support - add gpio-ranges property to pinctrl - add earlycon to rfb1 to find boot errros more easily - fix uart clock - add iommu and smi bindings - mt6797: - add support for the 96 board x20 development board - fix cooling-cells of mt7622 and mt8173 -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAltU6hoXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00MQTQ/+JI1N6YWXFKkl6NqGFlFd5Spj oLdlnagqc45b368eEKj+wBtbidgryhLXdPB62dSCQGABt9Id0WA+5fbTvq7xkvw7 cU8pNV0SPn5+mw2NzQfCgRtHyFEn8u+pGCZkn9CwX7yjk9mSWWKpFANJYy3isqPD hch8Pne5c1MtB1X9MVbrdo6IKuscdD8isXuGMEWMDyKq0VniOzC+uVa/uWDBdp++ C31OoJE6KQmJj3CJPTUM41DfiwXUfJro/Prfy0xHhoZ6qctJmkuHeCZUfbwBIGSQ xGBaN6C0AmyPzxfc56C2lVOGrTEy5LU7CgMYnMIvDQjAhREKl0nQj/E/F5YDQP/z BPDGDu+GhKi4xHNwf1ZchDLkiALOPPM7tKsorxcWNAxlKHV/0Gz737Twj7SaiWNn GrRNDrfyG1L3Lk3aJsPQ/S7IzTSQWmhXCFPgQKX86qijl/FfVtAEg79Mv1ay0Ii1 8uV9KnDQqiaElZRFxfeOF7oCsK1I4ugcDA7TmsWzk6diApO6w+v9mX8tTcgYetpv a80k7ymJEStfMSBr3p3mRs5b8dGC8940yik332YzPMLufJ6ocBjqpzgEUgx9S5kk dkYPV80CrtEYE5VmvjJjcQSroR6RNxjuMvwnsBxj0sH/KuUMFPoh+9qyXzR68g5l X/pJ6H5271ek+qPOIx0= =+G4b -----END PGP SIGNATURE----- Merge tag 'v4.18-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt - mt7622: - add EINT support - add gpio-ranges property to pinctrl - add earlycon to rfb1 to find boot errros more easily - fix uart clock - add iommu and smi bindings - mt6797: - add support for the 96 board x20 development board - fix cooling-cells of mt7622 and mt8173 * tag 'v4.18-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: Add Mediatek X20 Development Board support dt-bindings: arm: mediatek: Document Mediatek X20 Development Board dt-bindings: mediatek: Add binding for mt2712 IOMMU and SMI arm64: dts: mt7622: update a clock property for UART0 arm64: dts: mt7622: add earlycon to mt7622-rfb1 board arm64: dts: mt7622: use gpio-ranges to pinctrl device arm64: dts: mediatek: Add missing cooling device properties for CPUs arm64: dts: mt7622: add EINT support to pinctrl Signed-off-by: Olof Johansson <[email protected]>
This commit is contained in:
Olof Johansson
commit
c1c0f486d9
10 changed files with 157 additions and 10 deletions
95
include/dt-bindings/memory/mt2712-larb-port.h
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include/dt-bindings/memory/mt2712-larb-port.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Yong Wu <yong.wu@mediatek.com>
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*/
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#ifndef __DTS_IOMMU_PORT_MT2712_H
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#define __DTS_IOMMU_PORT_MT2712_H
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#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
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#define M4U_LARB0_ID 0
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#define M4U_LARB1_ID 1
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#define M4U_LARB2_ID 2
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#define M4U_LARB3_ID 3
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#define M4U_LARB4_ID 4
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#define M4U_LARB5_ID 5
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#define M4U_LARB6_ID 6
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#define M4U_LARB7_ID 7
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#define M4U_LARB8_ID 8
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#define M4U_LARB9_ID 9
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/* larb0 */
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#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
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#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
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#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
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#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
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#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
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#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
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#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
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#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7)
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/* larb1 */
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#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
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#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
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#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
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#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
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#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
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#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
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#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
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#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7)
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#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
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#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9)
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#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10)
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/* larb2 */
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#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0)
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#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1)
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#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2)
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/* larb3 */
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#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
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#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
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#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
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#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
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#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
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#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5)
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#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6)
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#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7)
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#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8)
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/* larb4 */
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#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0)
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#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1)
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#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2)
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#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3)
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#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4)
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#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5)
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#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6)
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/* larb5 */
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#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0)
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#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1)
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#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2)
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#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3)
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/* larb6 */
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#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0)
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#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1)
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#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2)
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#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3)
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/* larb7 */
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#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0)
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#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1)
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/* larb8 */
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#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0)
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#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1)
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#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2)
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/* larb9 */
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#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0)
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#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1)
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#endif
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