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clk: tegra: Use the proper parent for plld_dsi

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The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.

Fixes: b270491eb9 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: Thierry Reding <[email protected]>
This commit is contained in:
Thierry Reding 2015-03-26 17:53:01 +01:00
commit c1d676cec5
2 changed files with 9 additions and 7 deletions
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2
include/dt-bindings/clock/tegra124-car-common.h
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@ -297,7 +297,7 @@
#define TEGRA124_CLK_PLL_C4 270
#define TEGRA124_CLK_PLL_DP 271
#define TEGRA124_CLK_PLL_E_MUX 272
#define TEGRA124_CLK_PLLD_DSI 273
#define TEGRA124_CLK_PLL_D_DSI_OUT 273
/* 274 */
/* 275 */
/* 276 */