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serial: msm_geni_serial: Manage HSUART clocks when read HW Ver

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This change is to make sure UART doesn't turn on/off clocks for
console usecase. HSUART tries to store firmware version for debug
purpose which needs clocks to be ON, hence keep reading of FW
version only for HSUART.

Change-Id: I95025872852df3eb5b8252dfe1cc6f5be95586be
Signed-off-by: Mukesh Kumar Savaliya <[email protected]>
This commit is contained in:
Mukesh Kumar Savaliya 2020-02-07 04:29:18 +05:30
commit c1d740e838
1 changed files with 12 additions and 17 deletions
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33
drivers/tty/serial/msm_geni_serial.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/bitmap.h>
@ -170,6 +170,7 @@ struct msm_geni_serial_port {
struct msm_geni_serial_ver_info ver_info;
u32 cur_tx_remaining;
bool startup_in_progress;
bool is_console;
};
static const struct uart_ops msm_geni_serial_pops;
@ -1992,10 +1993,6 @@ static void msm_geni_serial_set_termios(struct uart_port *uport,
unsigned long clk_rate;
unsigned long flags;
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);
geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);
if (!uart_console(uport)) {
int ret = msm_geni_serial_power_on(uport);
@ -2334,10 +2331,6 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev,
*/
msm_geni_serial_poll_cancel_tx(uport);
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);
geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);
se_get_packing_config(8, 1, false, &cfg0, &cfg1);
geni_se_init(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1),
(DEF_FIFO_DEPTH_WORDS - 2));
@ -2530,7 +2523,9 @@ static int msm_geni_serial_get_ver_info(struct uart_port *uport)
int hw_ver, ret = 0;
struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
se_geni_clks_on(&msm_port->serial_rsc);
/* clks_on/off only for HSUART, as console remains actve */
if (!msm_port->is_console)
se_geni_clks_on(&msm_port->serial_rsc);
/* Basic HW and FW info */
if (unlikely(get_se_proto(uport->membase) != UART)) {
dev_err(uport->dev, "%s: Invalid FW %d loaded.\n",
@ -2558,7 +2553,8 @@ static int msm_geni_serial_get_ver_info(struct uart_port *uport)
msm_port->ver_info.hw_minor_ver,
msm_port->ver_info.hw_step_ver);
exit_ver_info:
se_geni_clks_off(&msm_port->serial_rsc);
if (!msm_port->is_console)
se_geni_clks_off(&msm_port->serial_rsc);
return ret;
}
@ -2649,6 +2645,7 @@ static int msm_geni_serial_probe(struct platform_device *pdev)
goto exit_geni_serial_probe;
dev_port->serial_rsc.ctrl_dev = &pdev->dev;
dev_port->is_console = is_console;
if (of_property_read_u32(pdev->dev.of_node, "qcom,wakeup-byte",
&wake_char)) {
@ -2782,10 +2779,6 @@ static int msm_geni_serial_probe(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev);
}
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);
geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);
geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);
dev_info(&pdev->dev, "Serial port%d added.FifoSize %d is_console%d\n",
line, uport->fifosize, is_console);
device_create_file(uport->dev, &dev_attr_loopback);
@ -2793,11 +2786,13 @@ static int msm_geni_serial_probe(struct platform_device *pdev)
device_create_file(uport->dev, &dev_attr_ver_info);
msm_geni_serial_debug_init(uport, is_console);
dev_port->port_setup = false;
ret = msm_geni_serial_get_ver_info(uport);
if (ret)
goto exit_geni_serial_probe;
return uart_add_one_port(drv, uport);
ret = msm_geni_serial_get_ver_info(uport);
if (ret) {
dev_err(&pdev->dev, "Failed to Read FW ver: %d\n", ret);
goto exit_geni_serial_probe;
}
return uart_add_one_port(drv, uport);
exit_geni_serial_probe:
return ret;
}