From c2048ddbed4c4f5e49caf643a627718fd489023b Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 17 Sep 2020 18:01:52 +0530 Subject: [PATCH] ARM: dts: msm: Add BLSP DTSI nodes on sdxlemur Add BLSP(I2C, SPI and UART) DTSI nodes on sdxlemur Change-Id: I7f6b1ce3ec27421500a5b52072b202c56fcdd618 --- qcom/sdxlemur-blsp.dtsi | 545 ++++++++++++++++++++++ qcom/sdxlemur-pinctrl.dtsi | 903 +++++++++++++++++++++++++++++++++++++ qcom/sdxlemur.dtsi | 3 +- 3 files changed, 1450 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-blsp.dtsi diff --git a/qcom/sdxlemur-blsp.dtsi b/qcom/sdxlemur-blsp.dtsi new file mode 100644 index 000000000000..997db6b37078 --- /dev/null +++ b/qcom/sdxlemur-blsp.dtsi @@ -0,0 +1,545 @@ +#include "sdxlemur-pinctrl.dtsi" + +/ { + aliases { + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + }; +}; + +&soc { + dma_blsp1: qcom,sps-dma@804000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x804000 0x23000>; + interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@835000 { /* BLSP1 QUP1: GPIO: 2,3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x835000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@836000 { /* BLSP1 QUP2: GPIO: 6,7 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x836000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@837000 { /* BLSP1 QUP3: GPIO: 10,11 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x837000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@838000 { /* BLSP1 QUP4: GPIO: 84,85 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x838000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@835000 { /* BLSP1 QUP1: GPIO: 82,83 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x835000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@836000 { /* BLSP1 QUP2: GPIO: 65,66 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x836000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + i2c_7: i2c@838000 { /* BLSP1 QUP4 GPIO: 18,19 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x838000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_7_active>; + pinctrl-1 = <&i2c_7_sleep>; + status = "disabled"; + }; + + spi_1: spi@835000 { /* BLSP1 QUP1: GPIO: 80,81,82,83 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x835000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_2: spi@836000 { /* BLSP1 QUP2: GPIO: 4,5,6,7 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x836000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_3: spi@837000 { /* BLSP1 QUP3: GPIO: 8,9,10,11 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x837000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_4: spi@838000 { /* BLSP1 QUP4: GPIO: 16,17,18,19 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x838000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; + status = "disabled"; + }; + + blsp1_uart1a_hs: uarta@82f000 { /* BLSP1 UART1: GPIO: 0,1,2,3 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x82f000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 24 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 1 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1a_tx_sleep>, + <&blsp1_uart1a_rxcts_sleep>, <&blsp1_uart1a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart1a_tx_active>, + <&blsp1_uart1a_rxcts_active>, + <&blsp1_uart1a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart1b_hs: uartb@82f000 { /* BLSP1 UART1: GPIO: 48,49,80,81 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x82f000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 24 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 49 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1b_tx_sleep>, + <&blsp1_uart1b_rxcts_sleep>, <&blsp1_uart1b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart1b_tx_active>, + <&blsp1_uart1b_rxcts_active>, + <&blsp1_uart1b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart2a_hs: uarta@830000 { /* BLSP1 UART2: GPIO: 4,5,6,7 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x830000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 25 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 5 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2a_tx_sleep>, + <&blsp1_uart2a_rxcts_sleep>, <&blsp1_uart2a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart2a_tx_active>, + <&blsp1_uart2a_rxcts_active>, + <&blsp1_uart2a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart2b_hs: uartb@830000 { /* BLSP1 UART2: GPIO: 63,64,65,66 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x830000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 25 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 64 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2b_tx_sleep>,<&blsp1_uart2b_rx_sleep>, + <&blsp1_uart2b_cts_sleep>, <&blsp1_uart2b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart2b_tx_active>, + <&blsp1_uart2b_rxcts_active>, + <&blsp1_uart2b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@831000 { /* BLSP1 UART3: GPIO: 8,9,10,11 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x831000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 26 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 9 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_tx_sleep>, + <&blsp1_uart3_rxcts_sleep>, <&blsp1_uart3_rfr_sleep>; + pinctrl-1 = <&blsp1_uart3_tx_active>, + <&blsp1_uart3_rxcts_active>, + <&blsp1_uart3_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart4a_hs: uarta@832000 { /* BLSP1 UART4: GPIO: 22,23,48,49 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x832000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 27 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 49 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4a_tx_sleep>, + <&blsp1_uart4a_rxcts_sleep>, <&blsp1_uart4a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4a_tx_active>, + <&blsp1_uart4a_rxcts_active>, + <&blsp1_uart4a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart4b_hs: uartb@832000 { /* BLSP1 UART4: GPIO: 16,17,18,19 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x832000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 27 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 17 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4b_tx_sleep>, + <&blsp1_uart4b_rxcts_sleep>, <&blsp1_uart4b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4b_tx_active>, + <&blsp1_uart4b_rxcts_active>, + <&blsp1_uart4b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + +}; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 771cf1df3a0f..fde920065f0b 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -93,5 +93,908 @@ }; }; }; + + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio84", "gpio85"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + mux { + pins = "gpio82", "gpio83"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + mux { + pins = "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + mux { + pins = "gpio65", "gpio66"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + mux { + pins = "gpio65", "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_7 { + i2c_7_active: i2c_7_active { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_7_sleep: i2c_7_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + blsp1_uart1a: blsp1_uart1a { + blsp1_uart1a_tx_active: blsp1_uart1a_tx_active { + mux { + pins = "gpio0"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1a_rxcts_active: blsp1_uart1a_rxcts_active { + mux { + pins = "gpio1", "gpio2"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rfr_active: blsp1_uart1a_rfr_active { + mux { + pins = "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart1a_tx_sleep: blsp1_uart1a_tx_sleep { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1a_rxcts_sleep: blsp1_uart1a_rxcts_sleep { + mux { + pins = "gpio1", "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rfr_sleep: blsp1_uart1a_rfr_sleep { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + + blsp1_uart1b: blsp1_uart1b { + blsp1_uart1b_tx_active: blsp1b_uart1_tx_active { + mux { + pins = "gpio48"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1b_rxcts_active: blsp1b_uart1_rxcts_active { + mux { + pins = "gpio49", "gpio80"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio49", "gpio80"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rfr_active: blsp1_uart1b_rfr_active { + mux { + pins = "gpio81"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart1b_tx_sleep: blsp1_uart1b_tx_sleep { + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1b_rxcts_sleep: blsp1_uart1b_rxcts_sleep { + mux { + pins = "gpio49", "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio80"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rfr_sleep: blsp1b_uart1_rfr_sleep { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart2a: blsp1_uart2a { + blsp1_uart2a_tx_active: blsp1_uart2a_tx_active { + mux { + pins = "gpio4"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2a_rxcts_active: blsp1_uart2a_rxcts_active { + mux { + pins = "gpio5", "gpio6"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio5", "gpio6"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rfr_active: blsp1_uart2a_rfr_active { + mux { + pins = "gpio7"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart2a_tx_sleep: blsp1_uart2a_tx_sleep { + mux { + pins = "gpio4"; + function = "gpio"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2a_rxcts_sleep: blsp1_uart2a_rxcts_sleep { + mux { + pins = "gpio5", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio5", "gpio6"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rfr_sleep: blsp1_uart2a_rfr_sleep { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart2b: blsp1_uart2b { + blsp1_uart2b_tx_active: blsp1_uart2b_tx_active { + mux { + pins = "gpio63"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2b_rxcts_active: blsp1_uart2b_rxcts_active { + mux { + pins = "gpio64", "gpio65"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_rfr_active: blsp1_uart2b_rfr_active { + mux { + pins = "gpio66"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart2b_tx_sleep: blsp1_uart2b_tx_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; + + blsp1_uart2b_rx_sleep: blsp1_uart2b_rx_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + blsp1_uart2b_cts_sleep: blsp1_uart2b_cts_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + + blsp1_uart2b_rfr_sleep: blsp1_uart2b_rfr_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + + blsp1_uart3: blsp1_uart3 { + blsp1_uart3_tx_active: blsp1_uart3_tx_active { + mux { + pins = "gpio8"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active { + mux { + pins = "gpio9", "gpio10"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_active: blsp1_uart3_rfr_active { + mux { + pins = "gpio11"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart4a: blsp1_uart4a { + blsp1_uart4a_tx_active: blsp1_uart4a_tx_active { + mux { + pins = "gpio48"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4a_rxcts_active: blsp1_uart4a_rxcts_active { + mux { + pins = "gpio49", "gpio22"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio49", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rfr_active: blsp1_uart4a_rfr_active { + mux { + pins = "gpio23"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart4a_tx_sleep: blsp1_uart4a_tx_sleep { + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4a_rxcts_sleep: blsp1_uart4a_rxcts_sleep { + mux { + pins = "gpio49", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rfr_sleep: blsp1_uart4a_rfr_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart4b: blsp1_uart4b { + blsp1_uart4b_tx_active: blsp1_uart4b_tx_active { + mux { + pins = "gpio16"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4b_rxcts_active: blsp1_uart4b_rxcts_active { + mux { + pins = "gpio17", "gpio18"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rfr_active: blsp1_uart4b_rfr_active { + mux { + pins = "gpio19"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart4b_tx_sleep: blsp1_uart4b_tx_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4b_rxcts_sleep: blsp1_uart4b_rxcts_sleep { + mux { + pins = "gpio17", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rfr_sleep: blsp1_uart4b_rfr_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; }; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a9a6ec23a414..93f175cfad5c 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -376,7 +376,7 @@ serial_uart: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x831000 0x200>; - interrupts = <0 26 0>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -678,3 +678,4 @@ #include "sdxlemur-usb.dtsi" #include "sdxlemur-pm.dtsi" #include "sdxlemur-pcie.dtsi" +#include "sdxlemur-blsp.dtsi"