From ac8b6dfbf2f9524f50a4b6735b7c8b36a4dd908e Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 3 Sep 2020 10:56:00 -0700 Subject: [PATCH] ARM: dts: msm: update phandle for pcie_pipe_clk_ext_src for sdxlemur Using wrong phandle for PCIe root complex pcie_pipe_clk_ext_src. Therefore, update to use the correct phandle on sdxlemur. Change-Id: I9cb3a9b362dd72a1d08be7e6de4c6db7d4d86a17 --- qcom/sdxlemur-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index b411c80be87f..753019979959 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -70,7 +70,7 @@ <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_RCHNG_PHY_CLK>, <&gcc GCC_PCIE_PIPE_CLK_SRC>, - <&gcc PCIE_PIPE_CLK>; + <&pcie_pipe_clk>; clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",