mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: arm-soc: Updates for Marvell mvebu/kirkwood
This is a branch with updates for Marvell's mvebu/kirkwood platforms. They came in late-ish, and were heavily interdependent such that it didn't make sense to split them up across the cross-platform topic branches. So here they are (for the second release in a row) in a branch on their own. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJQy5i9AAoJEIwa5zzehBx3ZskP/2wxjbwEaNdnR+7j8595bTaa GYq8qJ4lUCOKmSqp3bQkg/Plm2D88p78BO5qTm2io527gl10HemzCiGaejclujIw sDFZPAE8K0Z8p0gQcBNlRZNuI3J1N6IKRqYH5SIJ2vWmBMfO7nKRR9nmTiDpm5bx IcuKX2u/mhyXWN+F0EcHqcupH1K+mdzyGdIQk80Tyqni+UTN+pd0efLM6WL4SFJM 5fj64dDFpVDA8t+O2Avz8p+lx07vkSy2wIXWt7Ik9BVtsyZQecn+9lpl8FvcrSK/ MgL3QO4kqDpJDs88M7DJURU1/EdsWZc32M63avctaWnGWItQAbOJYBDmZTlng08x ZGrKOgf/I6le7wEpnzdag9ymI/rAL8I0755FkfXxf1R7/X40b+t8/61J/ddOKTDs 1sTVt+eKyyIMWle4V4zENa03goVBApCIEXcmnuFisFNbBY6azV31inJEp/3PvpgE GeMBfxBDkvn+03LkRFcZlhTeDsNTdctD+sfgrNPaQf5bZGIvEz87vgfNTIiaU3GA Vd5aiainVDQgmpoFfRG6391gdFlF2l9d67LoG4ClCjn4WL+UxcTRuzBW/liORpUO E7CwMHtPq6eoGKywiKMFRzY2QRIKZRkxrC2PCJ/1V9mbIGwgaD/3BQ2/czwrnc8q 1gnxWx8E5SKEGcDJXD+6 =7luC -----END PGP SIGNATURE----- Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson: "This is a branch with updates for Marvell's mvebu/kirkwood platforms. They came in late-ish, and were heavily interdependent such that it didn't make sense to split them up across the cross-platform topic branches. So here they are (for the second release in a row) in a branch on their own." * tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits) arm: l2x0: add aurora related properties to OF binding arm: mvebu: add Aurora L2 Cache Controller to the DT arm: mvebu: add L2 cache support dma: mv_xor: fix error handling path dma: mv_xor: fix error checking of irq_of_parse_and_map() dma: mv_xor: use request_irq() instead of devm_request_irq() dma: mv_xor: clear the window override control registers arm: mvebu: fix address decoding armada_cfg_base() function ARM: mvebu: update defconfig with I2C and RTC support ARM: mvebu: Add SATA support for OpenBlocks AX3-4 ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4 ARM: mvebu: Add support for I2C on OpenBlocks AX3-4 ARM: mvebu: Add support for I2C controllers in Armada 370/XP arm: mvebu: Add hardware I/O Coherency support arm: plat-orion: Add coherency attribute when setup mbus target arm: dma mapping: Export a dma ops function arm_dma_set_mask arm: mvebu: Add SMP support for Armada XP arm: mm: Add support for PJ4B cpu and init routines arm: mvebu: Add IPI support via doorbells arm: mvebu: Add initial support for power managmement service unit ...
This commit is contained in:
Linus Torvalds
commit
c2714334b9
76 changed files with 6530 additions and 414 deletions
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@ -64,3 +64,5 @@ config CLK_TWL6040
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as functional clock.
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endmenu
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source "drivers/clk/mvebu/Kconfig"
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@ -13,6 +13,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
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obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o
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obj-$(CONFIG_PLAT_ORION) += mvebu/
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ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_ARCH_MMP) += mmp/
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endif
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8
drivers/clk/mvebu/Kconfig
Normal file
8
drivers/clk/mvebu/Kconfig
Normal file
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@ -0,0 +1,8 @@
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config MVEBU_CLK_CORE
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bool
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config MVEBU_CLK_CPU
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bool
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config MVEBU_CLK_GATING
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bool
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3
drivers/clk/mvebu/Makefile
Normal file
3
drivers/clk/mvebu/Makefile
Normal file
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@ -0,0 +1,3 @@
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obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
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obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
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obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
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675
drivers/clk/mvebu/clk-core.c
Normal file
675
drivers/clk/mvebu/clk-core.c
Normal file
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@ -0,0 +1,675 @@
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/*
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* Marvell EBU clock core handling defined at reset
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "clk-core.h"
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struct core_ratio {
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int id;
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const char *name;
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};
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struct core_clocks {
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u32 (*get_tclk_freq)(void __iomem *sar);
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u32 (*get_cpu_freq)(void __iomem *sar);
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void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
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const struct core_ratio *ratios;
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int num_ratios;
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};
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static struct clk_onecell_data clk_data;
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static void __init mvebu_clk_core_setup(struct device_node *np,
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struct core_clocks *coreclk)
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{
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const char *tclk_name = "tclk";
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const char *cpuclk_name = "cpuclk";
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void __iomem *base;
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unsigned long rate;
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int n;
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base = of_iomap(np, 0);
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if (WARN_ON(!base))
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return;
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/*
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* Allocate struct for TCLK, cpu clk, and core ratio clocks
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*/
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clk_data.clk_num = 2 + coreclk->num_ratios;
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clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
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GFP_KERNEL);
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if (WARN_ON(!clk_data.clks))
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return;
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/*
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* Register TCLK
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*/
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of_property_read_string_index(np, "clock-output-names", 0,
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&tclk_name);
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rate = coreclk->get_tclk_freq(base);
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clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
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CLK_IS_ROOT, rate);
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WARN_ON(IS_ERR(clk_data.clks[0]));
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/*
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* Register CPU clock
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*/
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of_property_read_string_index(np, "clock-output-names", 1,
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&cpuclk_name);
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rate = coreclk->get_cpu_freq(base);
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clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
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CLK_IS_ROOT, rate);
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WARN_ON(IS_ERR(clk_data.clks[1]));
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/*
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* Register fixed-factor clocks derived from CPU clock
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*/
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for (n = 0; n < coreclk->num_ratios; n++) {
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const char *rclk_name = coreclk->ratios[n].name;
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int mult, div;
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of_property_read_string_index(np, "clock-output-names",
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2+n, &rclk_name);
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coreclk->get_clk_ratio(base, coreclk->ratios[n].id,
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&mult, &div);
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clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
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cpuclk_name, 0, mult, div);
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WARN_ON(IS_ERR(clk_data.clks[2+n]));
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};
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/*
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* SAR register isn't needed anymore
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*/
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iounmap(base);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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#ifdef CONFIG_MACH_ARMADA_370_XP
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/*
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* Armada 370/XP Sample At Reset is a 64 bit bitfiled split in two
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* register of 32 bits
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*/
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#define SARL 0 /* Low part [0:31] */
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#define SARL_AXP_PCLK_FREQ_OPT 21
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#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
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#define SARL_A370_PCLK_FREQ_OPT 11
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#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
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#define SARL_AXP_FAB_FREQ_OPT 24
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#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
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#define SARL_A370_FAB_FREQ_OPT 15
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#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
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#define SARL_A370_TCLK_FREQ_OPT 20
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#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
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#define SARH 4 /* High part [32:63] */
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#define SARH_AXP_PCLK_FREQ_OPT (52-32)
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#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
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#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
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#define SARH_AXP_FAB_FREQ_OPT (51-32)
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#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
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#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
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static const u32 __initconst armada_370_tclk_frequencies[] = {
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16600000,
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20000000,
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};
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static u32 __init armada_370_get_tclk_freq(void __iomem *sar)
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{
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u8 tclk_freq_select = 0;
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tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
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SARL_A370_TCLK_FREQ_OPT_MASK);
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return armada_370_tclk_frequencies[tclk_freq_select];
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}
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static const u32 __initconst armada_370_cpu_frequencies[] = {
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400000000,
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533000000,
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667000000,
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800000000,
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1000000000,
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1067000000,
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1200000000,
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};
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static u32 __init armada_370_get_cpu_freq(void __iomem *sar)
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{
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u32 cpu_freq;
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u8 cpu_freq_select = 0;
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cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
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SARL_A370_PCLK_FREQ_OPT_MASK);
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if (cpu_freq_select > ARRAY_SIZE(armada_370_cpu_frequencies)) {
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pr_err("CPU freq select unsuported %d\n", cpu_freq_select);
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cpu_freq = 0;
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} else
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cpu_freq = armada_370_cpu_frequencies[cpu_freq_select];
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return cpu_freq;
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}
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enum { A370_XP_NBCLK, A370_XP_HCLK, A370_XP_DRAMCLK };
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static const struct core_ratio __initconst armada_370_xp_core_ratios[] = {
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{ .id = A370_XP_NBCLK, .name = "nbclk" },
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{ .id = A370_XP_HCLK, .name = "hclk" },
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{ .id = A370_XP_DRAMCLK, .name = "dramclk" },
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};
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static const int __initconst armada_370_xp_nbclk_ratios[32][2] = {
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{0, 1}, {1, 2}, {2, 2}, {2, 2},
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{1, 2}, {1, 2}, {1, 1}, {2, 3},
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{0, 1}, {1, 2}, {2, 4}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {2, 2},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{2, 3}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static const int __initconst armada_370_xp_hclk_ratios[32][2] = {
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{0, 1}, {1, 2}, {2, 6}, {2, 3},
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{1, 3}, {1, 4}, {1, 2}, {2, 6},
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{0, 1}, {1, 6}, {2, 10}, {0, 1},
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{1, 4}, {0, 1}, {0, 1}, {2, 5},
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{0, 1}, {0, 1}, {0, 1}, {1, 2},
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{2, 6}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static const int __initconst armada_370_xp_dramclk_ratios[32][2] = {
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{0, 1}, {1, 2}, {2, 3}, {2, 3},
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{1, 3}, {1, 2}, {1, 2}, {2, 6},
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{0, 1}, {1, 3}, {2, 5}, {0, 1},
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{1, 4}, {0, 1}, {0, 1}, {2, 5},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{2, 3}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {1, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static void __init armada_370_xp_get_clk_ratio(u32 opt,
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void __iomem *sar, int id, int *mult, int *div)
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{
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switch (id) {
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case A370_XP_NBCLK:
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*mult = armada_370_xp_nbclk_ratios[opt][0];
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*div = armada_370_xp_nbclk_ratios[opt][1];
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break;
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case A370_XP_HCLK:
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*mult = armada_370_xp_hclk_ratios[opt][0];
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*div = armada_370_xp_hclk_ratios[opt][1];
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break;
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case A370_XP_DRAMCLK:
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*mult = armada_370_xp_dramclk_ratios[opt][0];
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*div = armada_370_xp_dramclk_ratios[opt][1];
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break;
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}
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}
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static void __init armada_370_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
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SARL_A370_FAB_FREQ_OPT_MASK);
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armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
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}
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static const struct core_clocks armada_370_core_clocks = {
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.get_tclk_freq = armada_370_get_tclk_freq,
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.get_cpu_freq = armada_370_get_cpu_freq,
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.get_clk_ratio = armada_370_get_clk_ratio,
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.ratios = armada_370_xp_core_ratios,
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.num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
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};
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static const u32 __initconst armada_xp_cpu_frequencies[] = {
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1000000000,
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1066000000,
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1200000000,
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1333000000,
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1500000000,
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1666000000,
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1800000000,
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2000000000,
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667000000,
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0,
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800000000,
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1600000000,
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};
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/* For Armada XP TCLK frequency is fix: 250MHz */
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static u32 __init armada_xp_get_tclk_freq(void __iomem *sar)
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{
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return 250 * 1000 * 1000;
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}
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static u32 __init armada_xp_get_cpu_freq(void __iomem *sar)
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{
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u32 cpu_freq;
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u8 cpu_freq_select = 0;
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cpu_freq_select = ((readl(sar) >> SARL_AXP_PCLK_FREQ_OPT) &
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SARL_AXP_PCLK_FREQ_OPT_MASK);
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/*
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* The upper bit is not contiguous to the other ones and
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* located in the high part of the SAR registers
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*/
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cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) &
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SARH_AXP_PCLK_FREQ_OPT_MASK)
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<< SARH_AXP_PCLK_FREQ_OPT_SHIFT);
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if (cpu_freq_select > ARRAY_SIZE(armada_xp_cpu_frequencies)) {
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pr_err("CPU freq select unsuported: %d\n", cpu_freq_select);
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cpu_freq = 0;
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} else
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cpu_freq = armada_xp_cpu_frequencies[cpu_freq_select];
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return cpu_freq;
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}
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static void __init armada_xp_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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u32 opt = ((readl(sar) >> SARL_AXP_FAB_FREQ_OPT) &
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SARL_AXP_FAB_FREQ_OPT_MASK);
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/*
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* The upper bit is not contiguous to the other ones and
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* located in the high part of the SAR registers
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*/
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opt |= (((readl(sar+4) >> SARH_AXP_FAB_FREQ_OPT) &
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SARH_AXP_FAB_FREQ_OPT_MASK)
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<< SARH_AXP_FAB_FREQ_OPT_SHIFT);
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armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
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}
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static const struct core_clocks armada_xp_core_clocks = {
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.get_tclk_freq = armada_xp_get_tclk_freq,
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.get_cpu_freq = armada_xp_get_cpu_freq,
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.get_clk_ratio = armada_xp_get_clk_ratio,
|
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.ratios = armada_370_xp_core_ratios,
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.num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
|
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};
|
||||
|
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#endif /* CONFIG_MACH_ARMADA_370_XP */
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||||
|
||||
/*
|
||||
* Dove PLL sample-at-reset configuration
|
||||
*
|
||||
* SAR0[8:5] : CPU frequency
|
||||
* 5 = 1000 MHz
|
||||
* 6 = 933 MHz
|
||||
* 7 = 933 MHz
|
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* 8 = 800 MHz
|
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* 9 = 800 MHz
|
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* 10 = 800 MHz
|
||||
* 11 = 1067 MHz
|
||||
* 12 = 667 MHz
|
||||
* 13 = 533 MHz
|
||||
* 14 = 400 MHz
|
||||
* 15 = 333 MHz
|
||||
* others reserved.
|
||||
*
|
||||
* SAR0[11:9] : CPU to L2 Clock divider ratio
|
||||
* 0 = (1/1) * CPU
|
||||
* 2 = (1/2) * CPU
|
||||
* 4 = (1/3) * CPU
|
||||
* 6 = (1/4) * CPU
|
||||
* others reserved.
|
||||
*
|
||||
* SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
|
||||
* 0 = (1/1) * CPU
|
||||
* 2 = (1/2) * CPU
|
||||
* 3 = (2/5) * CPU
|
||||
* 4 = (1/3) * CPU
|
||||
* 6 = (1/4) * CPU
|
||||
* 8 = (1/5) * CPU
|
||||
* 10 = (1/6) * CPU
|
||||
* 12 = (1/7) * CPU
|
||||
* 14 = (1/8) * CPU
|
||||
* 15 = (1/10) * CPU
|
||||
* others reserved.
|
||||
*
|
||||
* SAR0[24:23] : TCLK frequency
|
||||
* 0 = 166 MHz
|
||||
* 1 = 125 MHz
|
||||
* others reserved.
|
||||
*/
|
||||
#ifdef CONFIG_ARCH_DOVE
|
||||
#define SAR_DOVE_CPU_FREQ 5
|
||||
#define SAR_DOVE_CPU_FREQ_MASK 0xf
|
||||
#define SAR_DOVE_L2_RATIO 9
|
||||
#define SAR_DOVE_L2_RATIO_MASK 0x7
|
||||
#define SAR_DOVE_DDR_RATIO 12
|
||||
#define SAR_DOVE_DDR_RATIO_MASK 0xf
|
||||
#define SAR_DOVE_TCLK_FREQ 23
|
||||
#define SAR_DOVE_TCLK_FREQ_MASK 0x3
|
||||
|
||||
static const u32 __initconst dove_tclk_frequencies[] = {
|
||||
166666667,
|
||||
125000000,
|
||||
0, 0
|
||||
};
|
||||
|
||||
static u32 __init dove_get_tclk_freq(void __iomem *sar)
|
||||
{
|
||||
u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
|
||||
SAR_DOVE_TCLK_FREQ_MASK;
|
||||
return dove_tclk_frequencies[opt];
|
||||
}
|
||||
|
||||
static const u32 __initconst dove_cpu_frequencies[] = {
|
||||
0, 0, 0, 0, 0,
|
||||
1000000000,
|
||||
933333333, 933333333,
|
||||
800000000, 800000000, 800000000,
|
||||
1066666667,
|
||||
666666667,
|
||||
533333333,
|
||||
400000000,
|
||||
333333333
|
||||
};
|
||||
|
||||
static u32 __init dove_get_cpu_freq(void __iomem *sar)
|
||||
{
|
||||
u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
|
||||
SAR_DOVE_CPU_FREQ_MASK;
|
||||
return dove_cpu_frequencies[opt];
|
||||
}
|
||||
|
||||
enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
|
||||
|
||||
static const struct core_ratio __initconst dove_core_ratios[] = {
|
||||
{ .id = DOVE_CPU_TO_L2, .name = "l2clk", },
|
||||
{ .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
|
||||
};
|
||||
|
||||
static const int __initconst dove_cpu_l2_ratios[8][2] = {
|
||||
{ 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
|
||||
{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
|
||||
};
|
||||
|
||||
static const int __initconst dove_cpu_ddr_ratios[16][2] = {
|
||||
{ 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
|
||||
{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
|
||||
{ 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
|
||||
{ 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
|
||||
};
|
||||
|
||||
static void __init dove_get_clk_ratio(
|
||||
void __iomem *sar, int id, int *mult, int *div)
|
||||
{
|
||||
switch (id) {
|
||||
case DOVE_CPU_TO_L2:
|
||||
{
|
||||
u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
|
||||
SAR_DOVE_L2_RATIO_MASK;
|
||||
*mult = dove_cpu_l2_ratios[opt][0];
|
||||
*div = dove_cpu_l2_ratios[opt][1];
|
||||
break;
|
||||
}
|
||||
case DOVE_CPU_TO_DDR:
|
||||
{
|
||||
u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
|
||||
SAR_DOVE_DDR_RATIO_MASK;
|
||||
*mult = dove_cpu_ddr_ratios[opt][0];
|
||||
*div = dove_cpu_ddr_ratios[opt][1];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const struct core_clocks dove_core_clocks = {
|
||||
.get_tclk_freq = dove_get_tclk_freq,
|
||||
.get_cpu_freq = dove_get_cpu_freq,
|
||||
.get_clk_ratio = dove_get_clk_ratio,
|
||||
.ratios = dove_core_ratios,
|
||||
.num_ratios = ARRAY_SIZE(dove_core_ratios),
|
||||
};
|
||||
#endif /* CONFIG_ARCH_DOVE */
|
||||
|
||||
/*
|
||||
* Kirkwood PLL sample-at-reset configuration
|
||||
* (6180 has different SAR layout than other Kirkwood SoCs)
|
||||
*
|
||||
* SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
|
||||
* 4 = 600 MHz
|
||||
* 6 = 800 MHz
|
||||
* 7 = 1000 MHz
|
||||
* 9 = 1200 MHz
|
||||
* 12 = 1500 MHz
|
||||
* 13 = 1600 MHz
|
||||
* 14 = 1800 MHz
|
||||
* 15 = 2000 MHz
|
||||
* others reserved.
|
||||
*
|
||||
* SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
|
||||
* 1 = (1/2) * CPU
|
||||
* 3 = (1/3) * CPU
|
||||
* 5 = (1/4) * CPU
|
||||
* others reserved.
|
||||
*
|
||||
* SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
|
||||
* 2 = (1/2) * CPU
|
||||
* 4 = (1/3) * CPU
|
||||
* 6 = (1/4) * CPU
|
||||
* 7 = (2/9) * CPU
|
||||
* 8 = (1/5) * CPU
|
||||
* 9 = (1/6) * CPU
|
||||
* others reserved.
|
||||
*
|
||||
* SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
|
||||
* 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
|
||||
* 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
|
||||
* 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
|
||||
* others reserved.
|
||||
*
|
||||
* SAR0[21] : TCLK frequency
|
||||
* 0 = 200 MHz
|
||||
* 1 = 166 MHz
|
||||
* others reserved.
|
||||
*/
|
||||
#ifdef CONFIG_ARCH_KIRKWOOD
|
||||
#define SAR_KIRKWOOD_CPU_FREQ(x) \
|
||||
(((x & (1 << 1)) >> 1) | \
|
||||
((x & (1 << 22)) >> 21) | \
|
||||
((x & (3 << 3)) >> 1))
|
||||
#define SAR_KIRKWOOD_L2_RATIO(x) \
|
||||
(((x & (3 << 9)) >> 9) | \
|
||||
(((x & (1 << 19)) >> 17)))
|
||||
#define SAR_KIRKWOOD_DDR_RATIO 5
|
||||
#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
|
||||
#define SAR_MV88F6180_CLK 2
|
||||
#define SAR_MV88F6180_CLK_MASK 0x7
|
||||
#define SAR_KIRKWOOD_TCLK_FREQ 21
|
||||
#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
|
||||
|
||||
enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
|
||||
|
||||
static const struct core_ratio __initconst kirkwood_core_ratios[] = {
|
||||
{ .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
|
||||
{ .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
|
||||
};
|
||||
|
||||
static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
|
||||
{
|
||||
u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
|
||||
SAR_KIRKWOOD_TCLK_FREQ_MASK;
|
||||
return (opt) ? 166666667 : 200000000;
|
||||
}
|
||||
|
||||
static const u32 __initconst kirkwood_cpu_frequencies[] = {
|
||||
0, 0, 0, 0,
|
||||
600000000,
|
||||
0,
|
||||
800000000,
|
||||
1000000000,
|
||||
0,
|
||||
1200000000,
|
||||
0, 0,
|
||||
1500000000,
|
||||
1600000000,
|
||||
1800000000,
|
||||
2000000000
|
||||
};
|
||||
|
||||
static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
|
||||
{
|
||||
u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
|
||||
return kirkwood_cpu_frequencies[opt];
|
||||
}
|
||||
|
||||
static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
|
||||
{ 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
|
||||
};
|
||||
|
||||
static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
|
||||
{ 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
|
||||
{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
|
||||
{ 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
|
||||
{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
|
||||
};
|
||||
|
||||
static void __init kirkwood_get_clk_ratio(
|
||||
void __iomem *sar, int id, int *mult, int *div)
|
||||
{
|
||||
switch (id) {
|
||||
case KIRKWOOD_CPU_TO_L2:
|
||||
{
|
||||
u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
|
||||
*mult = kirkwood_cpu_l2_ratios[opt][0];
|
||||
*div = kirkwood_cpu_l2_ratios[opt][1];
|
||||
break;
|
||||
}
|
||||
case KIRKWOOD_CPU_TO_DDR:
|
||||
{
|
||||
u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
|
||||
SAR_KIRKWOOD_DDR_RATIO_MASK;
|
||||
*mult = kirkwood_cpu_ddr_ratios[opt][0];
|
||||
*div = kirkwood_cpu_ddr_ratios[opt][1];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const struct core_clocks kirkwood_core_clocks = {
|
||||
.get_tclk_freq = kirkwood_get_tclk_freq,
|
||||
.get_cpu_freq = kirkwood_get_cpu_freq,
|
||||
.get_clk_ratio = kirkwood_get_clk_ratio,
|
||||
.ratios = kirkwood_core_ratios,
|
||||
.num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
|
||||
};
|
||||
|
||||
static const u32 __initconst mv88f6180_cpu_frequencies[] = {
|
||||
0, 0, 0, 0, 0,
|
||||
600000000,
|
||||
800000000,
|
||||
1000000000
|
||||
};
|
||||
|
||||
static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
|
||||
{
|
||||
u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
|
||||
return mv88f6180_cpu_frequencies[opt];
|
||||
}
|
||||
|
||||
static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
|
||||
{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
|
||||
{ 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
|
||||
};
|
||||
|
||||
static void __init mv88f6180_get_clk_ratio(
|
||||
void __iomem *sar, int id, int *mult, int *div)
|
||||
{
|
||||
switch (id) {
|
||||
case KIRKWOOD_CPU_TO_L2:
|
||||
{
|
||||
/* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
|
||||
*mult = 1;
|
||||
*div = 2;
|
||||
break;
|
||||
}
|
||||
case KIRKWOOD_CPU_TO_DDR:
|
||||
{
|
||||
u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
|
||||
SAR_MV88F6180_CLK_MASK;
|
||||
*mult = mv88f6180_cpu_ddr_ratios[opt][0];
|
||||
*div = mv88f6180_cpu_ddr_ratios[opt][1];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const struct core_clocks mv88f6180_core_clocks = {
|
||||
.get_tclk_freq = kirkwood_get_tclk_freq,
|
||||
.get_cpu_freq = mv88f6180_get_cpu_freq,
|
||||
.get_clk_ratio = mv88f6180_get_clk_ratio,
|
||||
.ratios = kirkwood_core_ratios,
|
||||
.num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
|
||||
};
|
||||
#endif /* CONFIG_ARCH_KIRKWOOD */
|
||||
|
||||
static const __initdata struct of_device_id clk_core_match[] = {
|
||||
#ifdef CONFIG_MACH_ARMADA_370_XP
|
||||
{
|
||||
.compatible = "marvell,armada-370-core-clock",
|
||||
.data = &armada_370_core_clocks,
|
||||
},
|
||||
{
|
||||
.compatible = "marvell,armada-xp-core-clock",
|
||||
.data = &armada_xp_core_clocks,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DOVE
|
||||
{
|
||||
.compatible = "marvell,dove-core-clock",
|
||||
.data = &dove_core_clocks,
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_KIRKWOOD
|
||||
{
|
||||
.compatible = "marvell,kirkwood-core-clock",
|
||||
.data = &kirkwood_core_clocks,
|
||||
},
|
||||
{
|
||||
.compatible = "marvell,mv88f6180-core-clock",
|
||||
.data = &mv88f6180_core_clocks,
|
||||
},
|
||||
#endif
|
||||
|
||||
{ }
|
||||
};
|
||||
|
||||
void __init mvebu_core_clk_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
for_each_matching_node(np, clk_core_match) {
|
||||
const struct of_device_id *match =
|
||||
of_match_node(clk_core_match, np);
|
||||
mvebu_clk_core_setup(np, (struct core_clocks *)match->data);
|
||||
}
|
||||
}
|
||||
18
drivers/clk/mvebu/clk-core.h
Normal file
18
drivers/clk/mvebu/clk-core.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* * Marvell EBU clock core handling defined at reset
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MVEBU_CLK_CORE_H
|
||||
#define __MVEBU_CLK_CORE_H
|
||||
|
||||
void __init mvebu_core_clk_init(void);
|
||||
|
||||
#endif
|
||||
186
drivers/clk/mvebu/clk-cpu.c
Normal file
186
drivers/clk/mvebu/clk-cpu.c
Normal file
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
* Marvell MVEBU CPU clock handling.
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/delay.h>
|
||||
#include "clk-cpu.h"
|
||||
|
||||
#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
|
||||
#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
|
||||
#define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
|
||||
|
||||
#define MAX_CPU 4
|
||||
struct cpu_clk {
|
||||
struct clk_hw hw;
|
||||
int cpu;
|
||||
const char *clk_name;
|
||||
const char *parent_name;
|
||||
void __iomem *reg_base;
|
||||
};
|
||||
|
||||
static struct clk **clks;
|
||||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
#define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
|
||||
|
||||
static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
|
||||
u32 reg, div;
|
||||
|
||||
reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
|
||||
div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
/* Valid ratio are 1:1, 1:2 and 1:3 */
|
||||
u32 div;
|
||||
|
||||
div = *parent_rate / rate;
|
||||
if (div == 0)
|
||||
div = 1;
|
||||
else if (div > 3)
|
||||
div = 3;
|
||||
|
||||
return *parent_rate / div;
|
||||
}
|
||||
|
||||
static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
|
||||
u32 reg, div;
|
||||
u32 reload_mask;
|
||||
|
||||
div = parent_rate / rate;
|
||||
reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
|
||||
& (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
|
||||
| (div << (cpuclk->cpu * 8));
|
||||
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
|
||||
/* Set clock divider reload smooth bit mask */
|
||||
reload_mask = 1 << (20 + cpuclk->cpu);
|
||||
|
||||
reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
|
||||
| reload_mask;
|
||||
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
|
||||
|
||||
/* Now trigger the clock update */
|
||||
reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
|
||||
| 1 << 24;
|
||||
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
|
||||
|
||||
/* Wait for clocks to settle down then clear reload request */
|
||||
udelay(1000);
|
||||
reg &= ~(reload_mask | 1 << 24);
|
||||
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
|
||||
udelay(1000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops cpu_ops = {
|
||||
.recalc_rate = clk_cpu_recalc_rate,
|
||||
.round_rate = clk_cpu_round_rate,
|
||||
.set_rate = clk_cpu_set_rate,
|
||||
};
|
||||
|
||||
void __init of_cpu_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct cpu_clk *cpuclk;
|
||||
void __iomem *clock_complex_base = of_iomap(node, 0);
|
||||
int ncpus = 0;
|
||||
struct device_node *dn;
|
||||
|
||||
if (clock_complex_base == NULL) {
|
||||
pr_err("%s: clock-complex base register not set\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for_each_node_by_type(dn, "cpu")
|
||||
ncpus++;
|
||||
|
||||
cpuclk = kzalloc(ncpus * sizeof(*cpuclk), GFP_KERNEL);
|
||||
if (WARN_ON(!cpuclk))
|
||||
return;
|
||||
|
||||
clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL);
|
||||
if (WARN_ON(!clks))
|
||||
return;
|
||||
|
||||
for_each_node_by_type(dn, "cpu") {
|
||||
struct clk_init_data init;
|
||||
struct clk *clk;
|
||||
struct clk *parent_clk;
|
||||
char *clk_name = kzalloc(5, GFP_KERNEL);
|
||||
int cpu, err;
|
||||
|
||||
if (WARN_ON(!clk_name))
|
||||
return;
|
||||
|
||||
err = of_property_read_u32(dn, "reg", &cpu);
|
||||
if (WARN_ON(err))
|
||||
return;
|
||||
|
||||
sprintf(clk_name, "cpu%d", cpu);
|
||||
parent_clk = of_clk_get(node, 0);
|
||||
|
||||
cpuclk[cpu].parent_name = __clk_get_name(parent_clk);
|
||||
cpuclk[cpu].clk_name = clk_name;
|
||||
cpuclk[cpu].cpu = cpu;
|
||||
cpuclk[cpu].reg_base = clock_complex_base;
|
||||
cpuclk[cpu].hw.init = &init;
|
||||
|
||||
init.name = cpuclk[cpu].clk_name;
|
||||
init.ops = &cpu_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = &cpuclk[cpu].parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
clk = clk_register(NULL, &cpuclk[cpu].hw);
|
||||
if (WARN_ON(IS_ERR(clk)))
|
||||
goto bail_out;
|
||||
clks[cpu] = clk;
|
||||
}
|
||||
clk_data.clk_num = MAX_CPU;
|
||||
clk_data.clks = clks;
|
||||
of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
return;
|
||||
bail_out:
|
||||
kfree(clks);
|
||||
kfree(cpuclk);
|
||||
}
|
||||
|
||||
static const __initconst struct of_device_id clk_cpu_match[] = {
|
||||
{
|
||||
.compatible = "marvell,armada-xp-cpu-clock",
|
||||
.data = of_cpu_clk_setup,
|
||||
},
|
||||
{
|
||||
/* sentinel */
|
||||
},
|
||||
};
|
||||
|
||||
void __init mvebu_cpu_clk_init(void)
|
||||
{
|
||||
of_clk_init(clk_cpu_match);
|
||||
}
|
||||
22
drivers/clk/mvebu/clk-cpu.h
Normal file
22
drivers/clk/mvebu/clk-cpu.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Marvell MVEBU CPU clock handling.
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MVEBU_CLK_CPU_H
|
||||
#define __MVEBU_CLK_CPU_H
|
||||
|
||||
#ifdef CONFIG_MVEBU_CLK_CPU
|
||||
void __init mvebu_cpu_clk_init(void);
|
||||
#else
|
||||
static inline void mvebu_cpu_clk_init(void) {}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
249
drivers/clk/mvebu/clk-gating-ctrl.c
Normal file
249
drivers/clk/mvebu/clk-gating-ctrl.c
Normal file
|
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* Marvell MVEBU clock gating control.
|
||||
*
|
||||
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
* Andrew Lunn <andrew@lunn.ch>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/mvebu.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
struct mvebu_gating_ctrl {
|
||||
spinlock_t lock;
|
||||
struct clk **gates;
|
||||
int num_gates;
|
||||
};
|
||||
|
||||
struct mvebu_soc_descr {
|
||||
const char *name;
|
||||
const char *parent;
|
||||
int bit_idx;
|
||||
};
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
static struct clk __init *mvebu_clk_gating_get_src(
|
||||
struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
|
||||
int n;
|
||||
|
||||
if (clkspec->args_count < 1)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
for (n = 0; n < ctrl->num_gates; n++) {
|
||||
struct clk_gate *gate =
|
||||
to_clk_gate(__clk_get_hw(ctrl->gates[n]));
|
||||
if (clkspec->args[0] == gate->bit_idx)
|
||||
return ctrl->gates[n];
|
||||
}
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
static void __init mvebu_clk_gating_setup(
|
||||
struct device_node *np, const struct mvebu_soc_descr *descr)
|
||||
{
|
||||
struct mvebu_gating_ctrl *ctrl;
|
||||
struct clk *clk;
|
||||
void __iomem *base;
|
||||
const char *default_parent = NULL;
|
||||
int n;
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
|
||||
clk = of_clk_get(np, 0);
|
||||
if (!IS_ERR(clk)) {
|
||||
default_parent = __clk_get_name(clk);
|
||||
clk_put(clk);
|
||||
}
|
||||
|
||||
ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL);
|
||||
if (WARN_ON(!ctrl))
|
||||
return;
|
||||
|
||||
spin_lock_init(&ctrl->lock);
|
||||
|
||||
/*
|
||||
* Count, allocate, and register clock gates
|
||||
*/
|
||||
for (n = 0; descr[n].name;)
|
||||
n++;
|
||||
|
||||
ctrl->num_gates = n;
|
||||
ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
|
||||
GFP_KERNEL);
|
||||
if (WARN_ON(!ctrl->gates)) {
|
||||
kfree(ctrl);
|
||||
return;
|
||||
}
|
||||
|
||||
for (n = 0; n < ctrl->num_gates; n++) {
|
||||
u8 flags = 0;
|
||||
const char *parent =
|
||||
(descr[n].parent) ? descr[n].parent : default_parent;
|
||||
|
||||
/*
|
||||
* On Armada 370, the DDR clock is a special case: it
|
||||
* isn't taken by any driver, but should anyway be
|
||||
* kept enabled, so we mark it as IGNORE_UNUSED for
|
||||
* now.
|
||||
*/
|
||||
if (!strcmp(descr[n].name, "ddr"))
|
||||
flags |= CLK_IGNORE_UNUSED;
|
||||
|
||||
ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
|
||||
flags, base, descr[n].bit_idx, 0, &ctrl->lock);
|
||||
WARN_ON(IS_ERR(ctrl->gates[n]));
|
||||
}
|
||||
of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
|
||||
}
|
||||
|
||||
/*
|
||||
* SoC specific clock gating control
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_MACH_ARMADA_370
|
||||
static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
|
||||
{ "audio", NULL, 0 },
|
||||
{ "pex0_en", NULL, 1 },
|
||||
{ "pex1_en", NULL, 2 },
|
||||
{ "ge1", NULL, 3 },
|
||||
{ "ge0", NULL, 4 },
|
||||
{ "pex0", NULL, 5 },
|
||||
{ "pex1", NULL, 9 },
|
||||
{ "sata0", NULL, 15 },
|
||||
{ "sdio", NULL, 17 },
|
||||
{ "tdm", NULL, 25 },
|
||||
{ "ddr", NULL, 28 },
|
||||
{ "sata1", NULL, 30 },
|
||||
{ }
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_ARMADA_XP
|
||||
static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
|
||||
{ "audio", NULL, 0 },
|
||||
{ "ge3", NULL, 1 },
|
||||
{ "ge2", NULL, 2 },
|
||||
{ "ge1", NULL, 3 },
|
||||
{ "ge0", NULL, 4 },
|
||||
{ "pex0", NULL, 5 },
|
||||
{ "pex1", NULL, 6 },
|
||||
{ "pex2", NULL, 7 },
|
||||
{ "pex3", NULL, 8 },
|
||||
{ "bp", NULL, 13 },
|
||||
{ "sata0lnk", NULL, 14 },
|
||||
{ "sata0", "sata0lnk", 15 },
|
||||
{ "lcd", NULL, 16 },
|
||||
{ "sdio", NULL, 17 },
|
||||
{ "usb0", NULL, 18 },
|
||||
{ "usb1", NULL, 19 },
|
||||
{ "usb2", NULL, 20 },
|
||||
{ "xor0", NULL, 22 },
|
||||
{ "crypto", NULL, 23 },
|
||||
{ "tdm", NULL, 25 },
|
||||
{ "xor1", NULL, 28 },
|
||||
{ "sata1lnk", NULL, 29 },
|
||||
{ "sata1", "sata1lnk", 30 },
|
||||
{ }
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_DOVE
|
||||
static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
|
||||
{ "usb0", NULL, 0 },
|
||||
{ "usb1", NULL, 1 },
|
||||
{ "ge", "gephy", 2 },
|
||||
{ "sata", NULL, 3 },
|
||||
{ "pex0", NULL, 4 },
|
||||
{ "pex1", NULL, 5 },
|
||||
{ "sdio0", NULL, 8 },
|
||||
{ "sdio1", NULL, 9 },
|
||||
{ "nand", NULL, 10 },
|
||||
{ "camera", NULL, 11 },
|
||||
{ "i2s0", NULL, 12 },
|
||||
{ "i2s1", NULL, 13 },
|
||||
{ "crypto", NULL, 15 },
|
||||
{ "ac97", NULL, 21 },
|
||||
{ "pdma", NULL, 22 },
|
||||
{ "xor0", NULL, 23 },
|
||||
{ "xor1", NULL, 24 },
|
||||
{ "gephy", NULL, 30 },
|
||||
{ }
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_KIRKWOOD
|
||||
static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
|
||||
{ "ge0", NULL, 0 },
|
||||
{ "pex0", NULL, 2 },
|
||||
{ "usb0", NULL, 3 },
|
||||
{ "sdio", NULL, 4 },
|
||||
{ "tsu", NULL, 5 },
|
||||
{ "runit", NULL, 7 },
|
||||
{ "xor0", NULL, 8 },
|
||||
{ "audio", NULL, 9 },
|
||||
{ "sata0", NULL, 14 },
|
||||
{ "sata1", NULL, 15 },
|
||||
{ "xor1", NULL, 16 },
|
||||
{ "crypto", NULL, 17 },
|
||||
{ "pex1", NULL, 18 },
|
||||
{ "ge1", NULL, 19 },
|
||||
{ "tdm", NULL, 20 },
|
||||
{ }
|
||||
};
|
||||
#endif
|
||||
|
||||
static const __initdata struct of_device_id clk_gating_match[] = {
|
||||
#ifdef CONFIG_MACH_ARMADA_370
|
||||
{
|
||||
.compatible = "marvell,armada-370-gating-clock",
|
||||
.data = armada_370_gating_descr,
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_ARMADA_XP
|
||||
{
|
||||
.compatible = "marvell,armada-xp-gating-clock",
|
||||
.data = armada_xp_gating_descr,
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_DOVE
|
||||
{
|
||||
.compatible = "marvell,dove-gating-clock",
|
||||
.data = dove_gating_descr,
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_KIRKWOOD
|
||||
{
|
||||
.compatible = "marvell,kirkwood-gating-clock",
|
||||
.data = kirkwood_gating_descr,
|
||||
},
|
||||
#endif
|
||||
|
||||
{ }
|
||||
};
|
||||
|
||||
void __init mvebu_gating_clk_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
for_each_matching_node(np, clk_gating_match) {
|
||||
const struct of_device_id *match =
|
||||
of_match_node(clk_gating_match, np);
|
||||
mvebu_clk_gating_setup(np,
|
||||
(const struct mvebu_soc_descr *)match->data);
|
||||
}
|
||||
}
|
||||
22
drivers/clk/mvebu/clk-gating-ctrl.h
Normal file
22
drivers/clk/mvebu/clk-gating-ctrl.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Marvell EBU gating clock handling
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MVEBU_CLK_GATING_H
|
||||
#define __MVEBU_CLK_GATING_H
|
||||
|
||||
#ifdef CONFIG_MVEBU_CLK_GATING
|
||||
void __init mvebu_gating_clk_init(void);
|
||||
#else
|
||||
void mvebu_gating_clk_init(void) {}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
27
drivers/clk/mvebu/clk.c
Normal file
27
drivers/clk/mvebu/clk.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Marvell EBU SoC clock handling.
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/mvebu.h>
|
||||
#include <linux/of.h>
|
||||
#include "clk-core.h"
|
||||
#include "clk-cpu.h"
|
||||
#include "clk-gating-ctrl.h"
|
||||
|
||||
void __init mvebu_clocks_init(void)
|
||||
{
|
||||
mvebu_core_clk_init();
|
||||
mvebu_gating_clk_init();
|
||||
mvebu_cpu_clk_init();
|
||||
}
|
||||
Loading…
Reference in a new issue