From c281587f39a588a9bdc2e6f48e29bc9bb81799be Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 10 Jul 2020 11:29:02 +0530 Subject: [PATCH] bindings: Documentation: modify documentation for hbb This changes modifies the documentation for highest bank bit used for UBWC configuration. Change-Id: I4a35bf2330402b3d6680aa74344ea088cd6b2866 --- bindings/sde.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 93e968a01ab9..367633a93d3a 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -134,8 +134,10 @@ Optional properties: - qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. It supports "csc" and "csc-10bit" entries for csc type. -- qcom,sde-highest-bank-bit: A u32 property to indicate GPU/Camera/Video highest memory - bank bit used for tile format buffers. +- qcom,sde-highest-bank-bit: Property to specify GPU/Camera/Video highest memory + bank bit used for tile format buffers. First value + in the array represents the ddr type and the second + value is the hbb value corresponding to the ddr type. - qcom,sde-ubwc-version: Property to specify the UBWC feature version. - qcom,sde-ubwc-static: Property to specify the default UBWC static configuration value. @@ -674,7 +676,7 @@ Example: qcom,sde-sspp-linewidth = <2560>; qcom,sde-mixer-blendstages = <0x7>; qcom,sde-dsc-linewidth = <2048>; - qcom,sde-highest-bank-bit = <0x2>; + qcom,sde-highest-bank-bit = <0x7 0x2>; qcom,sde-ubwc-version = <0x100>; qcom,sde-ubwc-static = <0x100>; qcom,sde-ubwc-swizzle = <0>;