From 4166b3c0b0b6e2fcf50f3fe5964a8b058dd2924a Mon Sep 17 00:00:00 2001 From: Prateek Sood Date: Thu, 21 Jan 2021 01:41:37 +0530 Subject: [PATCH] ARM: dts: msm: Add mpm wakeup control capability in yupik pinctrl Add DT property for selective enabling of mpm wakeup control capability. Change-Id: I5a92558c44ad54f5e4c9b4499e4421a8b5430063 --- bindings/pinctrl/qcom,yupik-pinctrl.txt | 5 +++++ qcom/yupik-pinctrl.dtsi | 1 + 2 files changed, 6 insertions(+) diff --git a/bindings/pinctrl/qcom,yupik-pinctrl.txt b/bindings/pinctrl/qcom,yupik-pinctrl.txt index 819fd937ecd8..0a875154d0e4 100644 --- a/bindings/pinctrl/qcom,yupik-pinctrl.txt +++ b/bindings/pinctrl/qcom,yupik-pinctrl.txt @@ -45,6 +45,11 @@ YUPIK platform. Value type: Definition: A phandle to the wakeup interrupt controller for the SoC. +- qcom,tlmm-mpm-wake-control: + Usage: optional + Value type: + Definition: provide mpm wake control capability for a pin. + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index 7a6d1a6a7f15..ea88e048ce04 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -8,6 +8,7 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qcom,tlmm-mpm-wake-control; qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { qupv3_se0_i2c_active: qupv3_se0_i2c_active {