From 0d20299e32d0aaf83127a25c36e9e9159c26d8a5 Mon Sep 17 00:00:00 2001
From: Ram Prakash Gupta <rampraka@qti.qualcomm.com>
Date: Tue, 18 Aug 2020 02:17:25 +0530
Subject: [PATCH] ARM: dts: msm: Add hw gcc reset support for eMMC on shima

Add hw gcc reset support for eMMC on shima.

Change-Id: Icf62ee290c28d128bf1afc32520f8f08f9befd26
---
 qcom/shima.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 650f05e7da66..05e191168fdd 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -1791,6 +1791,8 @@
 		mmc-hs400-1_8v;
 		mmc-hs400-enhanced-strobe;
 
+		cap-mmc-hw-reset;
+
 		bus-width = <8>;
 		non-removable;
 		supports-cqe;
@@ -1798,6 +1800,10 @@
 		qcom,devfreq,freq-table = <50000000 200000000>;
 		qcom,scaling-lower-bus-speed-mode = "DDR52";
 
+		/* Add dt entry for gcc hw reset */
+		resets = <&gcc GCC_SDCC1_BCR>;
+		reset-names = "core_reset";
+
 		status = "disabled";
 
 		qos0 {