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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge 0fc34e9337 on remote branch
Change-Id: If86ebe32aade3f8823187e16ba5933b7fd23286f
This commit is contained in:
Linux Build Service Account
commit
c2e0f179b0
6 changed files with 1308 additions and 44 deletions
840
fw/htt.h
840
fw/htt.h
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@ -217,9 +217,10 @@
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* 3.93 Add HTT_T2H_MSG_TYPE_PEER_MAP_V3 def.
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* 3.94 Add HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG,
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* HTT_T2H_MSG_TYPE_VDEVS_TXRX_STATS_PERIODIC_IND defs.
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* 3.95 Add HTT_H2T_MSG_TYPE_TX_MONITOR_CFG def.
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 94
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#define HTT_CURRENT_VERSION_MINOR 95
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#define HTT_NUM_TX_FRAG_DESC 1024
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@ -654,6 +655,9 @@ typedef enum {
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HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, /* htt_t2h_soc_txrx_stats_common_tlv */
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HTT_STATS_VDEV_TXRX_STATS_HW_STATS_TAG = 126, /* htt_t2h_vdev_txrx_stats_hw_stats_tlv */
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HTT_STATS_VDEV_RTT_INIT_STATS_TAG = 127, /* htt_vdev_rtt_init_stats_tlv */
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HTT_STATS_PER_RATE_STATS_TAG = 128, /* htt_tx_rate_stats_per_tlv */
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HTT_STATS_MU_PPDU_DIST_TAG = 129, /* htt_pdev_mu_ppdu_dist_tlv */
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HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, /* htt_tx_pdev_mumimo_grp_stats_tlv */
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HTT_STATS_MAX_TAG,
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} htt_tlv_tag_t;
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@ -713,6 +717,7 @@ enum htt_h2t_msg_type {
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HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18,
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HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19,
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HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a,
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HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b,
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/* keep this last */
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HTT_H2T_NUM_MSGS
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@ -4687,6 +4692,12 @@ enum htt_srng_ring_id {
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HTT_HOST2_TO_FW_RXBUF_RING, /* (mobile only) second ring used by host to provide remote RX buffers */
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HTT_RXDMA_NON_MONITOR_DEST_RING, /* Per MDPU indication to host for non-monitor RxDMA traffic upload */
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HTT_RXDMA_HOST_BUF_RING2, /* Second ring used by FW to feed removed buffers and update removed packets */
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HTT_TX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */
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HTT_TX_MON_MON2HOST_DEST_RING0, /* Used by monitor to fill status buffers and provide to host */
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HTT_TX_MON_MON2HOST_DEST_RING1, /* Used by monitor to fill status buffers and provide to host */
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HTT_RX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */
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HTT_RX_MON_MON2HOST_DEST_RING0, /* Used by monitor to fill status buffers and provide to host */
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HTT_RX_MON_MON2HOST_DEST_RING1, /* Used by monitor to fill status buffers and provide to host */
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/* Add Other SRING which can't be directly configured by host software above this line */
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};
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@ -5856,6 +5867,833 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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HTT_RX_RING_TLV_ENABLE_GET( \
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word, HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_RX_##tlv)
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/**
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* @brief host -> target TX monitor config message
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*
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* MSG_TYPE => HTT_H2T_MSG_TYPE_TX_MONITOR_CFG
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*
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* @details
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* HTT_H2T_MSG_TYPE_TX_MONITOR_CFG message is sent by host to
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* configure RXDMA rings.
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* The configuration is per ring based and includes both packet types
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* and PPDU/MPDU TLVs.
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*
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* The message would appear as follows:
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*
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* |31 28|27|26|25|24|23 22|21 19|18 16|15 8|7 |2 0|
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* |-----+-----+--+--+-----=-----+------+----------------+---------+-----|
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* | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |
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* |-----+--------+--------+-----+------+--------------------------------|
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* |rsvd2| DATA | CTRL | MGMT| PT | ring_buffer_size |
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* |---------------------------------------------------------------+-----|
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* | rsvd3 | E |
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* |---------------------------------------------------------------------|
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* | tlv_filter_mask_in0 |
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* |---------------------------------------------------------------------|
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* | tlv_filter_mask_in1 |
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* |---------------------------------------------------------------------|
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* | tlv_filter_mask_in2 |
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* |---------------------------------------------------------------------|
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* | tlv_filter_mask_in3 |
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* |------------------------------------+--------------------------------|
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* | tx_peer_entry_word_mask | tx_fes_setup_word_mask |
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* |------------------------------------+--------------------------------|
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* | tx_msdu_start_word_mask | tx_queue_ext_word_mask |
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* |------------------------------------+--------------------------------|
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* | pcu_ppdu_setup_word_mask | tx_mpdu_start_word_mask |
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* |-----------------------+-----+------+--------------------------------|
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* | rsvd4 | EMM | PT | rxpcu_user_setup_word_mask |
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* |---------------------------------------------------------------------|
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*
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* Where:
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* PS = pkt_swap
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* SS = status_swap
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* The message is interpreted as follows:
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* dword0 - b'0:7 - msg_type: This will be set to
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* 0x1b (HTT_H2T_MSG_TYPE_TX_MONITOR_CFG)
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* b'8:15 - pdev_id:
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* 0 (for rings at SOC/UMAC level),
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* 1/2/3 mac id (for rings at LMAC level)
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* b'16:23 - ring_id : Identify the ring to configure.
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* More details can be got from enum htt_srng_ring_id
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* b'24 - status_swap (SS): 1 is to swap status TLV - refer to
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* BUF_RING_CFG_0 defs within HW .h files,
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* e.g. wmac_top_reg_seq_hwioreg.h
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* b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to
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* BUF_RING_CFG_0 defs within HW .h files,
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* e.g. wmac_top_reg_seq_hwioreg.h
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* b'26:31 - rsvd1: reserved for future use
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* dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring,
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* in byte units.
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* Valid only for HW_TO_SW_RING and SW_TO_HW_RING
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* b'16:18 - pkt_type_config_length (PT): MGMT, CTRL, DATA
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* Each bit out of 3 bits represents if configurable length
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* is valid and needs to programmed.
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* b'19:21 - config_length_mgmt(MGMT) for MGMT: Each bit set represent
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* 64, 128, 256.
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* If all 3 bits are set config length is > 256
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* b'22:24 - config_length_ctrl(CTRL) for CTRL: Each bit set represent
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* 64, 128, 256.
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* If all 3 bits are set config length is > 256
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* b'25:27 - config_length_data(DATA) for DATA: Each bit set represent
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* 64, 128, 256.
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* If all 3 bits are set config length is > 256
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* - b'28:31 - rsvd2: Reserved for future use
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* dword2 - b'0:2 - packet_type_enable_flags(E): MGMT, CTRL, DATA
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* b'3:31 - rsvd3: Reserved for future use
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* dword3 - b'0:31 - tlv_filter_mask_in0:
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* dword4 - b'0:31 - tlv_filter_mask_in1:
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* dword5 - b'0:31 - tlv_filter_mask_in2:
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* dword6 - b'0:31 - tlv_filter_mask_in3:
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* dword7 - b'0:15 - tx_fes_setup_word_mask:
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* - b'16:31 - tx_peer_entry_word_mask:
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* dword8 - b'0:15 - tx_queue_ext_word_mask:
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* - b'16:31 - tx_msdu_start_word_mask:
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* dword9 - b'0:15 - tx_mpdu_start_word_mask:
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* - b'16:31 - pcu_ppdu_setup_word_mask:
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* dword10- b'0:15 - rxpcu_user_setup_word_mask:
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* - b'16:18 - pkt_type_msdu_or_mpdu_logging (PT): MGMT, CTRL, DATA
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* Each bit out of 3 bits represents if MSDU/MPDU
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* logging is enabled
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* - b'19:21 - enable_msdu_or_mpdu_logging (EMM): For MGMT, CTRL, DATA
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* 0 -> MSDU level logging is enabled
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* (valid only if bit is set in
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* pkt_type_msdu_or_mpdu_logging)
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* 1 -> MPDU level logging is enabled
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* (valid only if bit is set in
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* pkt_type_msdu_or_mpdu_logging)
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* - b'22:31 - rsvd4 for future use
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*/
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PREPACK struct htt_tx_monitor_cfg_t {
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A_UINT32 msg_type: 8,
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pdev_id: 8,
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ring_id: 8,
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status_swap: 1,
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pkt_swap: 1,
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rsvd1: 6;
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A_UINT32 ring_buffer_size: 16,
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pkt_type_config_length: 3,
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config_length_mgmt: 3,
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config_length_ctrl: 3,
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config_length_data: 3,
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rsvd2: 4;
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A_UINT32 pkt_type_enable_flags: 3,
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rsvd3: 29;
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A_UINT32 tlv_filter_mask_in0;
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A_UINT32 tlv_filter_mask_in1;
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A_UINT32 tlv_filter_mask_in2;
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A_UINT32 tlv_filter_mask_in3;
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A_UINT32 tx_fes_setup_word_mask: 16,
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tx_peer_entry_word_mask: 16;
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A_UINT32 tx_queue_ext_word_mask: 16,
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tx_msdu_start_word_mask: 16;
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A_UINT32 tx_mpdu_start_word_mask: 16,
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pcu_ppdu_setup_word_mask: 16;
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A_UINT32 rxpcu_user_setup_word_mask: 16,
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pkt_type_msdu_or_mpdu_logging: 3,
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enable_msdu_or_mpdu_logging: 3,
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rsvd4: 10;
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} POSTPACK;
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#define HTT_TX_MONITOR_CFG_SZ (sizeof(struct htt_tx_monitor_cfg_t))
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#define HTT_TX_MONITOR_CFG_PDEV_ID_M 0x0000ff00
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#define HTT_TX_MONITOR_CFG_PDEV_ID_S 8
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#define HTT_TX_MONITOR_CFG_PDEV_ID_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_PDEV_ID_M) >> \
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HTT_TX_MONITOR_CFG_PDEV_ID_S)
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#define HTT_TX_MONITOR_CFG_PDEV_ID_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PDEV_ID, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PDEV_ID_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_RING_ID_M 0x00ff0000
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#define HTT_TX_MONITOR_CFG_RING_ID_S 16
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#define HTT_TX_MONITOR_CFG_RING_ID_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_RING_ID_M) >> \
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HTT_TX_MONITOR_CFG_RING_ID_S)
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#define HTT_TX_MONITOR_CFG_RING_ID_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_ID, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_ID_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_STATUS_SWAP_M 0x01000000
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#define HTT_TX_MONITOR_CFG_STATUS_SWAP_S 24
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#define HTT_TX_MONITOR_CFG_STATUS_TLV_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_STATUS_SWAP_M) >> \
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HTT_TX_MONITOR_CFG_STATUS_SWAP_S)
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#define HTT_TX_MONITOR_CFG_STATUS_TLV_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_STATUS_SWAP, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_STATUS_SWAP_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_PKT_SWAP_M 0x02000000
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#define HTT_TX_MONITOR_CFG_PKT_SWAP_S 25
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#define HTT_TX_MONITOR_CFG_PKT_TLV_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_PKT_SWAP_M) >> \
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HTT_TX_MONITOR_CFG_PKT_SWAP_S)
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#define HTT_TX_MONITOR_CFG_PKT_TLV_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_SWAP, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_SWAP_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M 0x0000ffff
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#define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S 0
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#define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M) >> \
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HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S)
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#define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_M 0x00070000
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#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_S 16
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#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_M) >> \
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HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_S)
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#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M 0x00380000
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S 19
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_M) >> \
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HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S)
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_MGMT_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M 0x01C00000
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S 22
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_M) >> \
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HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S)
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_CTRL_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M 0x0E000000
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S 25
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_M) >> \
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HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S)
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#define HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_CONFIG_LENGTH_DATA_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M 0x00000007
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#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S 0
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#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_M) >> \
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HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S)
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#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M 0xffffffff
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#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S 0
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#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M) >> \
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HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S)
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#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TLV_FILTER_MASK, _val); \
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((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S)); \
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} while (0)
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#define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M 0x0000ffff
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#define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S 0
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#define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_GET(_var) \
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(((_var) & HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_M) >> \
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HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S)
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#define HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_FES_SETUP_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M 0xffff0000
|
||||
#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S 16
|
||||
#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_PEER_ENTRY_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M 0x0000ffff
|
||||
#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S 0
|
||||
#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_QUEUE_EXT_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M 0xffff0000
|
||||
#define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S 16
|
||||
#define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MSDU_START_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M 0x0000ffff
|
||||
#define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S 0
|
||||
#define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TX_MPDU_START_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M 0xffff0000
|
||||
#define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S 16
|
||||
#define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PCU_PPDU_SETUP_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M 0x0000ffff
|
||||
#define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S 0
|
||||
#define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RXPCU_USER_SETUP_WORD_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MASK_M 0x00070000
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MASK_S 16
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M 0x00380000
|
||||
#define HTT_TX_MONITOR_CFG_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S 19
|
||||
#define HTT_TX_MONITOR_CFG_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_GET(_var) \
|
||||
(((_var) & HTT_TX_MONITOR_CFG_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_M) >> \
|
||||
HTT_TX_MONITOR_CFG_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S)
|
||||
#define HTT_TX_MONITOR_CFG_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_ENABLE_MSDU_OR_MPDU_LOGGING_MASK, _val); \
|
||||
((_var) |= ((_val) << HTT_TX_MONITOR_CFG_ENABLE_MSDU_OR_MPDU_LOGGING_MASK_S)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* pkt_type_config_length
|
||||
*/
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_MGMT_M 0x00000001
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_MGMT_S 0
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_CTRL_M 0x00000002
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_CTRL_S 1
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_DATA_M 0x00000004
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_CONFIG_LENGTH_DATA_S 2
|
||||
|
||||
/*
|
||||
* pkt_type_enable_flags
|
||||
*/
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_M 0x00010000
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_MGMT_S 16
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_M 0x00020000
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_CTRL_S 17
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_M 0x00040000
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_ENABLE_FLAGS_DATA_S 18
|
||||
|
||||
/*
|
||||
* pkt_type_msdu_or_mpdu_logging
|
||||
* */
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MGMT_M 0x00010000
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_MGMT_S 16
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_CTRL_M 0x00020000
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_CTRL_S 17
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_DATA_M 0x00040000
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_MSDU_OR_MPDU_LOGGING_DATA_S 18
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_SET(word, httsym, value) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(httsym, value); \
|
||||
(word) |= (value) << httsym##_S; \
|
||||
} while (0)
|
||||
#define HTT_TX_MONITOR_CFG_PKT_TYPE_GET(word, httsym) \
|
||||
(((word) & httsym##_M) >> httsym##_S)
|
||||
|
||||
/* mode -> CONFIG_LENGTH, ENABLE_FLAGS, MSDU_OR_MPDU_LOGGING
|
||||
* type -> MGMT, CTRL, DATA*/
|
||||
|
||||
#define htt_tx_ring_pkt_type_set( \
|
||||
word, mode, type, val) \
|
||||
HTT_TX_MONITOR_CFG_PKT_TYPE_SET( \
|
||||
word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type, val)
|
||||
|
||||
#define htt_tx_ring_pkt_type_get( \
|
||||
word, mode, type) \
|
||||
HTT_TX_MONITOR_CFG_PKT_TYPE_GET( \
|
||||
word, HTT_TX_MONITOR_CFG_PKT_TYPE_##mode##_##type)
|
||||
|
||||
/* Definition to filter in TLVs */
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_M 0x00000001
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_S 0
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_M 0x00000002
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_PEER_ENTRY_S 1
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_M 0x00000004
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_QUEUE_EXTENSION_S 2
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_M 0x00000008
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_END_S 3
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_M 0x00000010
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LAST_MPDU_FETCHED_S 4
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_M 0x00000020
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_DATA_SYNC_S 5
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_M 0x00000040
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_PCU_PPDU_SETUP_INIT_S 6
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_M 0x00000080
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_FW2SW_MON_S 7
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_M 0x00000100
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_LOOPBACK_SETUP_S 8
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_M 0x00000200
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_CRITICAL_TLV_REFERENCE_S 9
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_M 0x00000400
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_NDP_PREAMBLE_DONE_S 10
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_M 0x00000800
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_RAW_OR_NATIVE_FRAME_SETUP_S 11
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_M 0x00001000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TXPCU_USER_SETUP_S 12
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_M 0x00002000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_S 13
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_M 0x00004000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_SETUP_COMPLETE_S 14
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_M 0x00008000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_COEX_TX_REQ_S 15
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_M 0x00010000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_S 16
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_M 0x00020000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_RXPCU_USER_SETUP_EXT_S 17
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_M 0x00040000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_WUR_DATA_S 18
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_M 0x00080000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TQM_MPDU_GLOBAL_START_S 19
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_M 0x00100000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_TX_FES_SETUP_COMPLETE_S 20
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_M 0x00200000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCHEDULER_END_S 21
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_M 0x00400000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_SCH_WAIT_INSTR_TX_PATH_S 22
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_M 0x00800000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_S 23
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_M 0x01000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PUNC_S 24
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_M 0x02000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_COMMON_PER_BW_S 25
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_M 0x04000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_S 26
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_M 0x08000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PUNC_S 27
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_M 0x10000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MACTX_MU_UPLINK_USER_SETUP_PER_BW_S 28
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_M 0x20000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_MPDU_QUEUE_OVERVIEW_S 29
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_M 0x40000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_COMMON_S 30
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_M 0x80000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_BF_PARAMS_PER_USER_S 31
|
||||
|
||||
#define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET(word, httsym, enable) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(httsym, enable); \
|
||||
(word) |= (enable) << httsym##_S; \
|
||||
} while (0)
|
||||
#define HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET(word, httsym) \
|
||||
(((word) & httsym##_M) >> httsym##_S)
|
||||
|
||||
#define htt_tx_monitor_tlv_filter_in0_enable_set(word, tlv, enable) \
|
||||
HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_SET( \
|
||||
word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv, enable)
|
||||
|
||||
#define htt_tx_monitor_tlv_filter_in0_enable_get(word, tlv) \
|
||||
HTT_TX_MONITOR_TLV_FILTER_MASK_IN0_GET( \
|
||||
word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN0_##tlv)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_M 0x00000001
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_RESPONSE_REQUIRED_INFO_S 0
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_M 0x00000002
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_START_STATUS_S 1
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_M 0x00000004
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RESPONSE_END_STATUS_S 2
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_M 0x00000008
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_S 3
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_M 0x00000010
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_END_S 4
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_M 0x00000020
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PPDU_S 5
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_M 0x00000040
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_PPDU_S 6
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_M 0x00000080
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_ACK_OR_BA_S 7
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_M 0x00000100
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_1K_BA_S 8
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_M 0x00000200
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_START_PROT_S 9
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_M 0x00000400
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_PROT_S 10
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_M 0x00000800
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TX_FES_STATUS_USER_RESPONSE_S 11
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_M 0x00001000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_BITMAP_ACK_S 12
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_M 0x00002000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RX_FRAME_1K_BITMAP_ACK_S 13
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_M 0x00004000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_COEX_TX_STATUS_S 14
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_M 0x00008000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_S 15
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_M 0x00010000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_RESPONSE_INFO_PART2_S 16
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_M 0x00020000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_OFDMA_TRIGGER_DETAILS_S 17
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_M 0x00040000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_RECEIVED_TRIGGER_INFO_S 18
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_M 0x00080000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TX_REQUEST_S 19
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_M 0x00100000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_RESPONSE_S 20
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_M 0x00200000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PDG_TRIG_RESPONSE_S 21
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_M 0x00400000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_TRIGGER_RESPONSE_TX_DONE_S 22
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_M 0x00800000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PROT_TX_END_S 23
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_M 0x01000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_PPDU_TX_END_S 24
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_M 0x02000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_R2R_STATUS_END_S 25
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_M 0x04000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_FLUSH_REQ_S 26
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_M 0x08000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_PHY_DESC_S 27
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_M 0x10000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_COMMON_S 28
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_M 0x20000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_MACTX_USER_DESC_PER_USER_S 29
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_L_SIG_A_M 0x40000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_L_SIG_A_S 30
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_L_SIG_B_M 0x80000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_L_SIG_B_S 31
|
||||
|
||||
#define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET(word, httsym, enable) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(httsym, enable); \
|
||||
(word) |= (enable) << httsym##_S; \
|
||||
} while (0)
|
||||
#define HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET(word, httsym) \
|
||||
(((word) & httsym##_M) >> httsym##_S)
|
||||
|
||||
#define htt_tx_monitor_tlv_filter_in1_enable_set(word, tlv, enable) \
|
||||
HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_SET( \
|
||||
word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv, enable)
|
||||
|
||||
#define htt_tx_monitor_tlv_filter_in1_enable_get(word, tlv) \
|
||||
HTT_TX_MONITOR_TLV_FILTER_MASK_IN1_GET( \
|
||||
word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN1_##tlv)
|
||||
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_M 0x00000001
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HT_SIG_S 0
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_M 0x00000002
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_A_S 1
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_M 0x00000004
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU20_S 2
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_M 0x00000008
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU40_S 3
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_M 0x00000010
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU80_S 4
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_M 0x00000020
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_SU160_S 5
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_M 0x00000040
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU20_S 6
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_M 0x00000080
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU40_S 7
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_M 0x00000100
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU80_S 8
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_M 0x00000200
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_VHT_SIG_B_MU160_S 9
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_M 0x00000400
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TX_SERVICE_S 10
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_M 0x00000800
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_SU_S 11
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_M 0x00001000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_DL_S 12
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_M 0x00002000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_A_MU_UL_S 13
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_M 0x00004000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B1_MU_S 14
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_M 0x00008000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_MU_S 15
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_M 0x00010000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_HE_SIG_B2_OFDMA_S 16
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_M 0x00020000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_MU_S 17
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_M 0x00040000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_SU_S 18
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_M 0x00080000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_U_SIG_EHT_TB_S 19
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_M 0x00100000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_SU_S 20
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_M 0x00200000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_MU_MIMO_S 21
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_M 0x00400000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_EHT_SIG_USR_OFDMA_S 22
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_M 0x00800000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_PHYTX_PPDU_HEADER_INFO_REQUEST_S 23
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_M 0x01000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_UPDATE_TX_MPDU_COUNT_S 24
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_M 0x02000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_MPDU_S 25
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_M 0x04000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_TQM_ACKED_1K_MPDU_S 26
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_BUFFER_STATUS_M 0x08000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_BUFFER_STATUS_S 27
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_USER_BUFFER_STATUS_M 0x10000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_USER_BUFFER_STATUS_S 28
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXDMA_STOP_REQUEST_M 0x20000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXDMA_STOP_REQUEST_S 29
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_EXPECTED_RESPONSE_M 0x40000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_EXPECTED_RESPONSE_S 30
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_MPDU_COUNT_TRANSFER_END_M 0x80000000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_MPDU_COUNT_TRANSFER_END_S 31
|
||||
|
||||
#define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET(word, httsym, enable) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(httsym, enable); \
|
||||
(word) |= (enable) << httsym##_S; \
|
||||
} while (0)
|
||||
#define HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET(word, httsym) \
|
||||
(((word) & httsym##_M) >> httsym##_S)
|
||||
|
||||
#define htt_tx_monitor_tlv_filter_in2_enable_set(word, tlv, enable) \
|
||||
HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_SET( \
|
||||
word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv, enable)
|
||||
|
||||
#define htt_tx_monitor_tlv_filter_in2_enable_get(word, tlv) \
|
||||
HTT_TX_MONITOR_TLV_FILTER_MASK_IN2_GET( \
|
||||
word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN2_##tlv)
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_M 0x00000001
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_TRIG_INFO_S 0
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_M 0x00000002
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_TX_SETUP_CLEAR_S 1
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_M 0x00000004
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_FRAME_BITMAP_REQ_S 2
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_M 0x00000008
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PHY_SLEEP_S 3
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_M 0x00000010
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PREAMBLE_DONE_S 4
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_M 0x00000020
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_DEBUG32_S 5
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_M 0x00000040
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_S 6
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_M 0x00000080
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_NO_ACK_REPORT_S 7
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_M 0x00000100
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PPDU_ACK_REPORT_S 8
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_M 0x00000200
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_COEX_RX_STATUS_S 9
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_M 0x00000400
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_START_PARAM_S 10
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_M 0x00000800
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_TX_CBF_INFO_S 11
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_M 0x00001000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RXPCU_EARLY_RX_INDICATION_S 12
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_M 0x00002000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_7_0_S 13
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_M 0x00004000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_15_8_S 14
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_M 0x00008000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_23_16_S 15
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_M 0x00010000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_31_24_S 16
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_M 0x00020000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RECEIVED_RESPONSE_USER_36_32_S 17
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_M 0x00040000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PM_INFO_S 18
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_M 0x00080000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_RX_PREAMBLE_S 19
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_M 0x00100000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_OTHERS_S 20
|
||||
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_M 0x00200000
|
||||
#define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_MACTX_PRE_PHY_DESC_S 21
|
||||
|
||||
#define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET(word, httsym, enable) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(httsym, enable); \
|
||||
(word) |= (enable) << httsym##_S; \
|
||||
} while (0)
|
||||
#define HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET(word, httsym) \
|
||||
(((word) & httsym##_M) >> httsym##_S)
|
||||
|
||||
#define htt_tx_monitor_tlv_filter_in3_enable_set(word, tlv, enable) \
|
||||
HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_SET( \
|
||||
word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv, enable)
|
||||
|
||||
#define htt_tx_monitor_tlv_filter_in3_enable_get(word, tlv) \
|
||||
HTT_TX_MONITOR_TLV_FILTER_MASK_IN3_GET( \
|
||||
word, HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_IN3_##tlv)
|
||||
|
||||
/**
|
||||
* @brief host --> target Receive Flow Steering configuration message definition
|
||||
*
|
||||
|
|
|
|||
|
|
@ -375,6 +375,13 @@ enum HTT_STATS_FTYPE {
|
|||
HTT_STATS_FTYPE_TIDQ_DATA_MU,
|
||||
HTT_STATS_FTYPE_SGEN_UL_BSR_RESP,
|
||||
HTT_STATS_FTYPE_SGEN_QOS_NULL,
|
||||
HTT_STATS_FTYPE_SGEN_BE_NDPA,
|
||||
HTT_STATS_FTYPE_SGEN_BE_NDP,
|
||||
HTT_STATS_FTYPE_SGEN_BE_MU_TRIG,
|
||||
HTT_STATS_FTYPE_SGEN_BE_MU_BAR,
|
||||
HTT_STATS_FTYPE_SGEN_BE_MU_BRP,
|
||||
HTT_STATS_FTYPE_SGEN_BE_MU_RTS,
|
||||
HTT_STATS_FTYPE_SGEN_BE_MU_BSRP,
|
||||
HTT_STATS_FTYPE_MAX,
|
||||
};
|
||||
typedef enum HTT_STATS_FTYPE HTT_STATS_FTYPE;
|
||||
|
|
@ -416,6 +423,7 @@ enum HTT_PPDU_STATS_BW {
|
|||
HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4,
|
||||
HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
|
||||
HTT_PPDU_STATS_BANDWIDTH_DYN = 6,
|
||||
HTT_PPDU_STATS_BANDWIDTH_DYN_PATTERNS = 7,
|
||||
};
|
||||
typedef enum HTT_PPDU_STATS_BW HTT_PPDU_STATS_BW;
|
||||
|
||||
|
|
@ -1527,6 +1535,24 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE;
|
|||
((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_RESP_PPDU_TYPE_S)); \
|
||||
} while (0)
|
||||
|
||||
typedef enum HTT_PPDU_STATS_RU_SIZE {
|
||||
HTT_PPDU_STATS_RU_26,
|
||||
HTT_PPDU_STATS_RU_52,
|
||||
HTT_PPDU_STATS_RU_52_26,
|
||||
HTT_PPDU_STATS_RU_106,
|
||||
HTT_PPDU_STATS_RU_106_26,
|
||||
HTT_PPDU_STATS_RU_242,
|
||||
HTT_PPDU_STATS_RU_484,
|
||||
HTT_PPDU_STATS_RU_484_242,
|
||||
HTT_PPDU_STATS_RU_996,
|
||||
HTT_PPDU_STATS_RU_996_484,
|
||||
HTT_PPDU_STATS_RU_996_484_242,
|
||||
HTT_PPDU_STATS_RU_996x2,
|
||||
HTT_PPDU_STATS_RU_996x2_484,
|
||||
HTT_PPDU_STATS_RU_996x3,
|
||||
HTT_PPDU_STATS_RU_996x3_484,
|
||||
HTT_PPDU_STATS_RU_996x4,
|
||||
} HTT_PPDU_STATS_RU_SIZE;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
|
@ -1546,36 +1572,68 @@ typedef struct {
|
|||
|
||||
/* BIT [ 3 : 0] :- user_pos
|
||||
* BIT [ 11: 4] :- mu_group_id
|
||||
* BIT [ 31: 12] :- reserved1
|
||||
* BIT [ 15: 12] :- ru_format
|
||||
* BIT [ 31: 16] :- reserved1
|
||||
*/
|
||||
union {
|
||||
A_UINT32 mu_group_id__user_pos;
|
||||
struct {
|
||||
A_UINT32 user_pos: 4,
|
||||
mu_group_id: 8,
|
||||
reserved1: 20;
|
||||
ru_format: 4,
|
||||
reserved1: 16;
|
||||
};
|
||||
};
|
||||
|
||||
/* BIT [ 15 : 0] :- ru_end
|
||||
* BIT [ 31 : 16] :- ru_start
|
||||
/* BIT [ 15 : 0] :- ru_end or ru_index
|
||||
* BIT [ 31 : 16] :- ru_start or ru_size
|
||||
*
|
||||
* Discriminant is field ru_format:
|
||||
* - ru_format = 0: ru_end, ru_start
|
||||
* - ru_format = 1: ru_index, ru_size
|
||||
* - ru_format = other: reserved for future expansion
|
||||
*
|
||||
* ru_start and ru_end are RU 26 indices
|
||||
*
|
||||
* ru_size is an HTT_PPDU_STATS_RU_SIZE, ru_index is a size
|
||||
* specific index for the given ru_size.
|
||||
*/
|
||||
union {
|
||||
A_UINT32 ru_start__ru_end;
|
||||
A_UINT32 ru_size__ru_index;
|
||||
struct {
|
||||
A_UINT32 ru_end: 16,
|
||||
ru_start: 16;
|
||||
A_UINT32 ru_end: 16,
|
||||
ru_start: 16;
|
||||
};
|
||||
struct {
|
||||
A_UINT32 ru_index: 16,
|
||||
ru_size: 16;
|
||||
};
|
||||
};
|
||||
|
||||
/* BIT [ 15 : 0] :- ru_end
|
||||
* BIT [ 31 : 16] :- ru_start
|
||||
/* BIT [ 15 : 0] :- resp_ru_end or resp_ru_index
|
||||
* BIT [ 31 : 16] :- resp_ru_start or resp_ru_size
|
||||
*
|
||||
* Discriminant is field ru_format:
|
||||
* - ru_format = 0: resp_ru_end, resp_ru_start
|
||||
* - ru_format = 1: resp_ru_index, resp_ru_size
|
||||
* - ru_format = other: reserved for future expansion
|
||||
*
|
||||
* resp_ru_start and resp_ru_end are RU 26 indices
|
||||
*
|
||||
* resp_ru_size is an HTT_PPDU_STATS_RU_SIZE, resp_ru_index
|
||||
* is a size specific index for the given ru_size.
|
||||
*/
|
||||
union {
|
||||
A_UINT32 resp_ru_start__ru_end;
|
||||
A_UINT32 resp_ru_size__ru_index;
|
||||
struct {
|
||||
A_UINT32 resp_ru_end: 16,
|
||||
resp_ru_start: 16;
|
||||
A_UINT32 resp_ru_end: 16,
|
||||
resp_ru_start: 16;
|
||||
};
|
||||
struct {
|
||||
A_UINT32 resp_ru_index: 16,
|
||||
resp_ru_size: 16;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
204
fw/htt_stats.h
204
fw/htt_stats.h
|
|
@ -26,6 +26,7 @@
|
|||
|
||||
#include <htt_deps.h> /* A_UINT32 */
|
||||
#include <htt_common.h>
|
||||
#include <htt.h> /* HTT stats TLV struct def and tag defs */
|
||||
|
||||
/*
|
||||
* htt_dbg_ext_stats_type -
|
||||
|
|
@ -342,7 +343,7 @@ enum htt_dbg_ext_stats_type {
|
|||
* PARAMS:
|
||||
* - No Params
|
||||
* RESP MSG:
|
||||
* - htt_tx_pdev_rate_txbf_stats_t
|
||||
* - htt_tx_pdev_txbf_rate_stats_t
|
||||
*/
|
||||
HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF = 31,
|
||||
|
||||
|
|
@ -402,6 +403,14 @@ enum htt_dbg_ext_stats_type {
|
|||
|
||||
HTT_DBG_EXT_VDEV_RTT_INITIATOR_STATS = 39,
|
||||
|
||||
/* HTT_DBG_EXT_PDEV_PER_STATS
|
||||
* PARAMS:
|
||||
* - No Params
|
||||
* RESP MSG:
|
||||
* - htt_tx_pdev_per_stats_t
|
||||
*/
|
||||
HTT_DBG_EXT_PDEV_PER_STATS = 40,
|
||||
|
||||
|
||||
/* keep this last */
|
||||
HTT_DBG_NUM_EXT_STATS = 256,
|
||||
|
|
@ -632,7 +641,7 @@ typedef struct {
|
|||
A_UINT32 next_seq_cancel;
|
||||
/* Num of times fes offset was misaligned */
|
||||
A_UINT32 fes_offsets_err_cnt;
|
||||
/* Num of times peer blacklisted for MU-MIMO transmission */
|
||||
/* Num of times peer denylisted for MU-MIMO transmission */
|
||||
A_UINT32 num_mu_peer_blacklisted;
|
||||
/* Num of times mu_ofdma seq posted */
|
||||
A_UINT32 mu_ofdma_seq_posted;
|
||||
|
|
@ -658,6 +667,10 @@ typedef struct {
|
|||
* 3 -> Tx Abort Module
|
||||
*/
|
||||
A_UINT32 last_suspend_reason;
|
||||
/* Num of dynamic mimo ps dlmumimo sequences posted */
|
||||
A_UINT32 num_dyn_mimo_ps_dlmumimo_sequences;
|
||||
/* Num of times su bf sequences are denylisted */
|
||||
A_UINT32 num_su_txbf_denylisted;
|
||||
} htt_tx_pdev_stats_cmn_tlv;
|
||||
|
||||
#define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
|
||||
|
|
@ -704,6 +717,49 @@ typedef struct {
|
|||
A_UINT32 num_data_ppdus_ax_su_txbf;
|
||||
} htt_tx_pdev_stats_tx_ppdu_stats_tlv_v;
|
||||
|
||||
typedef enum {
|
||||
HTT_TX_WAL_ISR_SCHED_SUCCESS,
|
||||
HTT_TX_WAL_ISR_SCHED_FILTER,
|
||||
HTT_TX_WAL_ISR_SCHED_RESP_TIMEOUT,
|
||||
HTT_TX_WAL_ISR_SCHED_RATES_EXHAUSTED,
|
||||
HTT_TX_WAL_ISR_SCHED_DATA_EXHAUSTED,
|
||||
HTT_TX_WAL_ISR_SCHED_SEQ_ABORT,
|
||||
HTT_TX_WAL_ISR_SCHED_NOTIFY_FRAME_ENCOUNTERED,
|
||||
HTT_TX_WAL_ISR_SCHED_COMPLETION,
|
||||
HTT_TX_WAL_ISR_SCHED_IN_PROGRESS,
|
||||
} htt_tx_wal_tx_isr_sched_status;
|
||||
|
||||
/* [0]- nr4 , [1]- nr8 */
|
||||
#define HTT_STATS_NUM_NR_BINS 2
|
||||
/* Termination status stated in htt_tx_wal_tx_isr_sched_status */
|
||||
#define HTT_STATS_MAX_NUM_SCHED_STATUS 9
|
||||
#define HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10
|
||||
#define HTT_STATS_MAX_NUM_SCHED_STATUS_WORDS \
|
||||
(HTT_STATS_NUM_NR_BINS * HTT_STATS_MAX_NUM_SCHED_STATUS)
|
||||
#define HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS \
|
||||
(HTT_STATS_NUM_NR_BINS * HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST)
|
||||
|
||||
typedef enum {
|
||||
HTT_STATS_HWMODE_AC = 0,
|
||||
HTT_STATS_HWMODE_AX = 1,
|
||||
HTT_STATS_HWMODE_BE = 2,
|
||||
} htt_stats_hw_mode;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
||||
A_UINT32 hw_mode; /* HTT_STATS_HWMODE_xx */
|
||||
|
||||
A_UINT32 mu_mimo_num_seq_term_status[HTT_STATS_MAX_NUM_SCHED_STATUS_WORDS];
|
||||
|
||||
A_UINT32 mu_mimo_num_ppdu_completed_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS];
|
||||
|
||||
A_UINT32 mu_mimo_num_seq_posted[HTT_STATS_NUM_NR_BINS];
|
||||
|
||||
A_UINT32 mu_mimo_num_ppdu_posted_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS];
|
||||
|
||||
} htt_pdev_mu_ppdu_dist_tlv_v;
|
||||
|
||||
#define HTT_TX_PDEV_STATS_TRIED_MPDU_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
|
||||
/* NOTE: Variable length TLV, use length spec to infer array size .
|
||||
*
|
||||
|
|
@ -741,6 +797,7 @@ typedef struct {
|
|||
* - HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG
|
||||
* - HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG
|
||||
* - HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG
|
||||
* - HTT_STATS_MU_PPDU_DIST_TAG
|
||||
*/
|
||||
/* NOTE:
|
||||
* This structure is for documentation, and cannot be safely used directly.
|
||||
|
|
@ -756,6 +813,7 @@ typedef struct _htt_tx_pdev_stats {
|
|||
htt_tx_pdev_stats_tx_ppdu_stats_tlv_v tx_su_tlv;
|
||||
htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v tried_mpdu_cnt_hist_tlv;
|
||||
htt_pdev_ctrl_path_tx_stats_tlv_v ctrl_path_tx_tlv;
|
||||
htt_pdev_mu_ppdu_dist_tlv_v mu_ppdu_dist_tlv;
|
||||
} htt_tx_pdev_stats_t;
|
||||
|
||||
/* == SOC ERROR STATS == */
|
||||
|
|
@ -1237,6 +1295,7 @@ typedef enum {
|
|||
#define HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4
|
||||
#define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8
|
||||
#define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
|
||||
#define HTT_TX_PEER_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */
|
||||
|
||||
typedef struct _htt_tx_peer_rate_stats_tlv {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
|
@ -1268,6 +1327,7 @@ typedef struct _htt_tx_peer_rate_stats_tlv {
|
|||
A_UINT32 tx_mu_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
|
||||
A_UINT32 tx_stbc_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
|
||||
A_UINT32 tx_gi_ext[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
|
||||
A_UINT32 reduced_tx_bw[HTT_TX_PEER_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PEER_STATS_NUM_BW_COUNTERS];
|
||||
} htt_tx_peer_rate_stats_tlv;
|
||||
|
||||
#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
|
||||
|
|
@ -1277,6 +1337,7 @@ typedef struct _htt_tx_peer_rate_stats_tlv {
|
|||
#define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4
|
||||
#define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8
|
||||
#define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
|
||||
#define HTT_RX_PEER_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */
|
||||
|
||||
typedef struct _htt_rx_peer_rate_stats_tlv {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
|
@ -1328,6 +1389,8 @@ typedef struct _htt_rx_peer_rate_stats_tlv {
|
|||
A_UINT32 rx_mcs_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
|
||||
A_UINT32 rx_stbc_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
|
||||
A_UINT32 rx_gi_ext[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS];
|
||||
A_UINT32 reduced_rx_bw[HTT_RX_PEER_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PEER_STATS_NUM_BW_COUNTERS];
|
||||
A_INT8 rx_per_chain_rssi_in_dbm_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS];
|
||||
} htt_rx_peer_rate_stats_tlv;
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -1755,10 +1818,36 @@ typedef enum {
|
|||
HTT_TX_SELFGEN_SCH_TSFLAG_ERROR_STATS_VALID = 8
|
||||
} htt_tx_selfgen_sch_tsflag_error_stats;
|
||||
|
||||
typedef enum {
|
||||
HTT_TX_MUMIMO_GRP_VALID,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE,
|
||||
HTT_TX_MUMIMO_GRP_INVALID,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS,
|
||||
HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE,
|
||||
} htt_tx_mumimo_grp_invalid_reason_code_stats;
|
||||
|
||||
#define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4
|
||||
#define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8
|
||||
#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74
|
||||
#define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8
|
||||
#define HTT_STATS_MAX_MUMIMO_GRP_SZ 8
|
||||
/*
|
||||
* Each bin represents a 300 mbps throughput
|
||||
* [0] - 0-300mbps; [1] - 300-600mbps [2] - 600-900mbps; [3] - 900-1200mbps; [4] - 1200-1500mbps
|
||||
* [5] - 1500-1800mbps; [6] - 1800-2100mbps; [7] - 2100-2400mbps; [8] - 2400-2700mbps; [9] - >=2700mbps
|
||||
*/
|
||||
#define HTT_STATS_MUMIMO_TPUT_NUM_BINS 10
|
||||
#define HTT_STATS_MAX_INVALID_REASON_CODE \
|
||||
HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE
|
||||
/* Reasons stated in htt_tx_mumimo_grp_invalid_reason_code_stats */
|
||||
#define HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \
|
||||
(HTT_STATS_MAX_MUMIMO_GRP_SZ * HTT_STATS_MAX_INVALID_REASON_CODE)
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
|
@ -2111,6 +2200,28 @@ typedef struct {
|
|||
A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
|
||||
} htt_tx_pdev_mu_mimo_sch_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 dl_mumimo_grp_best_grp_size[HTT_STATS_MAX_MUMIMO_GRP_SZ];
|
||||
|
||||
A_UINT32 dl_mumimo_grp_best_num_usrs[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
|
||||
|
||||
A_UINT32 dl_mumimo_grp_eligible[HTT_STATS_MAX_MUMIMO_GRP_SZ];
|
||||
|
||||
A_UINT32 dl_mumimo_grp_ineligible[HTT_STATS_MAX_MUMIMO_GRP_SZ];
|
||||
|
||||
A_UINT32 dl_mumimo_grp_invalid[HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS];
|
||||
|
||||
A_UINT32 dl_mumimo_grp_tputs[HTT_STATS_MUMIMO_TPUT_NUM_BINS];
|
||||
|
||||
A_UINT32 ul_mumimo_grp_best_grp_size[HTT_STATS_MAX_MUMIMO_GRP_SZ];
|
||||
|
||||
A_UINT32 ul_mumimo_grp_best_num_usrs[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
|
||||
|
||||
A_UINT32 ul_mumimo_grp_tputs[HTT_STATS_MUMIMO_TPUT_NUM_BINS];
|
||||
|
||||
} htt_tx_pdev_mumimo_grp_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 mu_mimo_sch_posted; /* Number of MU MIMO schedules posted to HW */
|
||||
|
|
@ -2228,6 +2339,7 @@ typedef struct {
|
|||
* it can also hold MU-OFDMA stats.
|
||||
*/
|
||||
htt_tx_pdev_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; /* WAL_TX_STATS_MAX_NUM_USERS */
|
||||
htt_tx_pdev_mumimo_grp_stats_tlv mumimo_grp_stats_tlv;
|
||||
} htt_tx_pdev_mu_mimo_stats_t;
|
||||
|
||||
/* == TX SCHED STATS == */
|
||||
|
|
@ -3439,6 +3551,8 @@ typedef enum {
|
|||
HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS = 5
|
||||
} HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_TYPE;
|
||||
|
||||
#define HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
||||
|
|
@ -3545,6 +3659,13 @@ typedef struct {
|
|||
A_UINT32 tx_bw_320mhz;
|
||||
A_UINT32 tx_gi_ext_2[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS];
|
||||
A_UINT32 tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
|
||||
A_UINT32 reduced_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
|
||||
/* 11AC VHT DL MU MIMO TX BW stats at reduced channel config */
|
||||
A_UINT32 reduced_ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
|
||||
/* 11AX HE DL MU MIMO TX BW stats at reduced channel config */
|
||||
A_UINT32 reduced_ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
|
||||
/* 11AX HE DL MU OFDMA TX BW stats at reduced channel config */
|
||||
A_UINT32 reduced_ax_mu_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
|
||||
} htt_tx_pdev_rate_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE
|
||||
|
|
@ -3622,6 +3743,8 @@ typedef enum {
|
|||
HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS = 5
|
||||
} HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_TYPE;
|
||||
|
||||
#define HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
||||
|
|
@ -3771,6 +3894,7 @@ typedef struct {
|
|||
A_UINT32 rx_bw_ext[HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS];
|
||||
A_UINT32 rx_gi_ext_2[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS];
|
||||
A_UINT32 rx_su_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
|
||||
A_UINT32 reduced_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
|
||||
} htt_rx_pdev_rate_ext_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT
|
||||
|
|
@ -3849,6 +3973,7 @@ typedef struct {
|
|||
* Trig power headroom for STA AID in same idx - UNIT(dB)
|
||||
*/
|
||||
A_UINT32 uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
|
||||
A_UINT32 reduced_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
|
||||
} htt_rx_pdev_ul_trigger_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
|
||||
|
|
@ -3930,6 +4055,7 @@ typedef struct {
|
|||
A_INT8 rx_ul_mumimo_fd_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS];
|
||||
/* Average pilot EVM measued for RX UL TB PPDU */
|
||||
A_INT8 rx_ulmumimo_pilot_evm_dB_mean[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS];
|
||||
A_UINT32 reduced_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
|
||||
} htt_rx_pdev_ul_mumimo_trig_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS
|
||||
|
|
@ -4621,6 +4747,34 @@ typedef struct {
|
|||
* ... where max_bw == 4 for 160mhz
|
||||
*/
|
||||
A_UINT32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS];
|
||||
|
||||
/* cv upload handler stats */
|
||||
A_UINT32 cv_nc_mismatch_err;
|
||||
A_UINT32 cv_fcs_err;
|
||||
A_UINT32 cv_frag_idx_mismatch;
|
||||
A_UINT32 cv_invalid_peer_id;
|
||||
A_UINT32 cv_no_txbf_setup;
|
||||
A_UINT32 cv_expiry_in_update;
|
||||
A_UINT32 cv_pkt_bw_exceed;
|
||||
A_UINT32 cv_dma_not_done_err;
|
||||
A_UINT32 cv_update_failed;
|
||||
/* cv query stats */
|
||||
A_UINT32 cv_total_query;
|
||||
A_UINT32 cv_total_pattern_query;
|
||||
A_UINT32 cv_total_bw_query;
|
||||
A_UINT32 cv_invalid_bw_coding;
|
||||
A_UINT32 cv_forced_sounding;
|
||||
A_UINT32 cv_standalone_sounding;
|
||||
A_UINT32 cv_nc_mismatch;
|
||||
A_UINT32 cv_fb_type_mismatch;
|
||||
A_UINT32 cv_ofdma_bw_mismatch;
|
||||
A_UINT32 cv_bw_mismatch;
|
||||
A_UINT32 cv_pattern_mismatch;
|
||||
A_UINT32 cv_preamble_mismatch;
|
||||
A_UINT32 cv_nr_mismatch;
|
||||
A_UINT32 cv_in_use_cnt_exceeded;
|
||||
A_UINT32 cv_found;
|
||||
A_UINT32 cv_not_found;
|
||||
} htt_tx_sounding_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO
|
||||
|
|
@ -4984,6 +5138,8 @@ typedef struct {
|
|||
#define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14
|
||||
#define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 /* 20, 40, 80, 160, 320 */
|
||||
|
||||
#define HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES 2/* 0: Half, 1: Quarter */
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
/* SU TxBF TX MCS stats */
|
||||
|
|
@ -5006,8 +5162,45 @@ typedef struct {
|
|||
A_UINT32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
|
||||
/* Legacy and OFDM TX rate stats */
|
||||
A_UINT32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
|
||||
/* SU TxBF TX BW stats */
|
||||
A_UINT32 reduced_tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
|
||||
/* Implicit BF TX BW stats */
|
||||
A_UINT32 reduced_tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
|
||||
/* Open loop TX BW stats */
|
||||
A_UINT32 reduced_tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
|
||||
} htt_tx_pdev_txbf_rate_stats_tlv;
|
||||
|
||||
typedef enum {
|
||||
HTT_STATS_RC_MODE_DLSU = 0,
|
||||
HTT_STATS_RC_MODE_DLMUMIMO = 1,
|
||||
} htt_stats_rc_mode;
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 ppdus_tried;
|
||||
A_UINT32 ppdus_ack_failed;
|
||||
A_UINT32 mpdus_tried;
|
||||
A_UINT32 mpdus_failed;
|
||||
} htt_tx_rate_stats_t;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
||||
A_UINT32 rc_mode; /* HTT_STATS_RC_MODE_XX */
|
||||
|
||||
A_UINT32 last_probed_mcs;
|
||||
|
||||
A_UINT32 last_probed_nss;
|
||||
|
||||
A_UINT32 last_probed_bw;
|
||||
|
||||
htt_tx_rate_stats_t per_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
|
||||
|
||||
htt_tx_rate_stats_t per_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
|
||||
|
||||
htt_tx_rate_stats_t per_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
|
||||
|
||||
} htt_tx_rate_stats_per_tlv;
|
||||
|
||||
/* NOTE:
|
||||
* This structure is for documentation, and cannot be safely used directly.
|
||||
* Instead, use the constituent TLV structures to fill/parse.
|
||||
|
|
@ -5016,6 +5209,10 @@ typedef struct {
|
|||
htt_tx_pdev_txbf_rate_stats_tlv txbf_rate_stats;
|
||||
} htt_pdev_txbf_rate_stats_t;
|
||||
|
||||
typedef struct {
|
||||
htt_tx_rate_stats_per_tlv per_stats;
|
||||
} htt_tx_pdev_per_stats_t;
|
||||
|
||||
typedef enum {
|
||||
HTT_ULTRIG_QBOOST_TRIGGER = 0,
|
||||
HTT_ULTRIG_PSPOLL_TRIGGER,
|
||||
|
|
@ -5055,6 +5252,7 @@ typedef enum {
|
|||
#define HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS 14
|
||||
/* Counters BW 20,40,80,160,320 */
|
||||
#define HTT_STA_UL_OFDMA_NUM_BW_COUNTERS 5
|
||||
#define HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STA_11AX_UL_STATS
|
||||
* TLV_TAGS:
|
||||
|
|
@ -5108,7 +5306,7 @@ typedef struct {
|
|||
A_UINT32 current_cw_max[HTT_NUM_AC_WMM];
|
||||
/* AIFS value - 0 -255 */
|
||||
A_UINT32 current_aifs[HTT_NUM_AC_WMM];
|
||||
|
||||
A_UINT32 reduced_ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES][HTT_STA_UL_OFDMA_NUM_BW_COUNTERS];
|
||||
} htt_sta_ul_ofdma_stats_tlv;
|
||||
|
||||
/* NOTE:
|
||||
|
|
|
|||
|
|
@ -1197,6 +1197,7 @@ typedef enum {
|
|||
WMITLV_TAG_STRUC_wmi_roam_btm_request_candidate_info_tlv_param,
|
||||
WMITLV_TAG_STRUC_wmi_thermal_stats_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_thermal_throt_temp_range_stats,
|
||||
WMITLV_TAG_STRUC_wmi_ctrl_path_awgn_stats_struct,
|
||||
} WMITLV_TAG_ID;
|
||||
|
||||
/*
|
||||
|
|
@ -6154,7 +6155,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_mem_stats_struct, ctrl_path_mem_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_twt_stats_struct, ctrl_path_twt_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_calibration_stats_struct, ctrl_path_calibration_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_dfs_channel_stats_struct, ctrl_path_dfs_channel_stats, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_dfs_channel_stats_struct, ctrl_path_dfs_channel_stats, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_awgn_stats_struct, ctrl_path_awgn_stats, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_RADIO_CHAN_STATS_EVENTID(id, op, buf, len) \
|
||||
|
|
|
|||
224
fw/wmi_unified.h
224
fw/wmi_unified.h
|
|
@ -3895,8 +3895,13 @@ typedef struct {
|
|||
* 1-> enable the feature
|
||||
* Refer to the WMI_RSRC_CFG_FLAGS2_IS_DYNAMIC_PCIE_GEN_SPEED_SWITCH_ENABLED
|
||||
* GET/SET macros.
|
||||
* Bit 9 - calc_next_dtim_count
|
||||
* 0 -> disable calculation of DTIM count for MBSSID_NON_TX_VAP
|
||||
* 1 -> Used by some hosts to indicate calculation of DTIM count
|
||||
* for MBSSID_NON_TX_VAP
|
||||
* Refer to WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_GET/SET macros.
|
||||
*
|
||||
* Bits 31:9 - Reserved
|
||||
* Bits 31:10 - Reserved
|
||||
*/
|
||||
A_UINT32 flags2;
|
||||
/** @brief host_service_flags - can be used by Host to indicate
|
||||
|
|
@ -3938,7 +3943,36 @@ typedef struct {
|
|||
* Refer to the below definitions of the
|
||||
* WMI_RSRC_CFG_HOST_SERVICE_FLAG_REG_CC_EXT_SUPPORT_GET
|
||||
* and _SET macros.
|
||||
* Bits 31:5 - Reserved
|
||||
* Bit 5
|
||||
* This bit will be set when the host supports NAN channels.
|
||||
* Refer to WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_CHANNEL_SUPPORT_GET/SET
|
||||
* Bit 6
|
||||
* This bit will be set when the host supports synchronous TWT events.
|
||||
* Refer to WMI_RSRC_CFG_HOST_SERVICE_FLAG_STA_TWT_SYNC_EVT_SUPPORT_GET
|
||||
* and _SET.
|
||||
* Bit 7
|
||||
* This bit will be set when host supports both LPI and SP mode.
|
||||
* when this bit is set to 0 - Indicate LPI only mode
|
||||
* when set to 1 - Indicate both SP mode and LPI mode
|
||||
* both are supported
|
||||
* Refer to the below definitions of the
|
||||
* WMI_RSRC_CFG_HOST_SERVICE_FLAG_LPI_SP_MODE_SUPPORT_GET
|
||||
* and _SET macros.
|
||||
* Bit 8
|
||||
* This bit will be set when host wants to disable timer check in
|
||||
* reg for AFC.
|
||||
* when set to 1 - Disable timer check
|
||||
* Refer to the below definitions of the
|
||||
* WMI_RSRC_CFG_HOST_SERVICE_FLAG_REG_DISCARD_TIMER_CHECK_GET
|
||||
* and _SET macros.
|
||||
* Bit 9
|
||||
* This bit will be set when host host wants to disable request id
|
||||
* check in reg for AFC.
|
||||
* when set to 1 - Disable Request ID check
|
||||
* Refer to the below definitions of the
|
||||
* WMI_RSRC_CFG_HOST_SERVICE_FLAG_REG_DISCARD_REQ_ID_CHECK_GET
|
||||
* and _SET macros.
|
||||
* Bits 31:10 - Reserved
|
||||
*/
|
||||
A_UINT32 host_service_flags;
|
||||
|
||||
|
|
@ -3998,6 +4032,13 @@ typedef struct {
|
|||
* default beacon size (1500) is used.
|
||||
*/
|
||||
A_UINT32 ema_init_config;
|
||||
|
||||
/** @brief carrier_config
|
||||
* Carrier profile configuration
|
||||
* BIT 0 -> enable/disable charter configurations
|
||||
* BIT 1 : 31 Reserved
|
||||
*/
|
||||
A_UINT32 carrier_config;
|
||||
} wmi_resource_config;
|
||||
|
||||
#define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \
|
||||
|
|
@ -4222,6 +4263,11 @@ typedef struct {
|
|||
#define WMI_RSRC_CFG_FLAGS2_IS_DYNAMIC_PCIE_GEN_SPEED_SWITCH_ENABLED_SET(flags2, value) \
|
||||
WMI_SET_BITS(flags2, 8, 1, value)
|
||||
|
||||
#define WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_GET(flags2) \
|
||||
WMI_GET_BITS(flags2, 9, 1)
|
||||
#define WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_SET(flags2, value) \
|
||||
WMI_SET_BITS(flags2, 9, 1, value)
|
||||
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \
|
||||
WMI_GET_BITS(host_service_flags, 0, 1)
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_SET(host_service_flags, val) \
|
||||
|
|
@ -4257,6 +4303,26 @@ typedef struct {
|
|||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_STA_TWT_SYNC_EVT_SUPPORT_SET(host_service_flags, val) \
|
||||
WMI_SET_BITS(host_service_flags, 6, 1, val)
|
||||
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_LPI_SP_MODE_SUPPORT_GET(host_service_flags) \
|
||||
WMI_GET_BITS(host_service_flags, 7, 1)
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_LPI_SP_MODE_SUPPORT_SET(host_service_flags, val) \
|
||||
WMI_SET_BITS(host_service_flags, 7, 1, val)
|
||||
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_REG_DISCARD_AFC_TIMER_CHECK_GET(host_service_flags) \
|
||||
WMI_GET_BITS(host_service_flags, 8, 1)
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_REG_DISCARD_AFC_TIMER_CHECK_SET(host_service_flags, val) \
|
||||
WMI_SET_BITS(host_service_flags, 8, 1, val)
|
||||
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_REG_DISCARD_AFC_REQ_ID_CHECK_GET(host_service_flags) \
|
||||
WMI_GET_BITS(host_service_flags, 9, 1)
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_REG_DISCARD_AFC_REQ_ID_CHECK_SET(host_service_flags, val) \
|
||||
WMI_SET_BITS(host_service_flags, 9, 1, val)
|
||||
|
||||
#define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
|
||||
WMI_GET_BITS(carrier_config, 0, 1)
|
||||
#define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_SET(carrier_config, val) \
|
||||
WMI_SET_BITS(carrier_config, 0, 1, val)
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param */
|
||||
|
||||
|
|
@ -5116,6 +5182,7 @@ typedef struct {
|
|||
* link flags: refer WMI_ROAM_LINK_FLAG_XXX.
|
||||
*/
|
||||
A_UINT32 flags;
|
||||
wmi_mac_addr link_addr; /* link address */
|
||||
} wmi_roam_ml_setup_links_param;
|
||||
|
||||
/*
|
||||
|
|
@ -10177,6 +10244,77 @@ typedef struct {
|
|||
#define WMI_CTRL_PATH_CALIBRATION_STATS_IS_PERIODIC_CAL_GET(cal_info) WMI_GET_BITS(cal_info, 13, 1)
|
||||
#define WMI_CTRL_PATH_CALIBRATION_STATS_IS_PERIODIC_CAL_SET(cal_info, is_periodic) WMI_SET_BITS(cal_info, 13, 1, is_periodic)
|
||||
|
||||
/* 0=20MHz, 1=40MHz, 2=80MHz, 3=160MHz, 4=240MHz, 5=320MHz */
|
||||
#define WMI_AWGN_MAX_BW 6
|
||||
|
||||
typedef struct {
|
||||
/* TLV tag and len; tag equals
|
||||
* WMITLV_TAG_STRUC_wmi_ctrl_path_awgn_stats_struct
|
||||
* For 6G FCC test we have to monitor channel interference and switch
|
||||
* to non-interference channel.
|
||||
* Additive White Gaussian Noise (AWGN) interference detection logic
|
||||
* is used to detect interference based upon CCA / BW drop / packet drop.
|
||||
* Once AWGN interference is detected, the target sends
|
||||
* WMI_DCS_INTERFERENCE_EVENTID to host for channel change/BW change.
|
||||
* This stats struct is used to get info about how many times these
|
||||
* CCA_Interference/BW_Drop/Pkt_Drop indicators of AWGN occur.
|
||||
*/
|
||||
A_UINT32 tlv_header;
|
||||
/*
|
||||
* AWGN WMI event sent count
|
||||
* This is used to inform how many WMI_DCS_INTERFERENCE_EVENTID have been
|
||||
* sent to the host.
|
||||
* WMI_DCS_INTERFERENCE_EVENTID is sent whenever one or more of
|
||||
* CCA_Int/BW_Drop/Channel_Change(Pkt_Drop) happen.
|
||||
*/
|
||||
A_UINT32 awgn_send_evt_cnt;
|
||||
/* AWGN primary int count */
|
||||
A_UINT32 awgn_pri_int_cnt;
|
||||
/* AWGN secondary int count */
|
||||
A_UINT32 awgn_sec_int_cnt;
|
||||
/*
|
||||
* AWGN pkt drop trigger count
|
||||
* This shows how many times the presence of interference on the
|
||||
* primary BW has been inferred due to pkt drops.
|
||||
* WMI_DCS_INTERFERENCE_EVENTID wil be sent whenever there is
|
||||
* interference on Primary Channel.
|
||||
*/
|
||||
A_UINT32 awgn_pkt_drop_trigger_cnt;
|
||||
/* awgn pkt drop trigger reset count */
|
||||
A_UINT32 awgn_pkt_drop_trigger_reset_cnt;
|
||||
/*
|
||||
* AWGN bandwidth drop count
|
||||
* This is used to inform count for any frame transmitted on lower BW
|
||||
* than configured BW.
|
||||
* WMI_DCS_INTERFERENCE_EVENTID wil be sent whenever there is BW drop.
|
||||
*/
|
||||
A_UINT32 awgn_bw_drop_cnt;
|
||||
/* AWGN bandwidth drop reset count */
|
||||
A_UINT32 awgn_bw_drop_reset_cnt;
|
||||
/*
|
||||
* AWGN CCA int count
|
||||
* This is used to inform the interference based on CCA registers.
|
||||
* WMI_DCS_INTERFERENCE_EVENTID wil be sent whenever there is CCA
|
||||
* interference.
|
||||
*/
|
||||
A_UINT32 awgn_cca_int_cnt;
|
||||
/* AWGN cca int reset count */
|
||||
A_UINT32 awgn_cca_int_reset_cnt;
|
||||
/* AWGN cca ack blk count */
|
||||
A_UINT32 awgn_cca_ack_blk_cnt;
|
||||
/* AWGN cca ack blk reset count */
|
||||
A_UINT32 awgn_cca_ack_reset_cnt;
|
||||
/*
|
||||
* AWGN int BW cnt used to store interference occured at 20/40/80/160MHz
|
||||
* bw_cnt[0] counts interference detections in 20 MHz BW,
|
||||
* bw_cnt[1] counts interference detections in 40 MHz BW,
|
||||
* bw_cnt[2] counts interference detections in 80 MHz BW,
|
||||
* bw_cnt[3] counts interference detections in 160 MHz BW,
|
||||
* bw_cnt[4] and bw_cnt[6] are reserved for 240 MHz and 320 MHz.
|
||||
*/
|
||||
A_UINT32 awgn_int_bw_cnt[WMI_AWGN_MAX_BW];
|
||||
} wmi_ctrl_path_awgn_stats_struct;
|
||||
|
||||
typedef struct {
|
||||
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_dfs_channel_stats_struct*/
|
||||
A_UINT32 tlv_header;
|
||||
|
|
@ -14608,34 +14746,45 @@ typedef struct {
|
|||
* IMPORTANT: Make sure the bit definitions here are consistent
|
||||
* with the ni_flags definitions in wlan_peer.h
|
||||
*/
|
||||
#define WMI_PEER_AUTH 0x00000001 /* Authorized for data */
|
||||
#define WMI_PEER_QOS 0x00000002 /* QoS enabled */
|
||||
#define WMI_PEER_NEED_PTK_4_WAY 0x00000004 /* Needs PTK 4 way handshake for authorization */
|
||||
#define WMI_PEER_NEED_GTK_2_WAY 0x00000010 /* Needs GTK 2 way handshake after 4-way handshake */
|
||||
#define WMI_PEER_HE 0x00000400 /* HE Enabled */
|
||||
#define WMI_PEER_APSD 0x00000800 /* U-APSD power save enabled */
|
||||
#define WMI_PEER_HT 0x00001000 /* HT enabled */
|
||||
#define WMI_PEER_40MHZ 0x00002000 /* 40MHz enabld */
|
||||
#define WMI_PEER_INTER_BSS_PEER 0x00004000 /* Inter BSS peer */
|
||||
#define WMI_PEER_STBC 0x00008000 /* STBC Enabled */
|
||||
#define WMI_PEER_LDPC 0x00010000 /* LDPC ENabled */
|
||||
#define WMI_PEER_DYN_MIMOPS 0x00020000 /* Dynamic MIMO PS Enabled */
|
||||
#define WMI_PEER_STATIC_MIMOPS 0x00040000 /* Static MIMO PS enabled */
|
||||
#define WMI_PEER_SPATIAL_MUX 0x00200000 /* SM Enabled */
|
||||
#define WMI_PEER_TWT_REQ 0x00400000 /* TWT Requester Support bit in Extended Capabilities element */
|
||||
#define WMI_PEER_TWT_RESP 0x00800000 /* TWT Responder Support bit in Extended Capabilities element */
|
||||
#define WMI_PEER_MULTI_BSSID 0x01000000 /* Multiple BSSID Support bit in Extended Capabilities element */
|
||||
#define WMI_PEER_VHT 0x02000000 /* VHT Enabled */
|
||||
#define WMI_PEER_80MHZ 0x04000000 /* 80MHz enabld */
|
||||
#define WMI_PEER_PMF 0x08000000 /* Robust Management Frame Protection enabled */
|
||||
/** CAUTION TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000. Need to be clean up */
|
||||
#define WMI_PEER_IS_P2P_CAPABLE 0x20000000 /* P2P capable peer */
|
||||
#define WMI_PEER_160MHZ 0x40000000 /* 160 MHz enabled */
|
||||
#define WMI_PEER_SAFEMODE_EN 0x80000000 /* Fips Mode Enabled */
|
||||
#define WMI_PEER_AUTH 0x00000001 /* Authorized for data */
|
||||
#define WMI_PEER_QOS 0x00000002 /* QoS enabled */
|
||||
#define WMI_PEER_NEED_PTK_4_WAY 0x00000004 /* Needs PTK 4 way handshake for authorization */
|
||||
#define WMI_PEER_GK_INST 0x00000008 /* group Key Installed */
|
||||
#define WMI_PEER_NEED_GTK_2_WAY 0x00000010 /* Needs GTK 2 way handshake after 4-way handshake */
|
||||
#define WMI_PEER_PRIV 0x00000020 /* Encryption Enabled */
|
||||
#define WMI_PEER_PK_INST 0x00000040 /* Pairwise Key Installed */
|
||||
#define WMI_PEER_TKIP_CM_ENABLED 0x00000080 /* TKIP CounterMeasures */
|
||||
#define WMI_PEER_SW_DEMIC_FRAG 0x00000100 /* S/W Demic of Frag Train */
|
||||
#define WMI_PEER_CCX_ENABLED 0x00000200 /* CCX enabled */
|
||||
#define WMI_PEER_HE 0x00000400 /* HE Enabled */
|
||||
#define WMI_PEER_APSD 0x00000800 /* U-APSD power save enabled */
|
||||
#define WMI_PEER_HT 0x00001000 /* HT enabled */
|
||||
#define WMI_PEER_40MHZ 0x00002000 /* 40MHz enabld */
|
||||
#define WMI_PEER_INTER_BSS_PEER 0x00004000 /* Inter BSS peer */
|
||||
#define WMI_PEER_STBC 0x00008000 /* STBC Enabled */
|
||||
#define WMI_PEER_LDPC 0x00010000 /* LDPC ENabled */
|
||||
#define WMI_PEER_DYN_MIMOPS 0x00020000 /* Dynamic MIMO PS Enabled */
|
||||
#define WMI_PEER_STATIC_MIMOPS 0x00040000 /* Static MIMO PS enabled */
|
||||
#define WMI_PEER_DIS_MIMOPS 0x00080000 /* MIMO PS DISABLED */
|
||||
#define WMI_PEER_SPATIAL_EXP 0x00100000 /* Enable spatial expansion for
|
||||
* single stream rates to avoid
|
||||
* unintentional beamforming */
|
||||
#define WMI_PEER_SPATIAL_MUX 0x00200000 /* SM Enabled */
|
||||
#define WMI_PEER_TWT_REQ 0x00400000 /* TWT Requester Support bit in Extended Capabilities element */
|
||||
#define WMI_PEER_TWT_RESP 0x00800000 /* TWT Responder Support bit in Extended Capabilities element */
|
||||
#define WMI_PEER_MULTI_BSSID 0x01000000 /* Multiple BSSID Support bit in Extended Capabilities element */
|
||||
#define WMI_PEER_VHT 0x02000000 /* VHT Enabled */
|
||||
#define WMI_PEER_80MHZ 0x04000000 /* 80MHz enabld */
|
||||
#define WMI_PEER_PMF 0x08000000 /* Robust Management Frame Protection enabled */
|
||||
#define WMI_PEER_F_PS_PRESEND_REQUIRED 0x10000000 /* Use this flag to avoid calling powersave API when STA is awake */
|
||||
#define WMI_PEER_IS_P2P_CAPABLE 0x20000000 /* P2P capable peer */
|
||||
#define WMI_PEER_160MHZ 0x40000000 /* 160 MHz enabled */
|
||||
#define WMI_PEER_SAFEMODE_EN 0x80000000 /* Fips Mode Enabled */
|
||||
|
||||
/** define for peer_flags_ext */
|
||||
#define WMI_PEER_EXT_EHT 0x00000001 /* EHT enabled */
|
||||
#define WMI_PEER_EXT_320MHZ 0x00000002 /* 320Mhz enabled */
|
||||
#define WMI_PEER_EXT_EHT 0x00000001 /* EHT enabled */
|
||||
#define WMI_PEER_EXT_320MHZ 0x00000002 /* 320Mhz enabled */
|
||||
#define WMI_PEER_EXT_F_CRIT_PROTO_HINT_ENABLED 0x40000000
|
||||
|
||||
/**
|
||||
* Peer rate capabilities.
|
||||
|
|
@ -27396,6 +27545,7 @@ typedef enum {
|
|||
WMI_REQUEST_CTRL_PATH_TWT_STAT = 4,
|
||||
WMI_REQUEST_CTRL_PATH_CALIBRATION_STAT = 5,
|
||||
WMI_REQUEST_CTRL_PATH_DFS_CHANNEL_STAT = 6,
|
||||
WMI_REQUEST_CTRL_PATH_AWGN_STAT = 7,
|
||||
} wmi_ctrl_path_stats_id;
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -30537,6 +30687,18 @@ typedef enum _WMI_TWT_COMMAND_T {
|
|||
#define TWT_FLAGS_GET_TWT_INFO_FRAME_DISABLED(flag) WMI_GET_BITS(flag, 13, 1)
|
||||
#define TWT_FLAGS_SET_TWT_INFO_FRAME_DISABLED(flag, val) WMI_SET_BITS(flag, 13, 1, val)
|
||||
|
||||
/*
|
||||
* 1 means PM_RESPONDER_MODE information sent in BIT15 is valid, 0 means it is not valid.
|
||||
* Will be used for backward compatibility if host uses older FW versions
|
||||
* then value will be 0 so host will not consider the BIT15 value.
|
||||
*/
|
||||
#define TWT_FLAGS_GET_PM_RESPONDER_MODE_VALID(flag) WMI_GET_BITS(flag, 14, 1)
|
||||
#define TWT_FLAGS_SET_PM_RESPONDER_MODE_VALID(flag, val) WMI_SET_BITS(flag, 14, 1, val)
|
||||
|
||||
/* 1 means PM_RESPONDER_MODE supported, 0 means not supported */
|
||||
#define TWT_FLAGS_GET_PM_RESPONDER_MODE(flag) WMI_GET_BITS(flag, 15, 1)
|
||||
#define TWT_FLAGS_SET_PM_RESPONDER_MODE(flag, val) WMI_SET_BITS(flag, 15, 1, val)
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_ack_event_fixed_param */
|
||||
A_UINT32 vdev_id; /* VDEV identifier */
|
||||
|
|
@ -35351,6 +35513,12 @@ typedef struct {
|
|||
#define WMI_TWT_SESSION_FLAG_TWT_INFO_FRAME_DISABLED_GET(_var) WMI_GET_BITS(_var, 20, 1)
|
||||
#define WMI_TWT_SESSION_FLAG_TWT_INFO_FRAME_DISABLED_SET(_var, _val) WMI_SET_BITS(_var, 20, 1, _val)
|
||||
|
||||
#define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_VALID_GET(_var) WMI_GET_BITS(_var, 21, 1)
|
||||
#define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_VALID_SET(_var, _val) WMI_SET_BITS(_var, 21, 1, _val)
|
||||
|
||||
#define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_GET(_var) WMI_GET_BITS(_var, 22, 1)
|
||||
#define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_SET(_var, _val) WMI_SET_BITS(_var, 22, 1, _val)
|
||||
|
||||
typedef struct {
|
||||
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_session_stats_info */
|
||||
A_UINT32 tlv_hdr;
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
#define __WMI_VER_MINOR_ 0
|
||||
/** WMI revision number has to be incremented when there is a
|
||||
* change that may or may not break compatibility. */
|
||||
#define __WMI_REVISION_ 1043
|
||||
#define __WMI_REVISION_ 1050
|
||||
|
||||
/** The Version Namespace should not be normally changed. Only
|
||||
* host and firmware of the same WMI namespace will work
|
||||
|
|
|
|||
Loading…
Reference in a new issue