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Merge ../linux-2.6

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This commit is contained in:
Mauro Carvalho Chehab 2008-07-27 22:23:18 -03:00
commit c2f90e9536
81 changed files with 787 additions and 945 deletions
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48
include/asm-arm/arch-pnx4008/irqs.h
View file

@ -135,30 +135,30 @@
#define PNX4008_IRQ_TYPES \
{ /*IRQ #'s: */ \
IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \
IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \
IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \
IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \
IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \
}
/* Start Enable Pin Interrupts - table 58 page 66 */

10
include/asm-arm/arch-pxa/idp.h
View file

@ -138,18 +138,18 @@
#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
#define IDE_IRQ IRQ_GPIO(21)
#define TOUCH_PANEL_IRQ_EDGE IRQT_FALLING
#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
#define ETHERNET_IRQ IRQ_GPIO(4)
#define ETHERNET_IRQ_EDGE IRQT_RISING
#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define IDE_IRQ_EDGE IRQT_RISING
#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
#define PCMCIA_S0_CD_VALID_EDGE IRQT_BOTHEDGE
#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
#define PCMCIA_S1_CD_VALID_EDGE IRQT_BOTHEDGE
#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
#define PCMCIA_S1_RDYINT IRQ_GPIO(22)

14
include/asm-arm/arch-pxa/pcm990_baseboard.h
View file

@ -29,14 +29,14 @@
/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
#define PCM990_CTRL_INT_IRQ_GPIO 9
#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING
#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
#define PCM990_CTRL_BASE 0xea000000
#define PCM990_CTRL_SIZE (1*1024*1024)
#define PCM990_CTRL_PWR_IRQ_GPIO 14
#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING
#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING
/* visible CPLD (U7) registers */
#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
@ -133,7 +133,7 @@
*/
#define PCM990_IDE_IRQ_GPIO 13
#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
#define PCM990_IDE_IRQ_EDGE IRQT_RISING
#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
#define PCM990_IDE_PLD_BASE 0xee000000
#define PCM990_IDE_PLD_SIZE (1*1024*1024)
@ -189,11 +189,11 @@
*/
#define PCM990_CF_IRQ_GPIO 11
#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
#define PCM990_CF_IRQ_EDGE IRQT_RISING
#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CF_CD_GPIO 12
#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
#define PCM990_CF_CD_EDGE IRQT_RISING
#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING
#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
#define PCM990_CF_PLD_BASE 0xef000000
@ -259,14 +259,14 @@
*/
#define PCM990_AC97_IRQ_GPIO 10
#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
#define PCM990_AC97_IRQ_EDGE IRQT_RISING
#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING
/*
* MMC phyCORE
*/
#define PCM990_MMC0_IRQ_GPIO 9
#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING
#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
/*
* USB phyCore

2
include/asm-arm/arch-pxa/pxa25x-udc.h
View file

@ -2,7 +2,7 @@
#define _ASM_ARCH_PXA25X_UDC_H
#ifdef _ASM_ARCH_PXA27X_UDC_H
#error You can't include both PXA25x and PXA27x UDC support
#error "You can't include both PXA25x and PXA27x UDC support"
#endif
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */

2
include/asm-arm/arch-sa1100/ide.h
View file

@ -61,7 +61,7 @@ ide_init_default_hwifs(void)
/* Enable GPIO as interrupt line */
GPDR &= ~LART_GPIO_IDE;
set_irq_type(LART_IRQ_IDE, IRQT_RISING);
set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING);
/* set PCMCIA interface timing */
MECR = 0x00060006;

9
include/asm-arm/bitops.h
View file

@ -277,9 +277,16 @@ static inline int constant_fls(int x)
* the clz instruction for much better code efficiency.
*/
#define fls(x) \
#define __fls(x) \
( __builtin_constant_p(x) ? constant_fls(x) : \
({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
/* Implement fls() in C so that 64-bit args are suitably truncated */
static inline int fls(int x)
{
return __fls(x);
}
#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
#define __ffs(x) (ffs(x) - 1)
#define ffz(x) __ffs( ~(x) )

17
include/asm-arm/cacheflush.h
View file

@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
/*
* VIVT caches only
*/
#define cache_is_vivt() 1
#define cache_is_vipt() 0
#define cache_is_vipt_nonaliasing() 0
#define cache_is_vipt_aliasing() 0
#define icache_is_vivt_asid_tagged() 0
#elif defined(CONFIG_CPU_CACHE_VIPT)
#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
/*
* VIPT caches only
*/
#define cache_is_vivt() 0
#define cache_is_vipt() 1
#define cache_is_vipt_nonaliasing() \
@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
})
#else
/*
* VIVT or VIPT caches. Note that this is unreliable since ARM926
* and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
* There's no way to tell from the CacheType register what type (!)
* the cache is.
*/
#define cache_is_vivt() \
({ \
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \

17
include/asm-arm/irq.h
View file

@ -19,23 +19,6 @@
#define NO_IRQ ((unsigned int)(-1))
#endif
/*
* Migration helpers
*/
#define __IRQT_FALEDGE IRQ_TYPE_EDGE_FALLING
#define __IRQT_RISEDGE IRQ_TYPE_EDGE_RISING
#define __IRQT_LOWLVL IRQ_TYPE_LEVEL_LOW
#define __IRQT_HIGHLVL IRQ_TYPE_LEVEL_HIGH
#define IRQT_NOEDGE (0)
#define IRQT_RISING (__IRQT_RISEDGE)
#define IRQT_FALLING (__IRQT_FALEDGE)
#define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE)
#define IRQT_LOW (__IRQT_LOWLVL)
#define IRQT_HIGH (__IRQT_HIGHLVL)
#define IRQT_PROBE IRQ_TYPE_PROBE
#ifndef __ASSEMBLY__
struct irqaction;
extern void migrate_irqs(void);

8
include/asm-arm/pci.h
View file

@ -78,6 +78,14 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res)
return root;
}
/*
* Dummy implementation; always return 0.
*/
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
return 0;
}
#endif /* __KERNEL__ */
#endif

12
include/linux/sched.h
View file

@ -505,7 +505,7 @@ struct signal_struct {
unsigned long nvcsw, nivcsw, cnvcsw, cnivcsw;
unsigned long min_flt, maj_flt, cmin_flt, cmaj_flt;
unsigned long inblock, oublock, cinblock, coublock;
struct proc_io_accounting ioac;
struct task_io_accounting ioac;
/*
* Cumulative ns of scheduled CPU time for dead threads in the
@ -1253,7 +1253,7 @@ struct task_struct {
unsigned long ptrace_message;
siginfo_t *last_siginfo; /* For ptrace use. */
struct proc_io_accounting ioac;
struct task_io_accounting ioac;
#if defined(CONFIG_TASK_XACCT)
u64 acct_rss_mem1; /* accumulated rss usage */
u64 acct_vm_mem1; /* accumulated virtual memory usage */
@ -2183,22 +2183,22 @@ extern long sched_group_rt_period(struct task_group *tg);
#ifdef CONFIG_TASK_XACCT
static inline void add_rchar(struct task_struct *tsk, ssize_t amt)
{
tsk->ioac.chr.rchar += amt;
tsk->ioac.rchar += amt;
}
static inline void add_wchar(struct task_struct *tsk, ssize_t amt)
{
tsk->ioac.chr.wchar += amt;
tsk->ioac.wchar += amt;
}
static inline void inc_syscr(struct task_struct *tsk)
{
tsk->ioac.chr.syscr++;
tsk->ioac.syscr++;
}
static inline void inc_syscw(struct task_struct *tsk)
{
tsk->ioac.chr.syscw++;
tsk->ioac.syscw++;
}
#else
static inline void add_rchar(struct task_struct *tsk, ssize_t amt)

17
include/linux/task_io_accounting.h
View file

@ -1,5 +1,5 @@
/*
* proc_io_accounting: a structure which is used for recording a single task's
* task_io_accounting: a structure which is used for recording a single task's
* IO statistics.
*
* Don't include this header file directly - it is designed to be dragged in via
@ -8,8 +8,8 @@
* Blame akpm@osdl.org for all this.
*/
struct task_io_accounting {
#ifdef CONFIG_TASK_XACCT
struct task_chr_io_accounting {
/* bytes read */
u64 rchar;
/* bytes written */
@ -18,14 +18,9 @@ struct task_chr_io_accounting {
u64 syscr;
/* # of write syscalls */
u64 syscw;
};
#else /* CONFIG_TASK_XACCT */
struct task_chr_io_accounting {
};
#endif /* CONFIG_TASK_XACCT */
#ifdef CONFIG_TASK_IO_ACCOUNTING
struct task_io_accounting {
/*
* The number of bytes which this task has caused to be read from
* storage.
@ -46,13 +41,5 @@ struct task_io_accounting {
* information loss in doing that.
*/
u64 cancelled_write_bytes;
};
#else /* CONFIG_TASK_IO_ACCOUNTING */
struct task_io_accounting {
};
#endif /* CONFIG_TASK_IO_ACCOUNTING */
struct proc_io_accounting {
struct task_chr_io_accounting chr;
struct task_io_accounting blk;
};

48
include/linux/task_io_accounting_ops.h
View file

@ -9,7 +9,7 @@
#ifdef CONFIG_TASK_IO_ACCOUNTING
static inline void task_io_account_read(size_t bytes)
{
current->ioac.blk.read_bytes += bytes;
current->ioac.read_bytes += bytes;
}
/*
@ -18,12 +18,12 @@ static inline void task_io_account_read(size_t bytes)
*/
static inline unsigned long task_io_get_inblock(const struct task_struct *p)
{
return p->ioac.blk.read_bytes >> 9;
return p->ioac.read_bytes >> 9;
}
static inline void task_io_account_write(size_t bytes)
{
current->ioac.blk.write_bytes += bytes;
current->ioac.write_bytes += bytes;
}
/*
@ -32,25 +32,25 @@ static inline void task_io_account_write(size_t bytes)
*/
static inline unsigned long task_io_get_oublock(const struct task_struct *p)
{
return p->ioac.blk.write_bytes >> 9;
return p->ioac.write_bytes >> 9;
}
static inline void task_io_account_cancelled_write(size_t bytes)
{
current->ioac.blk.cancelled_write_bytes += bytes;
current->ioac.cancelled_write_bytes += bytes;
}
static inline void task_io_accounting_init(struct proc_io_accounting *ioac)
static inline void task_io_accounting_init(struct task_io_accounting *ioac)
{
memset(ioac, 0, sizeof(*ioac));
}
static inline void task_blk_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_blk_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
dst->blk.read_bytes += src->blk.read_bytes;
dst->blk.write_bytes += src->blk.write_bytes;
dst->blk.cancelled_write_bytes += src->blk.cancelled_write_bytes;
dst->read_bytes += src->read_bytes;
dst->write_bytes += src->write_bytes;
dst->cancelled_write_bytes += src->cancelled_write_bytes;
}
#else
@ -77,35 +77,35 @@ static inline void task_io_account_cancelled_write(size_t bytes)
{
}
static inline void task_io_accounting_init(struct proc_io_accounting *ioac)
static inline void task_io_accounting_init(struct task_io_accounting *ioac)
{
}
static inline void task_blk_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_blk_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
}
#endif /* CONFIG_TASK_IO_ACCOUNTING */
#ifdef CONFIG_TASK_XACCT
static inline void task_chr_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_chr_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
dst->chr.rchar += src->chr.rchar;
dst->chr.wchar += src->chr.wchar;
dst->chr.syscr += src->chr.syscr;
dst->chr.syscw += src->chr.syscw;
dst->rchar += src->rchar;
dst->wchar += src->wchar;
dst->syscr += src->syscr;
dst->syscw += src->syscw;
}
#else
static inline void task_chr_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_chr_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
}
#endif /* CONFIG_TASK_XACCT */
static inline void task_io_accounting_add(struct proc_io_accounting *dst,
struct proc_io_accounting *src)
static inline void task_io_accounting_add(struct task_io_accounting *dst,
struct task_io_accounting *src)
{
task_chr_io_accounting_add(dst, src);
task_blk_io_accounting_add(dst, src);