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ARM: dts: msm: Enable IPA node for monaco target

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Changes to enable the IPA node for monaco target.

Change-Id: I7597e73404b4e404da866a8464f92d230ee08eef
This commit is contained in:
Praveen Kurapati 2021-05-21 05:57:22 +05:30
commit c2fd643c61
1 changed files with 125 additions and 0 deletions
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125
qcom/monaco.dtsi
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@ -1219,6 +1219,18 @@
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-adsp {
@ -1473,6 +1485,119 @@
qcom,firmware-name = "venus";
memory-region = <&pil_video_mem>;
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
qcom,ipa-platform-type-msm;
qcom,ipa-advertise-sg-support;
qcom,ipa-napi-enable;
};
qcom,ipa_fws {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <0xf>;
qcom,firmware-name = "ipa_fws";
qcom,pil-force-shutdown;
memory-region = <&pil_ipa_fw_mem>;
};
ipa_hw: qcom,ipa@0x5800000 {
compatible = "qcom,ipa";
reg = <0x5800000 0x34000>,
<0x5804000 0x28000>;
reg-names = "ipa-base", "gsi-base";
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "gsi-irq";
qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
qcom,ipa-hw-mode = <0>;
qcom,platform-type = <1>; /* MSM platform */
qcom,ee = <0>;
qcom,use-ipa-tethering-bridge;
qcom,modem-cfg-emb-pipe-flt;
qcom,ipa-wdi2;
qcom,ipa-wdi2_over_gsi;
qcom,ipa-endp-delay-wa;
qcom,use-ipa-pm;
qcom,arm-smmu;
qcom,ipa-fltrt-not-hashable;
qcom,skip-ieob-mask-wa;
qcom,msm-bus,name = "ipa";
qcom,max_num_smmu_cb = <3>;
clocks = <&rpmcc RPM_SMD_IPA_CLK>;
clock-names = "core_clk";
qcom,interconnect,num-cases = <5>;
qcom,interconnect,num-paths = <3>;
interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI_CH0>,
<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>;
interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa";
/* No vote */
qcom,no-vote =
<0 0 0 0 0 0>;
/* SVS2 */
qcom,svs2 =
<80000 2720000 80000 560000 80000 120000>;
/* SVS */
qcom,svs =
<80000 5414000 80000 920000 80000 180000>;
/* NOMINAL */
qcom,nominal =
<206000 7200000 206000 1560000 206000 380000>;
/* TURBO */
qcom,turbo =
<206000 8500000 206000 1880000 206000 520000>;
qcom,bus-vector-names =
"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
qcom,throughput-threshold = <310 600 1000>;
qcom,scaling-exceptions = <>;
/* smp2p information */
qcom,smp2p_map_ipa_1_out {
compatible = "qcom,smp2p-map-ipa-1-out";
qcom,smem-states = <&smp2p_ipa_1_out 0>;
qcom,smem-state-names = "ipa-smp2p-out";
};
qcom,smp2p_map_ipa_1_in {
compatible = "qcom,smp2p-map-ipa-1-in";
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
interrupt-names = "ipa-smp2p-in";
};
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&apps_smmu 0x0140 0x0>;
qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
/* modem tables in IMEM */
qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-geometry = <0 0xB0000000>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&apps_smmu 0x141 0x0>;
/* ipa-uc ram */
qcom,iommu-dma = "atomic";
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
iommus = <&apps_smmu 0x0142 0x0>;
qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
qcom,iommu-dma = "atomic";
};
};
};
#include "pm5100.dtsi"