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ARM: dts: msm: Update cnss device tree node for interconnect paths

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Configure bandwidth vote data for individual platform interconnect paths.

Change-Id: I875bad28fc271a318bf38c794f1599d55b1af330
This commit is contained in:
Manikandan Mohan 2020-08-13 23:06:32 -07:00
commit c33bdf4e3f
2 changed files with 31 additions and 13 deletions
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4
bindings/cnss/cnss-wlan.txt
View file

@ -71,7 +71,9 @@ Optional properties:
specifications, should be drived depending on products
- qcom,wlan-cbc-enabled: boolean property to control cold boot calibration
- interconnects: Interconnect framework setup for bus configuration
- qcom,bus-bw-cfg-num: Number of bus bandwidth voting cases
- interconnect-names: Interconnect path names as strings
- qcom,icc-path-count: Number of Interconnect paths for this platform
- qcom,bus-bw-cfg-count: Number of bus bandwidth voting cases
- qcom,bus-bw-cfg: Bus bandwidth voting data
- qcom,tcs_offset_int_pow_amp_vreg: TCS CMD register offset for Voltage
regulator used in internal power amplifier for QCA6490

40
qcom/lahaina.dtsi
View file

@ -5295,22 +5295,38 @@
wlan-ant-switch-supply = <&L7E>;
qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
qcom,bus-bw-cfg-num = <7>;
interconnects =
<&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <7>;
qcom,bus-bw-cfg =
/* no vote */
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<2250 390000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<7500 390000>,
/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<30000 790000>,
/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<100000 790000>,
/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
<175000 1600000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
* ddr: 547.2 MHz
*/
<7500 390000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr freq: 451.2 MHz */
<2250 1600000>,
/* low: 18-60 Mbps ddr freq: 451.2 MHz */
<7500 1600000>,
/* medium: 60-240 Mbps ddr freq: 451.2 MHz */
<2250 1804800>,
<7500 1804800>,
<30000 1804800>,
/* high: 240 - 1080 Mbps ddr freq: 451.2 MHz */
<100000 1804800>,
/* high: 1080 - 1400 Mbps ddr freq: 451.2 MHz */
<175000 1804800>,
/* low (latency critical): 18 - 60 Mbps, ddr freq: 547.2 MHz */
<175000 6220800>,
<7500 2188800>;
mhi,max-channels = <30>;