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Revert "disp: msm: dsi: Support uncompressed rgb101010 format"

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This commit caused Rhode5G+ display issue

This reverts commit c56edb2f47.

Change-Id: I5779fb1b92ac00c386c286760bf5dc38a8157ac5
Reviewed-on: https://gerrit.mot.com/2189888
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Reviewed-by: Dezhen Hou <houdz1@motorola.com>
Tested-by: Jira Key
Submit-Approved: Liyun Zhang <zhangly19@lenovo.com>
This commit is contained in:
zhangly19 2022-02-14 15:18:57 +08:00 • committed by tongkun1
commit c36f5439e8
4 changed files with 7 additions and 17 deletions
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3
msm/dsi/dsi_ctrl.c
View file

@ -931,9 +931,6 @@ int dsi_ctrl_pixel_format_to_bpp(enum dsi_pixel_format dst_format)
case DSI_PIXEL_FORMAT_RGB888:
bpp = 24;
break;
case DSI_PIXEL_FORMAT_RGB101010:
bpp = 30;
break;
default:
bpp = 24;
break;

13
msm/dsi/dsi_ctrl_hw_cmn.c
View file

@ -42,9 +42,9 @@ static bool dsi_compression_enabled(struct dsi_mode_info *mode)
/* Unsupported formats default to RGB888 */
static const u8 cmd_mode_format_map[DSI_PIXEL_FORMAT_MAX] = {
0x6, 0x7, 0x8, 0x8, 0x0, 0x3, 0x4, 0x9 };
0x6, 0x7, 0x8, 0x8, 0x0, 0x3, 0x4 };
static const u8 video_mode_format_map[DSI_PIXEL_FORMAT_MAX] = {
0x0, 0x1, 0x2, 0x3, 0x3, 0x3, 0x3, 0x4 };
0x0, 0x1, 0x2, 0x3, 0x3, 0x3, 0x3 };
/**
* dsi_split_link_setup() - setup dsi split link configurations
@ -431,13 +431,10 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
u32 reg = 0, offset = 0;
int pic_width = 0, this_frame_slices = 0, intf_ip_w = 0;
u32 pkt_per_line = 0, eol_byte_num = 0, bytes_in_slice = 0;
u32 bpp;
if (roi && (!roi->w || !roi->h))
return;
bpp = dsi_pixel_format_to_bpp(cfg->dst_format);
if (dsi_dsc_compression_enabled(mode)) {
struct msm_display_dsc_info dsc;
@ -471,11 +468,11 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
bytes_in_slice = vdc.bytes_in_slice;
} else if (roi) {
width_final = roi->w;
stride_final = DIV_ROUND_UP(roi->w * bpp, 8);
stride_final = roi->w * 3;
height_final = roi->h;
} else {
width_final = mode->h_active;
stride_final = DIV_ROUND_UP(mode->h_active * bpp, 8);
stride_final = mode->h_active * 3;
height_final = mode->v_active;
}
@ -592,7 +589,7 @@ void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl,
reg |= (cfg->bllp_lp11_en ? BIT(12) : 0);
reg |= (cfg->traffic_mode & 0x3) << 8;
reg |= (cfg->vc_id & 0x3);
reg |= (video_mode_format_map[common_cfg->dst_format] & 0x7) << 4;
reg |= (video_mode_format_map[common_cfg->dst_format] & 0x3) << 4;
DSI_W32(ctrl, DSI_VIDEO_MODE_CTRL, reg);
reg = (common_cfg->swap_mode & 0x7) << 12;

4
msm/dsi/dsi_defs.h
View file

@ -39,7 +39,6 @@
* @DSI_PIXEL_FORMAT_RGB111:
* @DSI_PIXEL_FORMAT_RGB332:
* @DSI_PIXEL_FORMAT_RGB444:
* @DSI_PIXEL_FORMAT_RGB101010:
* @DSI_PIXEL_FORMAT_MAX:
*/
enum dsi_pixel_format {
@ -50,7 +49,6 @@ enum dsi_pixel_format {
DSI_PIXEL_FORMAT_RGB111,
DSI_PIXEL_FORMAT_RGB332,
DSI_PIXEL_FORMAT_RGB444,
DSI_PIXEL_FORMAT_RGB101010,
DSI_PIXEL_FORMAT_MAX
};
@ -783,8 +781,6 @@ static inline int dsi_pixel_format_to_bpp(enum dsi_pixel_format fmt)
return 8;
case DSI_PIXEL_FORMAT_RGB444:
return 12;
case DSI_PIXEL_FORMAT_RGB101010:
return 30;
}
return 24;
}

4
msm/dsi/dsi_phy_timing_calc.c
View file

@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*/
#include "dsi_phy_timing_calc.h"
static const u32 bits_per_pixel[DSI_PIXEL_FORMAT_MAX] = {
16, 18, 18, 24, 3, 8, 12, 30 };
16, 18, 18, 24, 3, 8, 12 };
static int dsi_phy_cmn_validate_and_set(struct timing_entry *t,
char const *t_name)