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ARM: dts: msm: Add I2C NFC device node for shima

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Device node changes required on shima describing
the GPIO configuration for Nfc controller chip.

Modified corresponding Nfc device node
for IDP & QRD platforms.

Change-Id: I122dc7b27204705309f6e0e667cda3410703a09d
This commit is contained in:
Bhuvan Varshney 2020-08-18 16:56:02 +05:30 • committed by Gerrit - the friendly Code Review server
commit c370aad7c7
3 changed files with 102 additions and 0 deletions
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21
qcom/shima-idp.dtsi
View file

@ -25,6 +25,27 @@
};
};
&qupv3_se9_i2c {
status = "ok"
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 87 0x00>;
qcom,sn-ven = <&tlmm 62 0x00>;
qcom,sn-firm = <&tlmm 86 0x00>;
qcom,sn-clkreq = <&tlmm 63 0x00>;
interrupt-parent = <&tlmm>;
interrupts = <87 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&sdhc_1 {
status = "ok"

60
qcom/shima-pinctrl.dtsi
View file

@ -151,6 +151,66 @@
};
};
nfc {
nfc_int_active: nfc_int_active {
/* active state */
mux {
/* GPIO 87: NFC Read Interrupt */
pins = "gpio87";
function = "gpio";
};
config {
pins = "gpio87";
drive-strength = <2>; /* 2 MA */
bias-pull-down;
};
};
nfc_int_suspend: nfc_int_suspend {
/* sleep state */
mux {
/* GPIO 87: NFC Read Interrupt */
pins = "gpio87";
function = "gpio";
};
config {
pins = "gpio87";
drive-strength = <2>; /* 2 MA */
bias-pull-down;
};
};
nfc_enable_active: nfc_enable_active {
mux {
/* 62: Enable,86: Firmware,63: CLOCK */
pins = "gpio62", "gpio86", "gpio63";
function = "gpio";
};
config {
pins = "gpio62", "gpio86", "gpio63";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
nfc_enable_suspend: nfc_enable_suspend {
mux {
/* 62: Enable,86: Firmware,63: CLOCK */
pins = "gpio62", "gpio86", "gpio63";
function = "gpio";
};
config {
pins = "gpio62", "gpio86", "gpio63";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
};
qupv3_se9_spi_pins: qupv3_se9_spi_pins {
qupv3_se9_spi_active: qupv3_se9_spi_active {
mux {

21
qcom/shima-qrd.dtsi
View file

@ -24,6 +24,27 @@
};
};
&qupv3_se9_i2c {
status = "ok"
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 87 0x00>;
qcom,sn-ven = <&tlmm 62 0x00>;
qcom,sn-firm = <&tlmm 86 0x00>;
qcom,sn-clkreq = <&tlmm 63 0x00>;
interrupt-parent = <&tlmm>;
interrupts = <87 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&sdhc_1 {
status = "ok"