From cd42f7bceff3846f0e23e6d79b095708e85be476 Mon Sep 17 00:00:00 2001
From: Elson Roy Serrao <eserrao@quicinc.com>
Date: Thu, 8 Oct 2020 15:48:37 -0700
Subject: [PATCH] ARM: dts: msm: Add QMP PHY dt entries on sdxlemur

Add hsphy and ssphy related dt nodes and the phy
init sequence on sdxlemur.

Change-Id: I89177fecd76f5a9ace051e118f304698e9d1e636
---
 qcom/sdxlemur-usb.dtsi | 154 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 154 insertions(+)

diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi
index d11cad741801..c80dc7e4b561 100644
--- a/qcom/sdxlemur-usb.dtsi
+++ b/qcom/sdxlemur-usb.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h>
+
 &soc {
 	usb: ssusb@a600000 {
 		compatible = "qcom,dwc-usb3-msm";
@@ -44,6 +46,7 @@
 			compatible = "snps,dwc3";
 			reg = <0x0a600000 0xcd00>;
 			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy>, <&usb_qmp_phy>;
 			linux,sysdev_is_parent;
 			snps,disable-clk-gating;
 			snps,has-lpm-erratum;
@@ -60,4 +63,155 @@
 	usb_nop_phy: usb_nop_phy {
 		compatible = "usb-nop-xceiv";
 	};
+
+	usb2_phy: hsphy@ff4000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0xff4000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&pmx65_l4>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		vdda18-supply = <&pmx65_l5>;
+		vdda33-supply = <&pmx65_l10>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+		clock-names = "ref_clk_src", "cfg_ahb_clk";
+
+		resets = <&gcc GCC_QUSB2PHY_BCR>;
+		reset-names = "phy_reset";
+		qcom,no-rext-present;
+	};
+
+	usb_qmp_phy: ssphy@ff6000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0xff6000 0x2000>,
+			<0xff628c 0x4>;
+		reg-names = "qmp_phy_base",
+			"pcs_clamp_enable_reg";
+
+		vdd-supply = <&pmx65_l4>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47900>;
+		core-supply = <&pmx65_l1>;
+		qcom,core-max-load-uA = <15000>;
+
+		clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_PHY_PIPE_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
+				"cfg_ahb_clk";
+
+		resets = <&gcc GCC_USB3_PHY_BCR>,
+			<&gcc GCC_USB3PHY_PHY_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+
+		qcom,qmp-phy-init-seq =
+		    /* <reg_offset, value, delay> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
+				USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
+				USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
+				USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04 0
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05 0
+				USB3_UNI_QSERDES_RX_GM_CAL 0x00 0
+				USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
+				USB3_UNI_PCS_RX_SIGDET_LVL 0xAA 0
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
+				USB3_UNI_PCS_CDR_RESET_TIME 0x0A 0
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
+				USB3_UNI_PCS_EQ_CONFIG1 0x4B 0
+				USB3_UNI_PCS_EQ_CONFIG5 0x10 0
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
+				0xffffffff 0xffffffff 0x00>;
+
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				 USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				 USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				 USB3_UNI_PCS_POWER_DOWN_CONTROL
+				 USB3_UNI_PCS_SW_RESET
+				 USB3_UNI_PCS_START_CONTROL>;
+
+
+	};
 };