mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 05:29:04 -04:00
Merge branch 'akpm' (patches from Andrew)
Merge fifth set of updates from Andrew Morton:
- A few things which were awaiting merges from linux-next:
- rtc
- ocfs2
- misc others
- Willy's "dax" feature: direct fs access to memory (mainly NV-DIMMs)
which isn't backed by pageframes.
* emailed patches from Andrew Morton <akpm@linux-foundation.org>: (37 commits)
rtc: add driver for DS1685 family of real time clocks
MAINTAINERS: add entry for Maxim PMICs on Samsung boards
lib/Kconfig: use bool instead of boolean
powerpc: drop _PAGE_FILE and pte_file()-related helpers
ocfs2: set append dio as a ro compat feature
ocfs2: wait for orphan recovery first once append O_DIRECT write crash
ocfs2: complete the rest request through buffer io
ocfs2: do not fallback to buffer I/O write if appending
ocfs2: allocate blocks in ocfs2_direct_IO_get_blocks
ocfs2: implement ocfs2_direct_IO_write
ocfs2: add orphan recovery types in ocfs2_recover_orphans
ocfs2: add functions to add and remove inode in orphan dir
ocfs2: prepare some interfaces used in append direct io
MAINTAINERS: fix spelling mistake & remove trailing WS
dax: does not work correctly with virtual aliasing caches
brd: rename XIP to DAX
ext4: add DAX functionality
dax: add dax_zero_page_range
ext2: get rid of most mentions of XIP in ext2
ext2: remove ext2_aops_xip
...
This commit is contained in:
Linus Torvalds
commit
c397f8fa43
72 changed files with 4491 additions and 946 deletions
|
|
@ -51,6 +51,7 @@ struct swap_info_struct;
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|||
struct seq_file;
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struct workqueue_struct;
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struct iov_iter;
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struct vm_fault;
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||||
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||||
extern void __init inode_init(void);
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||||
extern void __init inode_init_early(void);
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||||
|
|
@ -361,8 +362,6 @@ struct address_space_operations {
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|||
int (*releasepage) (struct page *, gfp_t);
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void (*freepage)(struct page *);
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||||
ssize_t (*direct_IO)(int, struct kiocb *, struct iov_iter *iter, loff_t offset);
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int (*get_xip_mem)(struct address_space *, pgoff_t, int,
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void **, unsigned long *);
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/*
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||||
* migrate the contents of a page to the specified target. If
|
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* migrate_mode is MIGRATE_ASYNC, it must not block.
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|
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@ -1677,6 +1676,11 @@ struct super_operations {
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#define S_IMA 1024 /* Inode has an associated IMA struct */
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#define S_AUTOMOUNT 2048 /* Automount/referral quasi-directory */
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#define S_NOSEC 4096 /* no suid or xattr security attributes */
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#ifdef CONFIG_FS_DAX
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#define S_DAX 8192 /* Direct Access, avoiding the page cache */
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#else
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#define S_DAX 0 /* Make all the DAX code disappear */
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#endif
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/*
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* Note that nosuid etc flags are inode-specific: setting some file-system
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@ -1714,6 +1718,7 @@ struct super_operations {
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#define IS_IMA(inode) ((inode)->i_flags & S_IMA)
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#define IS_AUTOMOUNT(inode) ((inode)->i_flags & S_AUTOMOUNT)
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#define IS_NOSEC(inode) ((inode)->i_flags & S_NOSEC)
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#define IS_DAX(inode) ((inode)->i_flags & S_DAX)
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#define IS_WHITEOUT(inode) (S_ISCHR(inode->i_mode) && \
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(inode)->i_rdev == WHITEOUT_DEV)
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@ -2581,19 +2586,13 @@ extern loff_t fixed_size_llseek(struct file *file, loff_t offset,
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extern int generic_file_open(struct inode * inode, struct file * filp);
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extern int nonseekable_open(struct inode * inode, struct file * filp);
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#ifdef CONFIG_FS_XIP
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extern ssize_t xip_file_read(struct file *filp, char __user *buf, size_t len,
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loff_t *ppos);
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extern int xip_file_mmap(struct file * file, struct vm_area_struct * vma);
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extern ssize_t xip_file_write(struct file *filp, const char __user *buf,
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size_t len, loff_t *ppos);
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extern int xip_truncate_page(struct address_space *mapping, loff_t from);
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#else
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static inline int xip_truncate_page(struct address_space *mapping, loff_t from)
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{
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return 0;
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}
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#endif
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ssize_t dax_do_io(int rw, struct kiocb *, struct inode *, struct iov_iter *,
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loff_t, get_block_t, dio_iodone_t, int flags);
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int dax_clear_blocks(struct inode *, sector_t block, long size);
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int dax_zero_page_range(struct inode *, loff_t from, unsigned len, get_block_t);
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int dax_truncate_page(struct inode *, loff_t from, get_block_t);
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int dax_fault(struct vm_area_struct *, struct vm_fault *, get_block_t);
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#define dax_mkwrite(vma, vmf, gb) dax_fault(vma, vmf, gb)
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#ifdef CONFIG_BLOCK
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typedef void (dio_submit_t)(int rw, struct bio *bio, struct inode *inode,
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@ -2750,6 +2749,11 @@ extern int generic_show_options(struct seq_file *m, struct dentry *root);
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extern void save_mount_options(struct super_block *sb, char *options);
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extern void replace_mount_options(struct super_block *sb, char *options);
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static inline bool io_is_direct(struct file *filp)
|
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{
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return (filp->f_flags & O_DIRECT) || IS_DAX(file_inode(filp));
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}
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static inline ino_t parent_ino(struct dentry *dentry)
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{
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ino_t res;
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|
|
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|
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@ -224,6 +224,7 @@ struct vm_fault {
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pgoff_t pgoff; /* Logical page offset based on vma */
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void __user *virtual_address; /* Faulting virtual address */
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struct page *cow_page; /* Handler may choose to COW */
|
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struct page *page; /* ->fault handlers should return a
|
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* page here, unless VM_FAULT_NOPAGE
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* is set (which is also implied by
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|
|
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|
|
@ -198,7 +198,7 @@ int page_referenced(struct page *, int is_locked,
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int try_to_unmap(struct page *, enum ttu_flags flags);
|
||||
|
||||
/*
|
||||
* Called from mm/filemap_xip.c to unmap empty zero page
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* Used by uprobes to replace a userspace page safely
|
||||
*/
|
||||
pte_t *__page_check_address(struct page *, struct mm_struct *,
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||||
unsigned long, spinlock_t **, int);
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||||
|
|
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|||
375
include/linux/rtc/ds1685.h
Normal file
375
include/linux/rtc/ds1685.h
Normal file
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@ -0,0 +1,375 @@
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|||
/*
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* Definitions for the registers, addresses, and platform data of the
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* DS1685/DS1687-series RTC chips.
|
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*
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* This Driver also works for the DS17X85/DS17X87 RTC chips. Functionally
|
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* similar to the DS1685/DS1687, they support a few extra features which
|
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* include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
|
||||
* write counter.
|
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*
|
||||
* Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
|
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* Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
|
||||
*
|
||||
* References:
|
||||
* DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
|
||||
* DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
|
||||
* DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
|
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* Application Note 90, Using the Multiplex Bus RTC Extended Features.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
|
||||
*/
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||||
#ifndef _LINUX_RTC_DS1685_H_
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#define _LINUX_RTC_DS1685_H_
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#include <linux/rtc.h>
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#include <linux/platform_device.h>
|
||||
#include <linux/workqueue.h>
|
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|
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/**
|
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* struct ds1685_priv - DS1685 private data structure.
|
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* @dev: pointer to the rtc_device structure.
|
||||
* @regs: iomapped base address pointer of the RTC registers.
|
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* @regstep: padding/step size between registers (optional).
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* @baseaddr: base address of the RTC device.
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* @size: resource size.
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* @lock: private lock variable for spin locking/unlocking.
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* @work: private workqueue.
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* @irq: IRQ number assigned to the RTC device.
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* @prepare_poweroff: pointer to platform pre-poweroff function.
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* @wake_alarm: pointer to platform wake alarm function.
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* @post_ram_clear: pointer to platform post ram-clear function.
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*/
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struct ds1685_priv {
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struct rtc_device *dev;
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void __iomem *regs;
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u32 regstep;
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resource_size_t baseaddr;
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size_t size;
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spinlock_t lock;
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struct work_struct work;
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int irq_num;
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bool bcd_mode;
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bool no_irq;
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bool uie_unsupported;
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bool alloc_io_resources;
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u8 (*read)(struct ds1685_priv *, int);
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void (*write)(struct ds1685_priv *, int, u8);
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void (*prepare_poweroff)(void);
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void (*wake_alarm)(void);
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void (*post_ram_clear)(void);
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};
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/**
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* struct ds1685_rtc_platform_data - platform data structure.
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* @plat_prepare_poweroff: platform-specific pre-poweroff function.
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* @plat_wake_alarm: platform-specific wake alarm function.
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* @plat_post_ram_clear: platform-specific post ram-clear function.
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*
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* If your platform needs to use a custom padding/step size between
|
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* registers, or uses one or more of the extended interrupts and needs special
|
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* handling, then include this header file in your platform definition and
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* set regstep and the plat_* pointers as appropriate.
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*/
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struct ds1685_rtc_platform_data {
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const u32 regstep;
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const bool bcd_mode;
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const bool no_irq;
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const bool uie_unsupported;
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const bool alloc_io_resources;
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u8 (*plat_read)(struct ds1685_priv *, int);
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void (*plat_write)(struct ds1685_priv *, int, u8);
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void (*plat_prepare_poweroff)(void);
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void (*plat_wake_alarm)(void);
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void (*plat_post_ram_clear)(void);
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};
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/*
|
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* Time Registers.
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*/
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#define RTC_SECS 0x00 /* Seconds 00-59 */
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#define RTC_SECS_ALARM 0x01 /* Alarm Seconds 00-59 */
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#define RTC_MINS 0x02 /* Minutes 00-59 */
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#define RTC_MINS_ALARM 0x03 /* Alarm Minutes 00-59 */
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#define RTC_HRS 0x04 /* Hours 01-12 AM/PM || 00-23 */
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#define RTC_HRS_ALARM 0x05 /* Alarm Hours 01-12 AM/PM || 00-23 */
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#define RTC_WDAY 0x06 /* Day of Week 01-07 */
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#define RTC_MDAY 0x07 /* Day of Month 01-31 */
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#define RTC_MONTH 0x08 /* Month 01-12 */
|
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#define RTC_YEAR 0x09 /* Year 00-99 */
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#define RTC_CENTURY 0x48 /* Century 00-99 */
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#define RTC_MDAY_ALARM 0x49 /* Alarm Day of Month 01-31 */
|
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/*
|
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* Bit masks for the Time registers in BCD Mode (DM = 0).
|
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*/
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#define RTC_SECS_BCD_MASK 0x7f /* - x x x x x x x */
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#define RTC_MINS_BCD_MASK 0x7f /* - x x x x x x x */
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#define RTC_HRS_12_BCD_MASK 0x1f /* - - - x x x x x */
|
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#define RTC_HRS_24_BCD_MASK 0x3f /* - - x x x x x x */
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#define RTC_MDAY_BCD_MASK 0x3f /* - - x x x x x x */
|
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#define RTC_MONTH_BCD_MASK 0x1f /* - - - x x x x x */
|
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#define RTC_YEAR_BCD_MASK 0xff /* x x x x x x x x */
|
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|
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/*
|
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* Bit masks for the Time registers in BIN Mode (DM = 1).
|
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*/
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#define RTC_SECS_BIN_MASK 0x3f /* - - x x x x x x */
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#define RTC_MINS_BIN_MASK 0x3f /* - - x x x x x x */
|
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#define RTC_HRS_12_BIN_MASK 0x0f /* - - - - x x x x */
|
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#define RTC_HRS_24_BIN_MASK 0x1f /* - - - x x x x x */
|
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#define RTC_MDAY_BIN_MASK 0x1f /* - - - x x x x x */
|
||||
#define RTC_MONTH_BIN_MASK 0x0f /* - - - - x x x x */
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#define RTC_YEAR_BIN_MASK 0x7f /* - x x x x x x x */
|
||||
|
||||
/*
|
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* Bit masks common for the Time registers in BCD or BIN Mode.
|
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*/
|
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#define RTC_WDAY_MASK 0x07 /* - - - - - x x x */
|
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#define RTC_CENTURY_MASK 0xff /* x x x x x x x x */
|
||||
#define RTC_MDAY_ALARM_MASK 0xff /* x x x x x x x x */
|
||||
#define RTC_HRS_AMPM_MASK BIT(7) /* Mask for the AM/PM bit */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Control Registers.
|
||||
*/
|
||||
#define RTC_CTRL_A 0x0a /* Control Register A */
|
||||
#define RTC_CTRL_B 0x0b /* Control Register B */
|
||||
#define RTC_CTRL_C 0x0c /* Control Register C */
|
||||
#define RTC_CTRL_D 0x0d /* Control Register D */
|
||||
#define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */
|
||||
#define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */
|
||||
|
||||
|
||||
/*
|
||||
* Bit names in Control Register A.
|
||||
*/
|
||||
#define RTC_CTRL_A_UIP BIT(7) /* Update In Progress */
|
||||
#define RTC_CTRL_A_DV2 BIT(6) /* Countdown Chain */
|
||||
#define RTC_CTRL_A_DV1 BIT(5) /* Oscillator Enable */
|
||||
#define RTC_CTRL_A_DV0 BIT(4) /* Bank Select */
|
||||
#define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */
|
||||
#define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */
|
||||
#define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */
|
||||
#define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */
|
||||
#define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */
|
||||
|
||||
/*
|
||||
* Bit names in Control Register B.
|
||||
*/
|
||||
#define RTC_CTRL_B_SET BIT(7) /* SET Bit */
|
||||
#define RTC_CTRL_B_PIE BIT(6) /* Periodic-Interrupt Enable */
|
||||
#define RTC_CTRL_B_AIE BIT(5) /* Alarm-Interrupt Enable */
|
||||
#define RTC_CTRL_B_UIE BIT(4) /* Update-Ended Interrupt-Enable */
|
||||
#define RTC_CTRL_B_SQWE BIT(3) /* Square-Wave Enable */
|
||||
#define RTC_CTRL_B_DM BIT(2) /* Data Mode */
|
||||
#define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */
|
||||
#define RTC_CTRL_B_DSE BIT(0) /* Daylight Savings Enable */
|
||||
#define RTC_CTRL_B_PAU_MASK 0x70 /* PIE + AIE + UIE */
|
||||
|
||||
|
||||
/*
|
||||
* Bit names in Control Register C.
|
||||
*
|
||||
* BIT(0), BIT(1), BIT(2), & BIT(3) are unused, always return 0, and cannot
|
||||
* be written to.
|
||||
*/
|
||||
#define RTC_CTRL_C_IRQF BIT(7) /* Interrupt-Request Flag */
|
||||
#define RTC_CTRL_C_PF BIT(6) /* Periodic-Interrupt Flag */
|
||||
#define RTC_CTRL_C_AF BIT(5) /* Alarm-Interrupt Flag */
|
||||
#define RTC_CTRL_C_UF BIT(4) /* Update-Ended Interrupt Flag */
|
||||
#define RTC_CTRL_C_PAU_MASK 0x70 /* PF + AF + UF */
|
||||
|
||||
|
||||
/*
|
||||
* Bit names in Control Register D.
|
||||
*
|
||||
* BIT(0) through BIT(6) are unused, always return 0, and cannot
|
||||
* be written to.
|
||||
*/
|
||||
#define RTC_CTRL_D_VRT BIT(7) /* Valid RAM and Time */
|
||||
|
||||
|
||||
/*
|
||||
* Bit names in Extended Control Register 4A.
|
||||
*
|
||||
* On the DS1685/DS1687/DS1689/DS1693, BIT(4) and BIT(5) are reserved for
|
||||
* future use. They can be read from and written to, but have no effect
|
||||
* on the RTC's operation.
|
||||
*
|
||||
* On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows
|
||||
* access to the extended NV-SRAM by automatically incrementing the address
|
||||
* register when they are read from or written to.
|
||||
*/
|
||||
#define RTC_CTRL_4A_VRT2 BIT(7) /* Auxillary Battery Status */
|
||||
#define RTC_CTRL_4A_INCR BIT(6) /* Increment-in-Progress Status */
|
||||
#define RTC_CTRL_4A_PAB BIT(3) /* Power-Active Bar Control */
|
||||
#define RTC_CTRL_4A_RF BIT(2) /* RAM-Clear Flag */
|
||||
#define RTC_CTRL_4A_WF BIT(1) /* Wake-Up Alarm Flag */
|
||||
#define RTC_CTRL_4A_KF BIT(0) /* Kickstart Flag */
|
||||
#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
|
||||
#define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */
|
||||
#endif
|
||||
#define RTC_CTRL_4A_RWK_MASK 0x07 /* RF + WF + KF */
|
||||
|
||||
|
||||
/*
|
||||
* Bit names in Extended Control Register 4B.
|
||||
*/
|
||||
#define RTC_CTRL_4B_ABE BIT(7) /* Auxillary Battery Enable */
|
||||
#define RTC_CTRL_4B_E32K BIT(6) /* Enable 32.768Hz on SQW Pin */
|
||||
#define RTC_CTRL_4B_CS BIT(5) /* Crystal Select */
|
||||
#define RTC_CTRL_4B_RCE BIT(4) /* RAM Clear-Enable */
|
||||
#define RTC_CTRL_4B_PRS BIT(3) /* PAB Reset-Select */
|
||||
#define RTC_CTRL_4B_RIE BIT(2) /* RAM Clear-Interrupt Enable */
|
||||
#define RTC_CTRL_4B_WIE BIT(1) /* Wake-Up Alarm-Interrupt Enable */
|
||||
#define RTC_CTRL_4B_KSE BIT(0) /* Kickstart Interrupt-Enable */
|
||||
#define RTC_CTRL_4B_RWK_MASK 0x07 /* RIE + WIE + KSE */
|
||||
|
||||
|
||||
/*
|
||||
* Misc register names in Bank 1.
|
||||
*
|
||||
* The DV0 bit in Control Register A must be set to 1 for these registers
|
||||
* to become available, including Extended Control Registers 4A & 4B.
|
||||
*/
|
||||
#define RTC_BANK1_SSN_MODEL 0x40 /* Model Number */
|
||||
#define RTC_BANK1_SSN_BYTE_1 0x41 /* 1st Byte of Serial Number */
|
||||
#define RTC_BANK1_SSN_BYTE_2 0x42 /* 2nd Byte of Serial Number */
|
||||
#define RTC_BANK1_SSN_BYTE_3 0x43 /* 3rd Byte of Serial Number */
|
||||
#define RTC_BANK1_SSN_BYTE_4 0x44 /* 4th Byte of Serial Number */
|
||||
#define RTC_BANK1_SSN_BYTE_5 0x45 /* 5th Byte of Serial Number */
|
||||
#define RTC_BANK1_SSN_BYTE_6 0x46 /* 6th Byte of Serial Number */
|
||||
#define RTC_BANK1_SSN_CRC 0x47 /* Serial CRC Byte */
|
||||
#define RTC_BANK1_RAM_DATA_PORT 0x53 /* Extended RAM Data Port */
|
||||
|
||||
|
||||
/*
|
||||
* Model-specific registers in Bank 1.
|
||||
*
|
||||
* The addresses below differ depending on the model of the RTC chip
|
||||
* selected in the kernel configuration. Not all of these features are
|
||||
* supported in the main driver at present.
|
||||
*
|
||||
* DS1685/DS1687 - Extended NV-SRAM address (LSB only).
|
||||
* DS1689/DS1693 - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N.
|
||||
* DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter.
|
||||
*/
|
||||
#if defined(CONFIG_RTC_DRV_DS1685)
|
||||
#define RTC_BANK1_RAM_ADDR 0x50 /* NV-SRAM Addr */
|
||||
#elif defined(CONFIG_RTC_DRV_DS1689)
|
||||
#define RTC_BANK1_VCC_CTR_LSB 0x54 /* Vcc Counter Addr (LSB) */
|
||||
#define RTC_BANK1_VCC_CTR_MSB 0x57 /* Vcc Counter Addr (MSB) */
|
||||
#define RTC_BANK1_VBAT_CTR_LSB 0x58 /* Vbat Counter Addr (LSB) */
|
||||
#define RTC_BANK1_VBAT_CTR_MSB 0x5b /* Vbat Counter Addr (MSB) */
|
||||
#define RTC_BANK1_PWR_CTR_LSB 0x5c /* Pwr Cycle Counter Addr (LSB) */
|
||||
#define RTC_BANK1_PWR_CTR_MSB 0x5d /* Pwr Cycle Counter Addr (MSB) */
|
||||
#define RTC_BANK1_UNIQ_SN 0x60 /* Customer-specific S/N */
|
||||
#else /* DS17x85/DS17x87 */
|
||||
#define RTC_BANK1_RAM_ADDR_LSB 0x50 /* NV-SRAM Addr (LSB) */
|
||||
#define RTC_BANK1_RAM_ADDR_MSB 0x51 /* NV-SRAM Addr (MSB) */
|
||||
#define RTC_BANK1_WRITE_CTR 0x5e /* RTC Write Counter */
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Model numbers.
|
||||
*
|
||||
* The DS1688/DS1691 and DS1689/DS1693 chips share the same model number
|
||||
* and the manual doesn't indicate any major differences. As such, they
|
||||
* are regarded as the same chip in this driver.
|
||||
*/
|
||||
#define RTC_MODEL_DS1685 0x71 /* DS1685/DS1687 */
|
||||
#define RTC_MODEL_DS17285 0x72 /* DS17285/DS17287 */
|
||||
#define RTC_MODEL_DS1689 0x73 /* DS1688/DS1691/DS1689/DS1693 */
|
||||
#define RTC_MODEL_DS17485 0x74 /* DS17485/DS17487 */
|
||||
#define RTC_MODEL_DS17885 0x78 /* DS17885/DS17887 */
|
||||
|
||||
|
||||
/*
|
||||
* Periodic Interrupt Rates / Square-Wave Output Frequency
|
||||
*
|
||||
* Periodic rates are selected by setting the RS3-RS0 bits in Control
|
||||
* Register A and enabled via either the E32K bit in Extended Control
|
||||
* Register 4B or the SQWE bit in Control Register B.
|
||||
*
|
||||
* E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz
|
||||
* on the SQW pin of the RTC chip. While there are 16 possible selections,
|
||||
* the 1-of-16 decoder is only able to divide the base 32768Hz signal into 13
|
||||
* smaller frequencies. The values 0x01 and 0x02 are not used and are
|
||||
* synonymous with 0x08 and 0x09, respectively.
|
||||
*
|
||||
* When E32K is set to a logic 1, periodic interrupts are disabled and reading
|
||||
* /dev/rtc will return -EINVAL. This also applies if the periodic interrupt
|
||||
* frequency is set to 0Hz.
|
||||
*
|
||||
* Not currently used by the rtc-ds1685 driver because the RTC core removed
|
||||
* support for hardware-generated periodic-interrupts in favour of
|
||||
* hrtimer-generated interrupts. But these defines are kept around for use
|
||||
* in userland, as documentation to the hardware, and possible future use if
|
||||
* hardware-generated periodic interrupts are ever added back.
|
||||
*/
|
||||
/* E32K RS3 RS2 RS1 RS0 */
|
||||
#define RTC_SQW_8192HZ 0x03 /* 0 0 0 1 1 */
|
||||
#define RTC_SQW_4096HZ 0x04 /* 0 0 1 0 0 */
|
||||
#define RTC_SQW_2048HZ 0x05 /* 0 0 1 0 1 */
|
||||
#define RTC_SQW_1024HZ 0x06 /* 0 0 1 1 0 */
|
||||
#define RTC_SQW_512HZ 0x07 /* 0 0 1 1 1 */
|
||||
#define RTC_SQW_256HZ 0x08 /* 0 1 0 0 0 */
|
||||
#define RTC_SQW_128HZ 0x09 /* 0 1 0 0 1 */
|
||||
#define RTC_SQW_64HZ 0x0a /* 0 1 0 1 0 */
|
||||
#define RTC_SQW_32HZ 0x0b /* 0 1 0 1 1 */
|
||||
#define RTC_SQW_16HZ 0x0c /* 0 1 1 0 0 */
|
||||
#define RTC_SQW_8HZ 0x0d /* 0 1 1 0 1 */
|
||||
#define RTC_SQW_4HZ 0x0e /* 0 1 1 1 0 */
|
||||
#define RTC_SQW_2HZ 0x0f /* 0 1 1 1 1 */
|
||||
#define RTC_SQW_0HZ 0x00 /* 0 0 0 0 0 */
|
||||
#define RTC_SQW_32768HZ 32768 /* 1 - - - - */
|
||||
#define RTC_MAX_USER_FREQ 8192
|
||||
|
||||
|
||||
/*
|
||||
* NVRAM data & addresses:
|
||||
* - 50 bytes of NVRAM are available just past the clock registers.
|
||||
* - 64 additional bytes are available in Bank0.
|
||||
*
|
||||
* Extended, battery-backed NV-SRAM:
|
||||
* - DS1685/DS1687 - 128 bytes.
|
||||
* - DS1689/DS1693 - 0 bytes.
|
||||
* - DS17285/DS17287 - 2048 bytes.
|
||||
* - DS17485/DS17487 - 4096 bytes.
|
||||
* - DS17885/DS17887 - 8192 bytes.
|
||||
*/
|
||||
#define NVRAM_TIME_BASE 0x0e /* NVRAM Addr in Time regs */
|
||||
#define NVRAM_BANK0_BASE 0x40 /* NVRAM Addr in Bank0 regs */
|
||||
#define NVRAM_SZ_TIME 50
|
||||
#define NVRAM_SZ_BANK0 64
|
||||
#if defined(CONFIG_RTC_DRV_DS1685)
|
||||
# define NVRAM_SZ_EXTND 128
|
||||
#elif defined(CONFIG_RTC_DRV_DS1689)
|
||||
# define NVRAM_SZ_EXTND 0
|
||||
#elif defined(CONFIG_RTC_DRV_DS17285)
|
||||
# define NVRAM_SZ_EXTND 2048
|
||||
#elif defined(CONFIG_RTC_DRV_DS17485)
|
||||
# define NVRAM_SZ_EXTND 4096
|
||||
#elif defined(CONFIG_RTC_DRV_DS17885)
|
||||
# define NVRAM_SZ_EXTND 8192
|
||||
#endif
|
||||
#define NVRAM_TOTAL_SZ_BANK0 (NVRAM_SZ_TIME + NVRAM_SZ_BANK0)
|
||||
#define NVRAM_TOTAL_SZ (NVRAM_TOTAL_SZ_BANK0 + NVRAM_SZ_EXTND)
|
||||
|
||||
|
||||
/*
|
||||
* Function Prototypes.
|
||||
*/
|
||||
extern void __noreturn
|
||||
ds1685_rtc_poweroff(struct platform_device *pdev);
|
||||
|
||||
#endif /* _LINUX_RTC_DS1685_H_ */
|
||||
Loading…
Reference in a new issue