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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add initial devicetrees for SDXNIGHTJAR target
Add initial devicetree files for supporing SDXNIGHTJAR target. Change-Id: I78a27e41723c3ff3a90955285ab5508dc6187855
This commit is contained in:
Lijuan Gao
parent
1d6d638dc3
commit
c4c41afbad
11 changed files with 1996 additions and 0 deletions
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@ -95,6 +95,9 @@ SoCs:
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- MONACO
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compatible = "qcom,monaco"
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- SDXNIGHTJAR
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compatible = "qcom,sdxnightjar"
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Generic board variants:
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- CDP device:
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@ -255,3 +258,6 @@ compatible = "qcom,holi-qrd"
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compatible = "qcom,holi-atp"
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compatible = "qcom,scuba-idp"
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compatible = "qcom,monaco-rumi"
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compatible = "qcom,sdxnightjar-mtp"
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compatible = "qcom,sdxnightjar-cdp"
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compatible = "qcom,sdxnightjar-qrd"
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171
bindings/interrupt-controller/arm,gic.txt
Normal file
171
bindings/interrupt-controller/arm,gic.txt
Normal file
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@ -0,0 +1,171 @@
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* ARM Generic Interrupt Controller
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ARM SMP cores are often associated with a GIC, providing per processor
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interrupts (PPI), shared processor interrupts (SPI) and software
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generated interrupts (SGI).
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Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
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Secondary GICs are cascaded into the upward interrupt controller and do not
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have PPIs or SGIs.
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Main node required properties:
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- compatible : should be one of:
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"arm,arm1176jzf-devchip-gic"
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"arm,arm11mp-gic"
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"arm,cortex-a15-gic"
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"arm,cortex-a7-gic"
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"arm,cortex-a9-gic"
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"arm,eb11mp-gic"
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"arm,gic-400"
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"arm,pl390"
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"arm,tc11mp-gic"
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"brcm,brahma-b15-gic"
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"nvidia,tegra210-agic"
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"qcom,msm-8660-qgic"
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"qcom,msm-qgic2"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 3.
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The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
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interrupts.
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The 2nd cell contains the interrupt number for the interrupt type.
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SPI interrupts are in the range [0-987]. PPI interrupts are in the
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range [0-15].
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The 3rd cell is the flags, encoded as follows:
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bits[3:0] trigger type and level flags.
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered (invalid for SPIs)
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4 = active high level-sensitive
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8 = active low level-sensitive (invalid for SPIs).
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bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
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the 8 possible cpus attached to the GIC. A bit set to '1' indicated
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the interrupt is wired to that CPU. Only valid for PPI interrupts.
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Also note that the configurability of PPI interrupts is IMPLEMENTATION
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DEFINED and as such not guaranteed to be present (most SoC available
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in 2014 seem to ignore the setting of this flag and use the hardware
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default value).
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- reg : Specifies base physical address(s) and size of the GIC registers. The
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first region is the GIC distributor register base and size. The 2nd region is
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the GIC cpu interface register base and size.
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Optional
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- interrupts : Interrupt source of the parent interrupt controller on
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secondary GICs, or VGIC maintenance interrupt on primary GIC (see
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below).
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- cpu-offset : per-cpu offset within the distributor and cpu interface
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regions, used when the GIC doesn't have banked registers. The offset is
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cpu-offset * cpu-nr.
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- clocks : List of phandle and clock-specific pairs, one for each entry
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in clock-names.
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- clock-names : List of names for the GIC clock input(s). Valid clock names
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depend on the GIC variant:
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"ic_clk" (for "arm,arm11mp-gic")
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"PERIPHCLKEN" (for "arm,cortex-a15-gic")
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"PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
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"clk" (for "arm,gic-400" and "nvidia,tegra210")
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"gclk" (for "arm,pl390")
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- power-domains : A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle, used when the GIC
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is part of a Power or Clock Domain.
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Example:
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xfff11000 0x1000>,
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<0xfff10100 0x100>;
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};
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* GIC virtualization extensions (VGIC)
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For ARM cores that support the virtualization extensions, additional
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properties must be described (they only exist if the GIC is the
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primary interrupt controller).
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Required properties:
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- reg : Additional regions specifying the base physical address and
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size of the VGIC registers. The first additional region is the GIC
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virtual interface control register base and size. The 2nd additional
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region is the GIC virtual cpu interface register base and size.
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- interrupts : VGIC maintenance interrupt.
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Example:
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interrupt-controller@2c001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x2c001000 0x1000>,
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<0x2c002000 0x1000>,
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<0x2c004000 0x2000>,
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<0x2c006000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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* GICv2m extension for MSI/MSI-x support (Optional)
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Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
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This is enabled by specifying v2m sub-node(s).
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Required properties:
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- compatible : The value here should contain "arm,gic-v2m-frame".
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- msi-controller : Identifies the node as an MSI controller.
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- reg : GICv2m MSI interface register base and size
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Optional properties:
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- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
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value, this property should contain the SPI base of
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the MSI frame, overriding the HW value.
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- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
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value, this property should contain the number of
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SPIs assigned to the frame, overriding the HW value.
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Example:
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interrupt-controller@e1101000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller;
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interrupts = <1 8 0xf04>;
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ranges = <0 0 0 0xe1100000 0 0x100000>;
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reg = <0x0 0xe1110000 0 0x01000>,
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<0x0 0xe112f000 0 0x02000>,
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<0x0 0xe1140000 0 0x10000>,
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<0x0 0xe1160000 0 0x10000>;
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v2m0: v2m@0x8000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x80000 0 0x1000>;
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};
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....
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v2mN: v2m@0x9000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x90000 0 0x1000>;
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};
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};
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@ -217,6 +217,10 @@ dtb-$(CONFIG_ARCH_QTI_VM) += shima-vm-rumi.dtb \
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endif
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endif
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dtb-$(CONFIG_ARCH_SDXNIGHTJAR) += sdxnightjar-mtp.dtb \
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sdxnightjar-cdp.dtb \
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sdxnightjar-qrd.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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11
qcom/sdxnightjar-cdp.dts
Normal file
11
qcom/sdxnightjar-cdp.dts
Normal file
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxnightjar.dtsi"
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#include "sdxnightjar-cdp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDX NIGHTJAR CDP";
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compatible = "qcom,sdxnightjar-cdp",
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"qcom,sdxnightjar", "qcom,cdp";
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qcom,board-id = <0x01 0>;
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};
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6
qcom/sdxnightjar-cdp.dtsi
Normal file
6
qcom/sdxnightjar-cdp.dtsi
Normal file
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@ -0,0 +1,6 @@
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&blsp1_uart3 {
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status = "ok"
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_console_active>;
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};
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11
qcom/sdxnightjar-mtp.dts
Normal file
11
qcom/sdxnightjar-mtp.dts
Normal file
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxnightjar.dtsi"
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#include "sdxnightjar-mtp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDX NIGHTJAR MTP";
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compatible = "qcom,sdxnightjar-mtp",
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"qcom,sdxnightjar", "qcom,mtp";
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qcom,board-id = <8 0>;
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};
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6
qcom/sdxnightjar-mtp.dtsi
Normal file
6
qcom/sdxnightjar-mtp.dtsi
Normal file
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@ -0,0 +1,6 @@
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&blsp1_uart3 {
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status = "ok"
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_console_active>;
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};
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1335
qcom/sdxnightjar-pinctrl.dtsi
Normal file
1335
qcom/sdxnightjar-pinctrl.dtsi
Normal file
File diff suppressed because it is too large
Load diff
11
qcom/sdxnightjar-qrd.dts
Normal file
11
qcom/sdxnightjar-qrd.dts
Normal file
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxnightjar.dtsi"
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#include "sdxnightjar-qrd.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDX NIGHTJAR QRD";
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compatible = "qcom,sdxnightjar-qrd",
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"qcom,sdxnightjar", "qcom,qrd";
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qcom,board-id = <0xB 0>;
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};
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6
qcom/sdxnightjar-qrd.dtsi
Normal file
6
qcom/sdxnightjar-qrd.dtsi
Normal file
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@ -0,0 +1,6 @@
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&blsp1_uart3 {
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status = "ok"
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_console_active>;
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};
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429
qcom/sdxnightjar.dtsi
Normal file
429
qcom/sdxnightjar.dtsi
Normal file
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@ -0,0 +1,429 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDXNIGHTJAR";
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compatible = "qcom,sdxnightjar";
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qcom,msm-id = <484 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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chosen { };
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memory {
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device_type = "memory";
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reg = <0 0>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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peripheral1_mem: peripheral1_region@0x87800000 {
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no-map;
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reg = <0x87800000 0x400000>;
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label = "peripheral1_mem";
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};
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peripheral2_mem: peripheral2_region@0x87d00000 {
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no-map;
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reg = <0x87d00000 0x300000>;
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label = "peripheral2_mem";
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};
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};
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aliases { };
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>,
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<0x0b002000 0x1000>;
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};
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qcom,mpm2-sleep-counter@4a3000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0x004a3000 0x1000>;
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clock-frequency = <32768>;
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};
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qcom,msm-imem@8600000 {
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compatible = "qcom,msm-imem";
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reg = <0x8600000 0x1000>; /* Address and size of IMEM */
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ranges = <0x0 0x8600000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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};
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clock_gcc: qcom,gcc@1800000 {
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ompatible = "qcom,dummycc";
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#clock-cells = <1>;
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};
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clock_debug: qcom,cc-debug@1874000 {
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compatible = "qcom,dummycc";
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#clock-cells = <1>;
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};
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clock_cpu: qcom,clock-a7@0b010008 {
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compatible = "qcom,dummycc";
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#clock-cells = <1>;
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};
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qcom,msm-cpufreq {
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compatible = "qcom,msm-cpufreq";
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/*TODO: Fix the clock when tree is available*/
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clock-names = "cpu0_clk", "cpu1_clk",
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"cpu2_clk", "cpu3_clk";
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qcom,cpufreq-table =
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< 200000 >,
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< 300000 >,
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< 384000 >,
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< 600000 >,
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< 787200 >,
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< 998400 >,
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< 1190400 >,
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< 1286400 >;
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};
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ahb_clk: qcom,ahb-clk-src {
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compatible = "devfreq-simple-dev";
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clock-names = "devfreq_clk";
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/*TODO: Fix the clock when tree is available*/
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governor = "powersave";
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freq-tbl-khz =
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< 19200 >,
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< 50000 >,
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< 100000 >,
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< 133330 >;
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};
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restart@4ab000 {
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>,
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<0x0193d100 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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timer@b020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xb020000 0x1000>;
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clock-frequency = <19200000>;
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frame@b021000 {
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frame-number = <0>;
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interrupts = <0 7 0x4>,
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<0 6 0x4>;
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reg = <0xb021000 0x1000>,
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<0xb022000 0x1000>;
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};
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frame@b023000 {
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frame-number = <1>;
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interrupts = <0 8 0x4>;
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reg = <0xb023000 0x1000>;
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status = "disabled";
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};
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frame@b024000 {
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frame-number = <2>;
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interrupts = <0 9 0x4>;
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reg = <0xb024000 0x1000>;
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status = "disabled";
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};
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frame@b025000 {
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frame-number = <3>;
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interrupts = <0 10 0x4>;
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reg = <0xb025000 0x1000>;
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status = "disabled";
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};
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frame@b026000 {
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frame-number = <4>;
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interrupts = <0 11 0x4>;
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reg = <0xb026000 0x1000>;
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status = "disabled";
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};
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frame@b027000 {
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frame-number = <5>;
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interrupts = <0 12 0x4>;
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reg = <0xb027000 0x1000>;
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status = "disabled";
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||||
};
|
||||
|
||||
frame@b028000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <0 13 0x4>;
|
||||
reg = <0xb028000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b029000 {
|
||||
frame-number = <7>;
|
||||
interrupts = <0 14 0x4>;
|
||||
reg = <0xb029000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
qcom,msm_gsi {
|
||||
compatible = "qcom,msm_gsi";
|
||||
};
|
||||
|
||||
qcom_rng: qrng@e3000 {
|
||||
compatible = "qcom,msm-rng";
|
||||
reg = <0xe3000 0x1000>;
|
||||
qcom,msm-rng-iface-clk;
|
||||
qcom,no-qrng-config;
|
||||
qcom,msm-bus,name = "msm-rng-noc";
|
||||
qcom,msm-bus,num-cases = <2>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<1 618 0 0>, /* No vote */
|
||||
<1 618 0 800>; /* 100 MB/s */
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "iface_clk";
|
||||
};
|
||||
|
||||
qcom_tzlog: tz-log@08600720 {
|
||||
compatible = "qcom,tz-log";
|
||||
reg = <0x08600720 0x2000>;
|
||||
};
|
||||
|
||||
qcom,qcedev@720000 {
|
||||
compatible = "qcom,qcedev";
|
||||
reg = <0x720000 0x20000>,
|
||||
<0x704000 0x20000>;
|
||||
reg-names = "crypto-base","crypto-bam-base";
|
||||
interrupts = <0 207 0>;
|
||||
qcom,bam-pipe-pair = <1>;
|
||||
qcom,ce-hw-instance = <0>;
|
||||
qcom,ce-device = <0>;
|
||||
qcom,ce-hw-shared;
|
||||
qcom,msm-bus,name = "qcedev-noc";
|
||||
qcom,msm-bus,num-cases = <2>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<47 512 0 0>,
|
||||
<47 512 393600 393600>;
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "core_clk", "iface_clk",
|
||||
"bus_clk","core_clk_src";
|
||||
qcom,ce-opp-freq = <171430000>;
|
||||
};
|
||||
|
||||
qcom,qcrypto@720000 {
|
||||
compatible = "qcom,qcrypto";
|
||||
reg = <0x720000 0x20000>,
|
||||
<0x704000 0x20000>;
|
||||
reg-names = "crypto-base","crypto-bam-base";
|
||||
interrupts = <0 207 0>;
|
||||
qcom,bam-pipe-pair = <2>;
|
||||
qcom,ce-hw-instance = <0>;
|
||||
qcom,ce-device = <0>;
|
||||
qcom,ce-hw-shared;
|
||||
qcom,msm-bus,name = "qcrypto-noc";
|
||||
qcom,msm-bus,num-cases = <2>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<47 512 0 0>,
|
||||
<47 512 393600 393600>;
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "core_clk", "iface_clk",
|
||||
"bus_clk","core_clk_src";
|
||||
qcom,use-sw-aes-cbc-ecb-ctr-algo;
|
||||
qcom,use-sw-aes-xts-algo;
|
||||
qcom,use-sw-aes-ccm-algo;
|
||||
qcom,use-sw-ahash-algo;
|
||||
qcom,use-sw-hmac-algo;
|
||||
qcom,use-sw-aead-algo;
|
||||
qcom,ce-opp-freq = <171430000>;
|
||||
};
|
||||
|
||||
qcom_seecom: qseecom@87800000 {
|
||||
compatible = "qcom,qseecom";
|
||||
reg = <0x87800000 0x200000>;
|
||||
reg-names = "secapp-region";
|
||||
qcom,hlos-ce-hw-instance = <0>;
|
||||
qcom,qsee-ce-hw-instance = <0>;
|
||||
qcom,msm-bus,name = "qseecom-noc";
|
||||
qcom,msm-bus,num-cases = <4>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<47 512 0 0>,
|
||||
<47 512 200000 400000>,
|
||||
<47 512 300000 800000>,
|
||||
<47 512 400000 1000000>;
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "core_clk", "iface_clk",
|
||||
"bus_clk","core_clk_src";
|
||||
qcom,ce-opp-freq = <100000000>;
|
||||
};
|
||||
|
||||
qcom,rmnet-ipa {
|
||||
compatible = "qcom,rmnet-ipa3";
|
||||
qcom,rmnet-ipa-ssr;
|
||||
};
|
||||
|
||||
blsp1_uart1: serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78af000 0x200>;
|
||||
interrupts = <0 107 0>;
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@78b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78b0000 0x200>;
|
||||
interrupts = <0 108 0>;
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart3: serial@78b1000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x78b1000 0x200>;
|
||||
interrupts = <0 109 0>;
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rpm_bus: qcom,rpm-smd {
|
||||
compatible = "qcom,rpm-smd";
|
||||
rpm-channel-name = "rpm_requests";
|
||||
rpm-channel-type = <15>; /* SMD_APPS_RPM */
|
||||
};
|
||||
|
||||
qcom,wdt@b017000 {
|
||||
compatible = "qcom,msm-watchdog";
|
||||
reg = <0xb017000 0x1000>;
|
||||
reg-names = "wdt-base";
|
||||
interrupts = <1 3 0>, <1 2 0>;
|
||||
qcom,bark-time = <11000>;
|
||||
qcom,pet-time = <10000>;
|
||||
};
|
||||
|
||||
qcom,msm-rtb {
|
||||
compatible = "qcom,msm-rtb";
|
||||
qcom,rtb-size = <0x100000>;
|
||||
};
|
||||
|
||||
jtag_mm0: jtagmm@842000 {
|
||||
compatible = "qcom,jtag-mm";
|
||||
reg = <0x842000 0x1000>,
|
||||
<0x840000 0x1000>;
|
||||
reg-names = "etm-base","debug-base";
|
||||
|
||||
qcom,coresight-jtagmm-cpu = <&CPU0>;
|
||||
|
||||
/*TODO: Fix the clock when tree is available*/
|
||||
clock-names = "core_clk", "core_a_clk";
|
||||
};
|
||||
|
||||
qcom,smem@87e80000 {
|
||||
compatible = "qcom,smem";
|
||||
reg = <0x87e80000 0xc0000>,
|
||||
<0xb011008 0x4>,
|
||||
<0x60000 0x6000>,
|
||||
<0x193d000 0x8>;
|
||||
reg-names = "smem", "irq-reg-base", "aux-mem1",
|
||||
"smem_targ_info_reg";
|
||||
qcom,mpu-enabled;
|
||||
|
||||
qcom,smd-modem {
|
||||
compatible = "qcom,smd";
|
||||
qcom,smd-edge = <0>;
|
||||
qcom,smd-irq-offset = <0x0>;
|
||||
qcom,smd-irq-bitmask = <0x1000>;
|
||||
interrupts = <0 25 1>;
|
||||
label = "modem";
|
||||
};
|
||||
|
||||
qcom,smd-rpm {
|
||||
compatible = "qcom,smd";
|
||||
qcom,smd-edge = <15>;
|
||||
qcom,smd-irq-offset = <0x0>;
|
||||
qcom,smd-irq-bitmask = <0x1>;
|
||||
interrupts = <0 168 1>;
|
||||
label = "rpm";
|
||||
qcom,irq-no-suspend;
|
||||
qcom,not-loadable;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
spmi_bus: qcom,spmi@200f000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0x200f000 0x1000>,
|
||||
<0x2400000 0x800000>,
|
||||
<0x2c00000 0x800000>,
|
||||
<0x3800000 0x200000>,
|
||||
<0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */
|
||||
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
||||
interrupts = <0 190 0>;
|
||||
qcom,pmic-arb-channel = <0>;
|
||||
qcom,pmic-arb-ee = <0>;
|
||||
qcom,pmic-arb-max-peripherals = <256>;
|
||||
qcom,pmic-arb-max-periph-interrupts = <256>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "sdxnightjar-pinctrl.dtsi"
|
||||
Loading…
Reference in a new issue