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Merge "dt-bindings: clock: Update clock ID's of GPUCC and DISPCC for SHIMA"

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qctecmdr 2020-07-19 21:01:10 -07:00 • committed by Gerrit - the friendly Code Review server
commit c5289e457d
2 changed files with 45 additions and 52 deletions
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66
include/dt-bindings/clock/qcom,dispcc-shima.h
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@ -20,41 +20,35 @@
#define DISP_CC_MDSS_BYTE1_INTF_CLK 10
#define DISP_CC_MDSS_DP_AUX_CLK 11
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 12
#define DISP_CC_MDSS_DP_CRYPTO_CLK 13
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 14
#define DISP_CC_MDSS_DP_LINK_CLK 15
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 16
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 17
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 18
#define DISP_CC_MDSS_DP_PIXEL1_CLK 19
#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 20
#define DISP_CC_MDSS_DP_PIXEL_CLK 21
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 22
#define DISP_CC_MDSS_ESC0_CLK 23
#define DISP_CC_MDSS_ESC0_CLK_SRC 24
#define DISP_CC_MDSS_ESC1_CLK 25
#define DISP_CC_MDSS_ESC1_CLK_SRC 26
#define DISP_CC_MDSS_MDP_CLK 27
#define DISP_CC_MDSS_MDP_CLK_SRC 28
#define DISP_CC_MDSS_MDP_LUT_CLK 29
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30
#define DISP_CC_MDSS_PCLK0_CLK 31
#define DISP_CC_MDSS_PCLK0_CLK_SRC 32
#define DISP_CC_MDSS_PCLK1_CLK 33
#define DISP_CC_MDSS_PCLK1_CLK_SRC 34
#define DISP_CC_MDSS_ROT_CLK 35
#define DISP_CC_MDSS_ROT_CLK_SRC 36
#define DISP_CC_MDSS_RSCC_AHB_CLK 37
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 38
#define DISP_CC_MDSS_VSYNC_CLK 39
#define DISP_CC_MDSS_VSYNC_CLK_SRC 40
#define DISP_CC_SLEEP_CLK 41
#define DISP_CC_SLEEP_CLK_SRC 42
#define DISP_CC_XO_CLK 43
#define DISP_CC_XO_CLK_SRC 44
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_RSCC_BCR 1
#define DISP_CC_MDSS_DP_LINK_CLK 13
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 14
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 15
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 16
#define DISP_CC_MDSS_DP_PIXEL1_CLK 17
#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 18
#define DISP_CC_MDSS_DP_PIXEL_CLK 19
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 20
#define DISP_CC_MDSS_ESC0_CLK 21
#define DISP_CC_MDSS_ESC0_CLK_SRC 22
#define DISP_CC_MDSS_ESC1_CLK 23
#define DISP_CC_MDSS_ESC1_CLK_SRC 24
#define DISP_CC_MDSS_MDP_CLK 25
#define DISP_CC_MDSS_MDP_CLK_SRC 26
#define DISP_CC_MDSS_MDP_LUT_CLK 27
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 28
#define DISP_CC_MDSS_PCLK0_CLK 29
#define DISP_CC_MDSS_PCLK0_CLK_SRC 30
#define DISP_CC_MDSS_PCLK1_CLK 31
#define DISP_CC_MDSS_PCLK1_CLK_SRC 32
#define DISP_CC_MDSS_ROT_CLK 33
#define DISP_CC_MDSS_ROT_CLK_SRC 34
#define DISP_CC_MDSS_RSCC_AHB_CLK 35
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 36
#define DISP_CC_MDSS_VSYNC_CLK 37
#define DISP_CC_MDSS_VSYNC_CLK_SRC 38
#define DISP_CC_SLEEP_CLK 39
#define DISP_CC_SLEEP_CLK_SRC 40
#define DISP_CC_XO_CLK 41
#define DISP_CC_XO_CLK_SRC 42
#endif

31
include/dt-bindings/clock/qcom,gpucc-shima.h
View file

@ -12,21 +12,20 @@
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CB_CLK 3
#define GPU_CC_CRC_AHB_CLK 4
#define GPU_CC_CX_APB_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CX_SNOC_DVM_CLK 7
#define GPU_CC_CXO_AON_CLK 8
#define GPU_CC_CXO_CLK 9
#define GPU_CC_GMU_CLK_SRC 10
#define GPU_CC_GX_GMU_CLK 11
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 13
#define GPU_CC_HUB_AON_CLK 14
#define GPU_CC_HUB_CLK_SRC 15
#define GPU_CC_HUB_CX_INT_CLK 16
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 17
#define GPU_CC_MND1X_0_GFX3D_CLK 18
#define GPU_CC_MND1X_1_GFX3D_CLK 19
#define GPU_CC_SLEEP_CLK 20
#define GPU_CC_CX_GMU_CLK 5
#define GPU_CC_CX_SNOC_DVM_CLK 6
#define GPU_CC_CXO_AON_CLK 7
#define GPU_CC_CXO_CLK 8
#define GPU_CC_GMU_CLK_SRC 9
#define GPU_CC_GX_GMU_CLK 10
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 12
#define GPU_CC_HUB_AON_CLK 13
#define GPU_CC_HUB_CLK_SRC 14
#define GPU_CC_HUB_CX_INT_CLK 15
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 16
#define GPU_CC_MND1X_0_GFX3D_CLK 17
#define GPU_CC_MND1X_1_GFX3D_CLK 18
#define GPU_CC_SLEEP_CLK 19
#endif