diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c index d3181c7d670a..c0775b380a90 100644 --- a/drivers/net/wireless/cnss2/pci.c +++ b/drivers/net/wireless/cnss2/pci.c @@ -136,240 +136,278 @@ static struct cnss_pci_reg qdss_csr[] = { { NULL }, }; +/* First field of the structure is the device bit mask. Use + * enum cnss_pci_reg_mask as reference for the value. + */ static struct cnss_misc_reg wcss_reg_access_seq[] = { - {0, QCA6390_GCC_DEBUG_CLK_CTL, 0}, - {1, QCA6390_GCC_DEBUG_CLK_CTL, 0x802}, - {0, QCA6390_GCC_DEBUG_CLK_CTL, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_PLL_MODE, 0}, - {1, QCA6390_GCC_DEBUG_CLK_CTL, 0x805}, - {0, QCA6390_GCC_DEBUG_CLK_CTL, 0}, - {0, QCA6390_WCSS_WFSS_PMM_WFSS_PMM_R0_PMM_CTRL, 0}, - {0, QCA6390_WCSS_PMM_TOP_PMU_CX_CSR, 0}, - {0, QCA6390_WCSS_PMM_TOP_AON_INT_RAW_STAT, 0}, - {0, QCA6390_WCSS_PMM_TOP_AON_INT_EN, 0}, - {0, QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_STS, 0}, - {1, QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_CTL, 0xD}, - {0, QCA6390_WCSS_PMM_TOP_TESTBUS_STS, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG, 0}, - {1, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG, 0}, - {1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x8}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_STS, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_CTL, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_0, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_9, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS0, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS1, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS2, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS3, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS4, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS5, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS6, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE0, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE1, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE2, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE3, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE4, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE5, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE6, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING0, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING1, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING2, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING3, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING4, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING5, 0}, - {0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING6, 0}, - {1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x30040}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x30105}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, - {0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0}, - {0, QCA6390_WCSS_CC_WCSS_UMAC_NOC_CBCR, 0}, - {0, QCA6390_WCSS_CC_WCSS_UMAC_AHB_CBCR, 0}, - {0, QCA6390_WCSS_CC_WCSS_UMAC_GDSCR, 0}, - {0, QCA6390_WCSS_CC_WCSS_WLAN1_GDSCR, 0}, - {0, QCA6390_WCSS_CC_WCSS_WLAN2_GDSCR, 0}, - {0, QCA6390_WCSS_PMM_TOP_PMM_INT_CLR, 0}, - {0, QCA6390_WCSS_PMM_TOP_AON_INT_STICKY_EN, 0}, + {1, 0, QCA6390_GCC_DEBUG_CLK_CTL, 0}, + {1, 1, QCA6390_GCC_DEBUG_CLK_CTL, 0x802}, + {1, 0, QCA6390_GCC_DEBUG_CLK_CTL, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_PLL_MODE, 0}, + {1, 1, QCA6390_GCC_DEBUG_CLK_CTL, 0x805}, + {1, 0, QCA6390_GCC_DEBUG_CLK_CTL, 0}, + {1, 0, QCA6390_WCSS_WFSS_PMM_WFSS_PMM_R0_PMM_CTRL, 0}, + {1, 0, QCA6390_WCSS_PMM_TOP_PMU_CX_CSR, 0}, + {1, 0, QCA6390_WCSS_PMM_TOP_AON_INT_RAW_STAT, 0}, + {1, 0, QCA6390_WCSS_PMM_TOP_AON_INT_EN, 0}, + {1, 0, QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_STS, 0}, + {1, 1, QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_CTL, 0xD}, + {1, 0, QCA6390_WCSS_PMM_TOP_TESTBUS_STS, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG, 0}, + {1, 1, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG, 0}, + {1, 1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x8}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_STS, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_CTL, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_0, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_9, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS0, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS1, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS2, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS3, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS4, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS5, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS6, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE0, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE1, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE2, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE3, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE4, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE5, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE6, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING0, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING1, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING2, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING3, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING4, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING5, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING6, 0}, + {1, 1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x30040}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x30105}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0}, + {1, 0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0}, + {1, 0, QCA6390_WCSS_CC_WCSS_UMAC_NOC_CBCR, 0}, + {1, 0, QCA6390_WCSS_CC_WCSS_UMAC_AHB_CBCR, 0}, + {1, 0, QCA6390_WCSS_CC_WCSS_UMAC_GDSCR, 0}, + {1, 0, QCA6390_WCSS_CC_WCSS_WLAN1_GDSCR, 0}, + {1, 0, QCA6390_WCSS_CC_WCSS_WLAN2_GDSCR, 0}, + {1, 0, QCA6390_WCSS_PMM_TOP_PMM_INT_CLR, 0}, + {1, 0, QCA6390_WCSS_PMM_TOP_AON_INT_STICKY_EN, 0}, }; static struct cnss_misc_reg pcie_reg_access_seq[] = { - {0, QCA6390_PCIE_PCIE_WCSS_STATUS_FOR_DEBUG_LOW_PCIE_LOCAL_REG, 0}, - {0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0}, - {1, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0x18}, - {0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0}, - {0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0}, - {0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_STATUS_SOC_PCIE_REG, 0}, - {0, QCA6390_PCIE_SOC_COMMIT_REPLAY_SOC_PCIE_REG, 0}, - {0, QCA6390_TLMM_GPIO_IN_OUT57, 0}, - {0, QCA6390_TLMM_GPIO_INTR_CFG57, 0}, - {0, QCA6390_TLMM_GPIO_INTR_STATUS57, 0}, - {0, QCA6390_TLMM_GPIO_IN_OUT59, 0}, - {0, QCA6390_TLMM_GPIO_INTR_CFG59, 0}, - {0, QCA6390_TLMM_GPIO_INTR_STATUS59, 0}, - {0, QCA6390_PCIE_PCIE_PARF_LTSSM, 0}, - {0, QCA6390_PCIE_PCIE_PARF_PM_STTS, 0}, - {0, QCA6390_PCIE_PCIE_PARF_PM_STTS_1, 0}, - {0, QCA6390_PCIE_PCIE_PARF_INT_STATUS, 0}, - {0, QCA6390_PCIE_PCIE_INT_ALL_STATUS, 0}, - {0, QCA6390_PCIE_PCIE_INT_ALL_MASK, 0}, - {0, QCA6390_PCIE_PCIE_PARF_BDF_TO_SID_CFG, 0}, - {0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_4, 0}, - {0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_3, 0}, - {0, QCA6390_PCIE_PCIE_PARF_MHI_CLOCK_RESET_CTRL, 0}, - {0, QCA6390_PCIE_PCIE_PARF_MHI_BASE_ADDR_LOWER, 0}, - {0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_STATUS, 0}, - {0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_CFG, 0}, - {0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2, 0}, - {0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1SUB, 0}, - {0, QCA6390_PCIE_PCIE_CORE_CONFIG, 0}, - {0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_4, 0}, - {0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L2, 0}, - {0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1, 0}, - {0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1, 0}, - {0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2, 0}, - {0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_HIGH, 0}, - {0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_LOW, 0}, - {0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_HIGH, 0}, - {0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_LOW, 0}, - {0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2, 0}, - {0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_STATUS_REG2, 0}, - {0, QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN2_CFG_REG1, 0}, - {0, QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1, 0}, - {0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_APS_STATUS_REG1, 0}, - {0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1, 0}, - {0, QCA6390_PCIE_PCIE_BHI_EXECENV_REG, 0}, + {1, 0, QCA6390_PCIE_PCIE_WCSS_STATUS_FOR_DEBUG_LOW_PCIE_LOCAL_REG, 0}, + {1, 0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0}, + {1, 1, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0x18}, + {1, 0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0}, + {1, 0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0}, + {1, 0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_STATUS_SOC_PCIE_REG, 0}, + {1, 0, QCA6390_PCIE_SOC_COMMIT_REPLAY_SOC_PCIE_REG, 0}, + {1, 0, QCA6390_TLMM_GPIO_IN_OUT57, 0}, + {1, 0, QCA6390_TLMM_GPIO_INTR_CFG57, 0}, + {1, 0, QCA6390_TLMM_GPIO_INTR_STATUS57, 0}, + {1, 0, QCA6390_TLMM_GPIO_IN_OUT59, 0}, + {1, 0, QCA6390_TLMM_GPIO_INTR_CFG59, 0}, + {1, 0, QCA6390_TLMM_GPIO_INTR_STATUS59, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_LTSSM, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_PM_STTS, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_PM_STTS_1, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_INT_STATUS, 0}, + {1, 0, QCA6390_PCIE_PCIE_INT_ALL_STATUS, 0}, + {1, 0, QCA6390_PCIE_PCIE_INT_ALL_MASK, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_BDF_TO_SID_CFG, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_4, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_3, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_MHI_CLOCK_RESET_CTRL, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_MHI_BASE_ADDR_LOWER, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_STATUS, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_CFG, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1SUB, 0}, + {1, 0, QCA6390_PCIE_PCIE_CORE_CONFIG, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_4, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L2, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1, 0}, + {1, 0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2, 0}, + {1, 0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_HIGH, 0}, + {1, 0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_LOW, 0}, + {1, 0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_HIGH, 0}, + {1, 0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_LOW, 0}, + {1, 0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2, 0}, + {1, 0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_STATUS_REG2, 0}, + {1, 0, QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN2_CFG_REG1, 0}, + {1, 0, QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1, 0}, + {1, 0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_APS_STATUS_REG1, 0}, + {1, 0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1, 0}, + {1, 0, QCA6390_PCIE_PCIE_BHI_EXECENV_REG, 0}, }; static struct cnss_misc_reg wlaon_reg_access_seq[] = { - {0, QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG, 0}, - {0, QCA6390_WLAON_SOC_POWER_CTRL, 0}, - {0, QCA6390_WLAON_PCIE_PWR_CTRL_REG, 0}, - {0, QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG, 0}, - {0, QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG, 0}, - {0, QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG, 0}, - {0, QCA6390_WLAON_SOC_POWER_CTRL, 0}, - {0, QCA6390_WLAON_SOC_PWR_WDG_BARK_THRSHD, 0}, - {0, QCA6390_WLAON_SOC_PWR_WDG_BITE_THRSHD, 0}, - {0, QCA6390_WLAON_SW_COLD_RESET, 0}, - {0, QCA6390_WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE, 0}, - {0, QCA6390_WLAON_GDSC_DELAY_SETTING, 0}, - {0, QCA6390_WLAON_GDSC_DELAY_SETTING2, 0}, - {0, QCA6390_WLAON_WL_PWR_STATUS_REG, 0}, - {0, QCA6390_WLAON_WL_AON_DBG_CFG_REG, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL1, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL6, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL7, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL3, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL4, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL5, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL8, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL2, 0}, - {0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL9, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL1, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL2, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL3, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL4, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL5, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL6, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL7, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL8, 0}, - {0, QCA6390_WLAON_RTC_CLK_CAL_CTRL9, 0}, - {0, QCA6390_WLAON_WCSSAON_CONFIG_REG, 0}, - {0, QCA6390_WLAON_WLAN_OEM_DEBUG_REG, 0}, - {0, QCA6390_WLAON_WLAN_RAM_DUMP_REG, 0}, - {0, QCA6390_WLAON_QDSS_WCSS_REG, 0}, - {0, QCA6390_WLAON_QDSS_WCSS_ACK, 0}, - {0, QCA6390_WLAON_WL_CLK_CNTL_KDF_REG, 0}, - {0, QCA6390_WLAON_WL_CLK_CNTL_PMU_HFRC_REG, 0}, - {0, QCA6390_WLAON_QFPROM_PWR_CTRL_REG, 0}, - {0, QCA6390_WLAON_DLY_CONFIG, 0}, - {0, QCA6390_WLAON_WLAON_Q6_IRQ_REG, 0}, - {0, QCA6390_WLAON_PCIE_INTF_SW_CFG_REG, 0}, - {0, QCA6390_WLAON_PCIE_INTF_STICKY_SW_CFG_REG, 0}, - {0, QCA6390_WLAON_PCIE_INTF_PHY_SW_CFG_REG, 0}, - {0, QCA6390_WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG, 0}, - {0, QCA6390_WLAON_Q6_COOKIE_BIT, 0}, - {0, QCA6390_WLAON_WARM_SW_ENTRY, 0}, - {0, QCA6390_WLAON_RESET_DBG_SW_ENTRY, 0}, - {0, QCA6390_WLAON_WL_PMUNOC_CFG_REG, 0}, - {0, QCA6390_WLAON_RESET_CAUSE_CFG_REG, 0}, - {0, QCA6390_WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG, 0}, - {0, QCA6390_WLAON_DEBUG, 0}, - {0, QCA6390_WLAON_SOC_PARAMETERS, 0}, - {0, QCA6390_WLAON_WLPM_SIGNAL, 0}, - {0, QCA6390_WLAON_SOC_RESET_CAUSE_REG, 0}, - {0, QCA6390_WLAON_WAKEUP_PCIE_SOC_REG, 0}, - {0, QCA6390_WLAON_PBL_STACK_CANARY, 0}, - {0, QCA6390_WLAON_MEM_TOT_NUM_GRP_REG, 0}, - {0, QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP0_REG, 0}, - {0, QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP1_REG, 0}, - {0, QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP2_REG, 0}, - {0, QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP3_REG, 0}, - {0, QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP0_REG, 0}, - {0, QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP1_REG, 0}, - {0, QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP2_REG, 0}, - {0, QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP3_REG, 0}, - {0, QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG, 0}, - {0, QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG, 0}, - {0, QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG, 0}, - {0, QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG, 0}, - {0, QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG, 0}, - {0, QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG, 0}, - {0, QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG, 0}, - {0, QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG, 0}, - {0, QCA6390_WLAON_MEM_CNT_SEL_REG, 0}, - {0, QCA6390_WLAON_MEM_NO_EXTBHS_REG, 0}, - {0, QCA6390_WLAON_MEM_DEBUG_REG, 0}, - {0, QCA6390_WLAON_MEM_DEBUG_BUS_REG, 0}, - {0, QCA6390_WLAON_MEM_REDUN_CFG_REG, 0}, - {0, QCA6390_WLAON_WL_AON_SPARE2, 0}, - {0, QCA6390_WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG, 0}, - {0, QCA6390_WLAON_BTFM_WLAN_IPC_STATUS_REG, 0}, - {0, QCA6390_WLAON_MPM_COUNTER_CHICKEN_BITS, 0}, - {0, QCA6390_WLAON_WLPM_CHICKEN_BITS, 0}, - {0, QCA6390_WLAON_PCIE_PHY_PWR_REG, 0}, - {0, QCA6390_WLAON_WL_CLK_CNTL_PMU_LPO2M_REG, 0}, - {0, QCA6390_WLAON_WL_SS_ROOT_CLK_SWITCH_REG, 0}, - {0, QCA6390_WLAON_POWERCTRL_PMU_REG, 0}, - {0, QCA6390_WLAON_POWERCTRL_MEM_REG, 0}, - {0, QCA6390_WLAON_PCIE_PWR_CTRL_REG, 0}, - {0, QCA6390_WLAON_SOC_PWR_PROFILE_REG, 0}, - {0, QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG, 0}, - {0, QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG, 0}, - {0, QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG, 0}, - {0, QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG, 0}, - {0, QCA6390_WLAON_MEM_SVS_CFG_REG, 0}, - {0, QCA6390_WLAON_CMN_AON_MISC_REG, 0}, - {0, QCA6390_WLAON_INTR_STATUS, 0}, - {0, QCA6390_SYSPM_SYSPM_PWR_STATUS, 0}, - {0, QCA6390_SYSPM_DBG_BTFM_AON_REG, 0}, - {0, QCA6390_SYSPM_DBG_BUS_SEL_REG, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, - {0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {3, 0, WLAON_SOC_POWER_CTRL, 0}, + {3, 0, WLAON_SOC_PWR_WDG_BARK_THRSHD, 0}, + {3, 0, WLAON_SOC_PWR_WDG_BITE_THRSHD, 0}, + {3, 0, WLAON_SW_COLD_RESET, 0}, + {3, 0, WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE, 0}, + {3, 0, WLAON_GDSC_DELAY_SETTING, 0}, + {3, 0, WLAON_GDSC_DELAY_SETTING2, 0}, + {3, 0, WLAON_WL_PWR_STATUS_REG, 0}, + {3, 0, WLAON_WL_AON_DBG_CFG_REG, 0}, + {2, 0, WLAON_WL_AON_DBG_ENABLE_GRP0_REG, 0}, + {2, 0, WLAON_WL_AON_DBG_ENABLE_GRP1_REG, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL0, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL1, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL2, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL3, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL4, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL5, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL5_1, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL6, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL6_1, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL7, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL8, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL8_1, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL9, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL9_1, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL10, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL11, 0}, + {2, 0, WLAON_WL_AON_APM_CFG_CTRL12, 0}, + {2, 0, WLAON_WL_AON_APM_OVERRIDE_REG, 0}, + {2, 0, WLAON_WL_AON_CXPC_REG, 0}, + {2, 0, WLAON_WL_AON_APM_STATUS0, 0}, + {2, 0, WLAON_WL_AON_APM_STATUS1, 0}, + {2, 0, WLAON_WL_AON_APM_STATUS2, 0}, + {2, 0, WLAON_WL_AON_APM_STATUS3, 0}, + {2, 0, WLAON_WL_AON_APM_STATUS4, 0}, + {2, 0, WLAON_WL_AON_APM_STATUS5, 0}, + {2, 0, WLAON_WL_AON_APM_STATUS6, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL1, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL6, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL7, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL3, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL4, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL5, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL8, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL2, 0}, + {3, 0, WLAON_GLOBAL_COUNTER_CTRL9, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL1, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL2, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL3, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL4, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL5, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL6, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL7, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL8, 0}, + {3, 0, WLAON_RTC_CLK_CAL_CTRL9, 0}, + {3, 0, WLAON_WCSSAON_CONFIG_REG, 0}, + {3, 0, WLAON_WLAN_OEM_DEBUG_REG, 0}, + {3, 0, WLAON_WLAN_RAM_DUMP_REG, 0}, + {3, 0, WLAON_QDSS_WCSS_REG, 0}, + {3, 0, WLAON_QDSS_WCSS_ACK, 0}, + {3, 0, WLAON_WL_CLK_CNTL_KDF_REG, 0}, + {3, 0, WLAON_WL_CLK_CNTL_PMU_HFRC_REG, 0}, + {3, 0, WLAON_QFPROM_PWR_CTRL_REG, 0}, + {3, 0, WLAON_DLY_CONFIG, 0}, + {3, 0, WLAON_WLAON_Q6_IRQ_REG, 0}, + {3, 0, WLAON_PCIE_INTF_SW_CFG_REG, 0}, + {3, 0, WLAON_PCIE_INTF_STICKY_SW_CFG_REG, 0}, + {3, 0, WLAON_PCIE_INTF_PHY_SW_CFG_REG, 0}, + {3, 0, WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG, 0}, + {3, 0, WLAON_Q6_COOKIE_BIT, 0}, + {3, 0, WLAON_WARM_SW_ENTRY, 0}, + {3, 0, WLAON_RESET_DBG_SW_ENTRY, 0}, + {3, 0, WLAON_WL_PMUNOC_CFG_REG, 0}, + {3, 0, WLAON_RESET_CAUSE_CFG_REG, 0}, + {3, 0, WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG, 0}, + {3, 0, WLAON_DEBUG, 0}, + {3, 0, WLAON_SOC_PARAMETERS, 0}, + {3, 0, WLAON_WLPM_SIGNAL, 0}, + {3, 0, WLAON_SOC_RESET_CAUSE_REG, 0}, + {3, 0, WLAON_WAKEUP_PCIE_SOC_REG, 0}, + {3, 0, WLAON_PBL_STACK_CANARY, 0}, + {3, 0, WLAON_MEM_TOT_NUM_GRP_REG, 0}, + {3, 0, WLAON_MEM_TOT_BANKS_IN_GRP0_REG, 0}, + {3, 0, WLAON_MEM_TOT_BANKS_IN_GRP1_REG, 0}, + {3, 0, WLAON_MEM_TOT_BANKS_IN_GRP2_REG, 0}, + {3, 0, WLAON_MEM_TOT_BANKS_IN_GRP3_REG, 0}, + {3, 0, WLAON_MEM_TOT_SIZE_IN_GRP0_REG, 0}, + {3, 0, WLAON_MEM_TOT_SIZE_IN_GRP1_REG, 0}, + {3, 0, WLAON_MEM_TOT_SIZE_IN_GRP2_REG, 0}, + {3, 0, WLAON_MEM_TOT_SIZE_IN_GRP3_REG, 0}, + {3, 0, WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG, 0}, + {3, 0, WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG, 0}, + {3, 0, WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG, 0}, + {3, 0, WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG, 0}, + {3, 0, WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG, 0}, + {3, 0, WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG, 0}, + {3, 0, WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG, 0}, + {3, 0, WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG, 0}, + {3, 0, WLAON_MEM_CNT_SEL_REG, 0}, + {3, 0, WLAON_MEM_NO_EXTBHS_REG, 0}, + {3, 0, WLAON_MEM_DEBUG_REG, 0}, + {3, 0, WLAON_MEM_DEBUG_BUS_REG, 0}, + {3, 0, WLAON_MEM_REDUN_CFG_REG, 0}, + {3, 0, WLAON_WL_AON_SPARE2, 0}, + {3, 0, WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG, 0}, + {3, 0, WLAON_BTFM_WLAN_IPC_STATUS_REG, 0}, + {3, 0, WLAON_MPM_COUNTER_CHICKEN_BITS, 0}, + {3, 0, WLAON_WLPM_CHICKEN_BITS, 0}, + {3, 0, WLAON_PCIE_PHY_PWR_REG, 0}, + {3, 0, WLAON_WL_CLK_CNTL_PMU_LPO2M_REG, 0}, + {3, 0, WLAON_WL_SS_ROOT_CLK_SWITCH_REG, 0}, + {3, 0, WLAON_POWERCTRL_PMU_REG, 0}, + {3, 0, WLAON_POWERCTRL_MEM_REG, 0}, + {3, 0, WLAON_PCIE_PWR_CTRL_REG, 0}, + {3, 0, WLAON_SOC_PWR_PROFILE_REG, 0}, + {3, 0, WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG, 0}, + {3, 0, WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG, 0}, + {3, 0, WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG, 0}, + {3, 0, WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG, 0}, + {3, 0, WLAON_MEM_SVS_CFG_REG, 0}, + {3, 0, WLAON_CMN_AON_MISC_REG, 0}, + {3, 0, WLAON_INTR_STATUS, 0}, + {2, 0, WLAON_INTR_ENABLE, 0}, + {2, 0, WLAON_NOC_DBG_BUS_SEL_REG, 0}, + {2, 0, WLAON_NOC_DBG_BUS_REG, 0}, + {2, 0, WLAON_WL_CTRL_MISC_REG, 0}, + {2, 0, WLAON_DBG_STATUS0, 0}, + {2, 0, WLAON_DBG_STATUS1, 0}, + {2, 0, WLAON_TIMERSYNC_OFFSET_L, 0}, + {2, 0, WLAON_TIMERSYNC_OFFSET_H, 0}, + {2, 0, WLAON_PMU_LDO_SETTLE_REG, 0}, +}; + +static struct cnss_misc_reg syspm_reg_access_seq[] = { + {1, 0, QCA6390_SYSPM_SYSPM_PWR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_DBG_BTFM_AON_REG, 0}, + {1, 0, QCA6390_SYSPM_DBG_BUS_SEL_REG, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, + {1, 0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0}, }; #define WCSS_REG_SIZE ARRAY_SIZE(wcss_reg_access_seq) #define PCIE_REG_SIZE ARRAY_SIZE(pcie_reg_access_seq) #define WLAON_REG_SIZE ARRAY_SIZE(wlaon_reg_access_seq) +#define SYSPM_REG_SIZE ARRAY_SIZE(syspm_reg_access_seq) #if IS_ENABLED(CONFIG_PCI_MSM) /** @@ -1892,16 +1930,15 @@ static void cnss_pci_set_wlaon_pwr_ctrl(struct cnss_pci_data *pci_priv, if (cnss_pci_force_wake_get(pci_priv)) return; - ret = cnss_pci_reg_read(pci_priv, QCA6390_WLAON_QFPROM_PWR_CTRL_REG, - &val); + ret = cnss_pci_reg_read(pci_priv, WLAON_QFPROM_PWR_CTRL_REG, &val); if (ret) { cnss_pr_err("Failed to read register offset 0x%x, err = %d\n", - QCA6390_WLAON_QFPROM_PWR_CTRL_REG, ret); + WLAON_QFPROM_PWR_CTRL_REG, ret); goto force_wake_put; } cnss_pr_dbg("Read register offset 0x%x, val = 0x%x\n", - QCA6390_WLAON_QFPROM_PWR_CTRL_REG, val); + WLAON_QFPROM_PWR_CTRL_REG, val); if (set_vddd4blow) val |= QFPROM_PWR_CTRL_VDD4BLOW_SW_EN_MASK; @@ -1913,16 +1950,15 @@ static void cnss_pci_set_wlaon_pwr_ctrl(struct cnss_pci_data *pci_priv, else val &= ~QFPROM_PWR_CTRL_SHUTDOWN_EN_MASK; - ret = cnss_pci_reg_write(pci_priv, QCA6390_WLAON_QFPROM_PWR_CTRL_REG, - val); + ret = cnss_pci_reg_write(pci_priv, WLAON_QFPROM_PWR_CTRL_REG, val); if (ret) { cnss_pr_err("Failed to write register offset 0x%x, err = %d\n", - QCA6390_WLAON_QFPROM_PWR_CTRL_REG, ret); + WLAON_QFPROM_PWR_CTRL_REG, ret); goto force_wake_put; } cnss_pr_dbg("Write val 0x%x to register offset 0x%x\n", val, - QCA6390_WLAON_QFPROM_PWR_CTRL_REG); + WLAON_QFPROM_PWR_CTRL_REG); if (set_shutdown) usleep_range(WLAON_PWR_CTRL_SHUTDOWN_DELAY_MIN_US, @@ -1945,8 +1981,8 @@ static int cnss_pci_get_device_timestamp(struct cnss_pci_data *pci_priv, return -EINVAL; } - cnss_pci_reg_read(pci_priv, QCA6390_WLAON_GLOBAL_COUNTER_CTRL3, &low); - cnss_pci_reg_read(pci_priv, QCA6390_WLAON_GLOBAL_COUNTER_CTRL4, &high); + cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL3, &low); + cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL4, &high); device_ticks = (u64)high << 32 | low; do_div(device_ticks, plat_priv->device_freq_hz / 100000); @@ -1957,13 +1993,13 @@ static int cnss_pci_get_device_timestamp(struct cnss_pci_data *pci_priv, static void cnss_pci_enable_time_sync_counter(struct cnss_pci_data *pci_priv) { - cnss_pci_reg_write(pci_priv, QCA6390_WLAON_GLOBAL_COUNTER_CTRL5, + cnss_pci_reg_write(pci_priv, WLAON_GLOBAL_COUNTER_CTRL5, QCA6390_TIME_SYNC_ENABLE); } static void cnss_pci_clear_time_sync_counter(struct cnss_pci_data *pci_priv) { - cnss_pci_reg_write(pci_priv, QCA6390_WLAON_GLOBAL_COUNTER_CTRL5, + cnss_pci_reg_write(pci_priv, WLAON_GLOBAL_COUNTER_CTRL5, QCA6390_TIME_SYNC_CLEAR); } @@ -2256,6 +2292,8 @@ static void cnss_pci_misc_reg_dump(struct cnss_pci_data *pci_priv, u32 misc_reg_size, char *reg_name) { + struct cnss_plat_data *plat_priv = pci_priv->plat_priv; + bool do_force_wake_put = true; int i; if (!misc_reg) @@ -2267,12 +2305,20 @@ static void cnss_pci_misc_reg_dump(struct cnss_pci_data *pci_priv, if (cnss_pci_check_link_status(pci_priv)) return; - if (cnss_pci_force_wake_get(pci_priv)) - return; + if (cnss_pci_force_wake_get(pci_priv)) { + /* Continue to dump when device has entered RDDM already */ + if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state)) + return; + do_force_wake_put = false; + } - cnss_pr_dbg("start to dump %s registers\n", reg_name); + cnss_pr_dbg("Start to dump %s registers\n", reg_name); for (i = 0; i < misc_reg_size; i++) { + if (!test_bit(pci_priv->misc_reg_dev_mask, + &misc_reg[i].dev_mask)) + continue; + if (misc_reg[i].wr) { if (misc_reg[i].offset == QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG && @@ -2293,14 +2339,12 @@ static void cnss_pci_misc_reg_dump(struct cnss_pci_data *pci_priv, misc_reg[i].offset, &misc_reg[i].val)) goto force_wake_put; - cnss_pr_vdbg("Read 0x%X from 0x%X\n", - misc_reg[i].val, - misc_reg[i].offset); } } force_wake_put: - cnss_pci_force_wake_put(pci_priv); + if (do_force_wake_put) + cnss_pci_force_wake_put(pci_priv); } static void cnss_pci_dump_misc_reg(struct cnss_pci_data *pci_priv) @@ -2311,13 +2355,14 @@ static void cnss_pci_dump_misc_reg(struct cnss_pci_data *pci_priv) if (cnss_pci_check_link_status(pci_priv)) return; - mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_misc_reg_dump(pci_priv, pci_priv->wcss_reg, - pci_priv->wcss_reg_size, "wcss"); + WCSS_REG_SIZE, "wcss"); cnss_pci_misc_reg_dump(pci_priv, pci_priv->pcie_reg, - pci_priv->pcie_reg_size, "pcie"); + PCIE_REG_SIZE, "pcie"); cnss_pci_misc_reg_dump(pci_priv, pci_priv->wlaon_reg, - pci_priv->wlaon_reg_size, "wlaon"); + WLAON_REG_SIZE, "wlaon"); + cnss_pci_misc_reg_dump(pci_priv, pci_priv->syspm_reg, + SYSPM_REG_SIZE, "syspm"); } static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv) @@ -4620,6 +4665,8 @@ static void cnss_pci_dump_qdss_reg(struct cnss_pci_data *pci_priv) return; } + cnss_pr_dbg("Start to dump qdss registers\n"); + for (i = 0; qdss_csr[i].name; i++) { reg_offset = QDSS_APB_DEC_CSR_BASE + qdss_csr[i].offset; if (cnss_pci_reg_read(pci_priv, reg_offset, @@ -4673,13 +4720,13 @@ static void cnss_pci_dump_ce_reg(struct cnss_pci_data *pci_priv, } } -static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv) +static void cnss_pci_dump_debug_reg(struct cnss_pci_data *pci_priv) { - cnss_pr_dbg("Start to dump debug registers\n"); - if (cnss_pci_check_link_status(pci_priv)) return; + cnss_pr_dbg("Start to dump debug registers\n"); + mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON); cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09); @@ -4710,6 +4757,7 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv) return 0; } + mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_dump_misc_reg(pci_priv); cnss_pci_dump_shadow_reg(pci_priv); @@ -4721,7 +4769,7 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv) return 0; } cnss_fatal_err("Failed to trigger RDDM, err = %d\n", ret); - cnss_pci_dump_registers(pci_priv); + cnss_pci_dump_debug_reg(pci_priv); cnss_schedule_recovery(&pci_priv->pci_dev->dev, CNSS_REASON_DEFAULT); return ret; @@ -4883,6 +4931,7 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic) return; } + mhi_debug_reg_dump(pci_priv->mhi_ctrl); cnss_pci_dump_misc_reg(pci_priv); cnss_pci_dump_shadow_reg(pci_priv); cnss_pci_dump_qdss_reg(pci_priv); @@ -4891,7 +4940,7 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic) if (ret) { cnss_fatal_err("Failed to download RDDM image, err = %d\n", ret); - cnss_pci_dump_registers(pci_priv); + cnss_pci_dump_debug_reg(pci_priv); return; } @@ -5450,12 +5499,11 @@ static void cnss_pci_config_regs(struct cnss_pci_data *pci_priv) { switch (pci_priv->device_id) { case QCA6390_DEVICE_ID: + pci_priv->misc_reg_dev_mask = REG_MASK_QCA6390; pci_priv->wcss_reg = wcss_reg_access_seq; - pci_priv->wcss_reg_size = WCSS_REG_SIZE; pci_priv->pcie_reg = pcie_reg_access_seq; - pci_priv->pcie_reg_size = PCIE_REG_SIZE; pci_priv->wlaon_reg = wlaon_reg_access_seq; - pci_priv->wlaon_reg_size = WLAON_REG_SIZE; + pci_priv->syspm_reg = syspm_reg_access_seq; /* Configure WDOG register with specific value so that we can * know if HW is in the process of WDOG reset recovery or not @@ -5466,6 +5514,10 @@ static void cnss_pci_config_regs(struct cnss_pci_data *pci_priv) QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG, QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG_VAL); break; + case QCA6490_DEVICE_ID: + pci_priv->misc_reg_dev_mask = REG_MASK_QCA6490; + pci_priv->wlaon_reg = wlaon_reg_access_seq; + break; default: return; } diff --git a/drivers/net/wireless/cnss2/pci.h b/drivers/net/wireless/cnss2/pci.h index e801d32e02e8..8528be806119 100644 --- a/drivers/net/wireless/cnss2/pci.h +++ b/drivers/net/wireless/cnss2/pci.h @@ -39,6 +39,12 @@ enum cnss_rtpm_id { RTPM_ID_MAX, }; +enum cnss_pci_reg_dev_mask { + REG_MASK_QCA6390, + REG_MASK_QCA6490, + REG_MASK_WCN7850, +}; + struct cnss_msi_user { char *name; int num_vectors; @@ -62,6 +68,7 @@ struct cnss_pci_debug_reg { }; struct cnss_misc_reg { + unsigned long dev_mask; u8 wr; u32 offset; u32 val; @@ -122,11 +129,10 @@ struct cnss_pci_data { struct mutex bus_lock; /* mutex for suspend and resume bus */ struct cnss_pci_debug_reg *debug_reg; struct cnss_misc_reg *wcss_reg; - u32 wcss_reg_size; struct cnss_misc_reg *pcie_reg; - u32 pcie_reg_size; struct cnss_misc_reg *wlaon_reg; - u32 wlaon_reg_size; + struct cnss_misc_reg *syspm_reg; + unsigned long misc_reg_dev_mask; u8 iommu_geometry; bool drv_supported; }; diff --git a/drivers/net/wireless/cnss2/reg.h b/drivers/net/wireless/cnss2/reg.h index 1c8c12e72a15..f5cbc0d903d6 100644 --- a/drivers/net/wireless/cnss2/reg.h +++ b/drivers/net/wireless/cnss2/reg.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef _CNSS_REG_H #define _CNSS_REG_H @@ -48,9 +48,6 @@ #define QCA6390_PCIE_SHADOW_REG_VALUE_0 0x8FC #define QCA6390_PCIE_SHADOW_REG_VALUE_34 0x984 #define QCA6390_PCIE_SHADOW_REG_VALUE_35 0x988 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120 #define SHADOW_REG_INTER_COUNT 43 #define QCA6390_PCIE_SHADOW_REG_INTER_0 0x1E05000 @@ -165,102 +162,139 @@ #define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_APS_STATUS_REG1 0x00B600B0 #define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1 0x00B60044 -#define QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG 0x01F806C4 -#define QCA6390_WLAON_SOC_POWER_CTRL 0x01F80000 -#define QCA6390_WLAON_PCIE_PWR_CTRL_REG 0x01F806BC -#define QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG 0x1F806C8 -#define QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG 0x1F806CC -#define QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG 0x1F806D0 -#define QCA6390_WLAON_SOC_PWR_WDG_BARK_THRSHD 0x1F80004 -#define QCA6390_WLAON_SOC_PWR_WDG_BITE_THRSHD 0x1F80008 -#define QCA6390_WLAON_SW_COLD_RESET 0x1F8000C -#define QCA6390_WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE 0x1F8001C -#define QCA6390_WLAON_GDSC_DELAY_SETTING 0x1F80024 -#define QCA6390_WLAON_GDSC_DELAY_SETTING2 0x1F80028 -#define QCA6390_WLAON_WL_PWR_STATUS_REG 0x1F8002C -#define QCA6390_WLAON_WL_AON_DBG_CFG_REG 0x1F80030 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL1 0x1F80100 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL6 0x1F80108 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL7 0x1F8010C -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL8 0x1F801F0 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL2 0x1F801F4 -#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL9 0x1F801F8 -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL1 0x1F80200 -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL2 0x1F80204 -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL3 0x1F80208 -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL4 0x1F8020C -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL5 0x1F80210 -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL6 0x1F80214 -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL7 0x1F80218 -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL8 0x1F8021C -#define QCA6390_WLAON_RTC_CLK_CAL_CTRL9 0x1F80220 -#define QCA6390_WLAON_WCSSAON_CONFIG_REG 0x1F80300 -#define QCA6390_WLAON_WLAN_OEM_DEBUG_REG 0x1F80304 -#define QCA6390_WLAON_WLAN_RAM_DUMP_REG 0x1F80308 -#define QCA6390_WLAON_QDSS_WCSS_REG 0x1F8030C -#define QCA6390_WLAON_QDSS_WCSS_ACK 0x1F80310 -#define QCA6390_WLAON_WL_CLK_CNTL_KDF_REG 0x1F80314 -#define QCA6390_WLAON_WL_CLK_CNTL_PMU_HFRC_REG 0x1F80318 -#define QCA6390_WLAON_QFPROM_PWR_CTRL_REG 0x1F8031C +#define WLAON_SOC_POWER_CTRL 0x01F80000 +#define WLAON_SOC_PWR_WDG_BARK_THRSHD 0x1F80004 +#define WLAON_SOC_PWR_WDG_BITE_THRSHD 0x1F80008 +#define WLAON_SW_COLD_RESET 0x1F8000C +#define WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE 0x1F8001C +#define WLAON_GDSC_DELAY_SETTING 0x1F80024 +#define WLAON_GDSC_DELAY_SETTING2 0x1F80028 +#define WLAON_WL_PWR_STATUS_REG 0x1F8002C +#define WLAON_WL_AON_DBG_CFG_REG 0x1F80030 +#define WLAON_WL_AON_DBG_ENABLE_GRP0_REG 0x1F80034 +#define WLAON_WL_AON_DBG_ENABLE_GRP1_REG 0x1F80038 +#define WLAON_WL_AON_APM_CFG_CTRL0 0x1F80040 +#define WLAON_WL_AON_APM_CFG_CTRL1 0x1F80044 +#define WLAON_WL_AON_APM_CFG_CTRL2 0x1F80048 +#define WLAON_WL_AON_APM_CFG_CTRL3 0x1F8004C +#define WLAON_WL_AON_APM_CFG_CTRL4 0x1F80050 +#define WLAON_WL_AON_APM_CFG_CTRL5 0x1F80054 +#define WLAON_WL_AON_APM_CFG_CTRL5_1 0x1F80058 +#define WLAON_WL_AON_APM_CFG_CTRL6 0x1F8005C +#define WLAON_WL_AON_APM_CFG_CTRL6_1 0x1F80060 +#define WLAON_WL_AON_APM_CFG_CTRL7 0x1F80064 +#define WLAON_WL_AON_APM_CFG_CTRL8 0x1F80068 +#define WLAON_WL_AON_APM_CFG_CTRL8_1 0x1F8006C +#define WLAON_WL_AON_APM_CFG_CTRL9 0x1F80070 +#define WLAON_WL_AON_APM_CFG_CTRL9_1 0x1F80074 +#define WLAON_WL_AON_APM_CFG_CTRL10 0x1F80078 +#define WLAON_WL_AON_APM_CFG_CTRL11 0x1F8007C +#define WLAON_WL_AON_APM_CFG_CTRL12 0x1F80080 +#define WLAON_WL_AON_APM_OVERRIDE_REG 0x1F800B0 +#define WLAON_WL_AON_CXPC_REG 0x1F800B4 +#define WLAON_WL_AON_APM_STATUS0 0x1F800C0 +#define WLAON_WL_AON_APM_STATUS1 0x1F800C4 +#define WLAON_WL_AON_APM_STATUS2 0x1F800C8 +#define WLAON_WL_AON_APM_STATUS3 0x1F800CC +#define WLAON_WL_AON_APM_STATUS4 0x1F800D0 +#define WLAON_WL_AON_APM_STATUS5 0x1F800D4 +#define WLAON_WL_AON_APM_STATUS6 0x1F800D8 +#define WLAON_GLOBAL_COUNTER_CTRL1 0x1F80100 +#define WLAON_GLOBAL_COUNTER_CTRL6 0x1F80108 +#define WLAON_GLOBAL_COUNTER_CTRL7 0x1F8010C +#define WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118 +#define WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C +#define WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120 +#define WLAON_GLOBAL_COUNTER_CTRL8 0x1F801F0 +#define WLAON_GLOBAL_COUNTER_CTRL2 0x1F801F4 +#define WLAON_GLOBAL_COUNTER_CTRL9 0x1F801F8 +#define WLAON_RTC_CLK_CAL_CTRL1 0x1F80200 +#define WLAON_RTC_CLK_CAL_CTRL2 0x1F80204 +#define WLAON_RTC_CLK_CAL_CTRL3 0x1F80208 +#define WLAON_RTC_CLK_CAL_CTRL4 0x1F8020C +#define WLAON_RTC_CLK_CAL_CTRL5 0x1F80210 +#define WLAON_RTC_CLK_CAL_CTRL6 0x1F80214 +#define WLAON_RTC_CLK_CAL_CTRL7 0x1F80218 +#define WLAON_RTC_CLK_CAL_CTRL8 0x1F8021C +#define WLAON_RTC_CLK_CAL_CTRL9 0x1F80220 +#define WLAON_WCSSAON_CONFIG_REG 0x1F80300 +#define WLAON_WLAN_OEM_DEBUG_REG 0x1F80304 +#define WLAON_WLAN_RAM_DUMP_REG 0x1F80308 +#define WLAON_QDSS_WCSS_REG 0x1F8030C +#define WLAON_QDSS_WCSS_ACK 0x1F80310 +#define WLAON_WL_CLK_CNTL_KDF_REG 0x1F80314 +#define WLAON_WL_CLK_CNTL_PMU_HFRC_REG 0x1F80318 +#define WLAON_QFPROM_PWR_CTRL_REG 0x1F8031C #define QFPROM_PWR_CTRL_VDD4BLOW_SW_EN_MASK 0x4 #define QFPROM_PWR_CTRL_SHUTDOWN_EN_MASK 0x1 -#define QCA6390_WLAON_DLY_CONFIG 0x1F80400 -#define QCA6390_WLAON_WLAON_Q6_IRQ_REG 0x1F80404 -#define QCA6390_WLAON_PCIE_INTF_SW_CFG_REG 0x1F80408 -#define QCA6390_WLAON_PCIE_INTF_STICKY_SW_CFG_REG 0x1F8040C -#define QCA6390_WLAON_PCIE_INTF_PHY_SW_CFG_REG 0x1F80410 -#define QCA6390_WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG 0x1F80414 -#define QCA6390_WLAON_Q6_COOKIE_BIT 0x1F80500 -#define QCA6390_WLAON_WARM_SW_ENTRY 0x1F80504 -#define QCA6390_WLAON_RESET_DBG_SW_ENTRY 0x1F80508 -#define QCA6390_WLAON_WL_PMUNOC_CFG_REG 0x1F8050C -#define QCA6390_WLAON_RESET_CAUSE_CFG_REG 0x1F80510 -#define QCA6390_WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG 0x1F80514 -#define QCA6390_WLAON_DEBUG 0x1F80600 -#define QCA6390_WLAON_SOC_PARAMETERS 0x1F80604 -#define QCA6390_WLAON_WLPM_SIGNAL 0x1F80608 -#define QCA6390_WLAON_SOC_RESET_CAUSE_REG 0x1F8060C -#define QCA6390_WLAON_WAKEUP_PCIE_SOC_REG 0x1F80610 -#define QCA6390_WLAON_PBL_STACK_CANARY 0x1F80614 -#define QCA6390_WLAON_MEM_TOT_NUM_GRP_REG 0x1F80618 -#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP0_REG 0x1F8061C -#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP1_REG 0x1F80620 -#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP2_REG 0x1F80624 -#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP3_REG 0x1F80628 -#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP0_REG 0x1F8062C -#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP1_REG 0x1F80630 -#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP2_REG 0x1F80634 -#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP3_REG 0x1F80638 -#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG 0x1F8063C -#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG 0x1F80640 -#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG 0x1F80644 -#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG 0x1F80648 -#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG 0x1F8064C -#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG 0x1F80650 -#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG 0x1F80654 -#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG 0x1F80658 -#define QCA6390_WLAON_MEM_CNT_SEL_REG 0x1F8065C -#define QCA6390_WLAON_MEM_NO_EXTBHS_REG 0x1F80660 -#define QCA6390_WLAON_MEM_DEBUG_REG 0x1F80664 -#define QCA6390_WLAON_MEM_DEBUG_BUS_REG 0x1F80668 -#define QCA6390_WLAON_MEM_REDUN_CFG_REG 0x1F8066C -#define QCA6390_WLAON_WL_AON_SPARE2 0x1F80670 -#define QCA6390_WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG 0x1F80680 -#define QCA6390_WLAON_BTFM_WLAN_IPC_STATUS_REG 0x1F80690 -#define QCA6390_WLAON_MPM_COUNTER_CHICKEN_BITS 0x1F806A0 -#define QCA6390_WLAON_WLPM_CHICKEN_BITS 0x1F806A4 -#define QCA6390_WLAON_PCIE_PHY_PWR_REG 0x1F806A8 -#define QCA6390_WLAON_WL_CLK_CNTL_PMU_LPO2M_REG 0x1F806AC -#define QCA6390_WLAON_WL_SS_ROOT_CLK_SWITCH_REG 0x1F806B0 -#define QCA6390_WLAON_POWERCTRL_PMU_REG 0x1F806B4 -#define QCA6390_WLAON_POWERCTRL_MEM_REG 0x1F806B8 -#define QCA6390_WLAON_SOC_PWR_PROFILE_REG 0x1F806C0 -#define QCA6390_WLAON_MEM_SVS_CFG_REG 0x1F806D4 -#define QCA6390_WLAON_CMN_AON_MISC_REG 0x1F806D8 -#define QCA6390_WLAON_INTR_STATUS 0x1F80700 +#define WLAON_DLY_CONFIG 0x1F80400 +#define WLAON_WLAON_Q6_IRQ_REG 0x1F80404 +#define WLAON_PCIE_INTF_SW_CFG_REG 0x1F80408 +#define WLAON_PCIE_INTF_STICKY_SW_CFG_REG 0x1F8040C +#define WLAON_PCIE_INTF_PHY_SW_CFG_REG 0x1F80410 +#define WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG 0x1F80414 +#define WLAON_Q6_COOKIE_BIT 0x1F80500 +#define WLAON_WARM_SW_ENTRY 0x1F80504 +#define WLAON_RESET_DBG_SW_ENTRY 0x1F80508 +#define WLAON_WL_PMUNOC_CFG_REG 0x1F8050C +#define WLAON_RESET_CAUSE_CFG_REG 0x1F80510 +#define WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG 0x1F80514 +#define WLAON_DEBUG 0x1F80600 +#define WLAON_SOC_PARAMETERS 0x1F80604 +#define WLAON_WLPM_SIGNAL 0x1F80608 +#define WLAON_SOC_RESET_CAUSE_REG 0x1F8060C +#define WLAON_WAKEUP_PCIE_SOC_REG 0x1F80610 +#define WLAON_PBL_STACK_CANARY 0x1F80614 +#define WLAON_MEM_TOT_NUM_GRP_REG 0x1F80618 +#define WLAON_MEM_TOT_BANKS_IN_GRP0_REG 0x1F8061C +#define WLAON_MEM_TOT_BANKS_IN_GRP1_REG 0x1F80620 +#define WLAON_MEM_TOT_BANKS_IN_GRP2_REG 0x1F80624 +#define WLAON_MEM_TOT_BANKS_IN_GRP3_REG 0x1F80628 +#define WLAON_MEM_TOT_SIZE_IN_GRP0_REG 0x1F8062C +#define WLAON_MEM_TOT_SIZE_IN_GRP1_REG 0x1F80630 +#define WLAON_MEM_TOT_SIZE_IN_GRP2_REG 0x1F80634 +#define WLAON_MEM_TOT_SIZE_IN_GRP3_REG 0x1F80638 +#define WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG 0x1F8063C +#define WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG 0x1F80640 +#define WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG 0x1F80644 +#define WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG 0x1F80648 +#define WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG 0x1F8064C +#define WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG 0x1F80650 +#define WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG 0x1F80654 +#define WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG 0x1F80658 +#define WLAON_MEM_CNT_SEL_REG 0x1F8065C +#define WLAON_MEM_NO_EXTBHS_REG 0x1F80660 +#define WLAON_MEM_DEBUG_REG 0x1F80664 +#define WLAON_MEM_DEBUG_BUS_REG 0x1F80668 +#define WLAON_MEM_REDUN_CFG_REG 0x1F8066C +#define WLAON_WL_AON_SPARE2 0x1F80670 +#define WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG 0x1F80680 +#define WLAON_BTFM_WLAN_IPC_STATUS_REG 0x1F80690 +#define WLAON_MPM_COUNTER_CHICKEN_BITS 0x1F806A0 +#define WLAON_WLPM_CHICKEN_BITS 0x1F806A4 +#define WLAON_PCIE_PHY_PWR_REG 0x1F806A8 +#define WLAON_WL_CLK_CNTL_PMU_LPO2M_REG 0x1F806AC +#define WLAON_WL_SS_ROOT_CLK_SWITCH_REG 0x1F806B0 +#define WLAON_POWERCTRL_PMU_REG 0x1F806B4 +#define WLAON_POWERCTRL_MEM_REG 0x1F806B8 +#define WLAON_PCIE_PWR_CTRL_REG 0x01F806BC +#define WLAON_SOC_PWR_PROFILE_REG 0x1F806C0 +#define WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG 0x01F806C4 +#define WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG 0x1F806C8 +#define WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG 0x1F806CC +#define WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG 0x1F806D0 +#define WLAON_MEM_SVS_CFG_REG 0x1F806D4 +#define WLAON_CMN_AON_MISC_REG 0x1F806D8 +#define WLAON_INTR_STATUS 0x1F80700 +#define WLAON_INTR_ENABLE 0x1F807040 +#define WLAON_NOC_DBG_BUS_SEL_REG 0x1F80708 +#define WLAON_NOC_DBG_BUS_REG 0x1F8070C +#define WLAON_WL_CTRL_MISC_REG 0x1F80710 +#define WLAON_DBG_STATUS0 0x1F80720 +#define WLAON_DBG_STATUS1 0x1F80724 +#define WLAON_TIMERSYNC_OFFSET_L 0x1F80730 +#define WLAON_TIMERSYNC_OFFSET_H 0x1F80734 +#define WLAON_PMU_LDO_SETTLE_REG 0x1F80740 #define QCA6390_SYSPM_SYSPM_PWR_STATUS 0x1F82000 #define QCA6390_SYSPM_DBG_BTFM_AON_REG 0x1F82004