From 85c149550cc777735f161f93edbb6abbc4a6a646 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 8 Jun 2020 13:32:34 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Add support for SCM PAS The PIL drivers need to vote for bandwidth across DDR and crypto subsytem, such that the secure world can perform initialization and authorization of the firmware blobs. Hence add a device-tree node indicating the corresponding interconnect. Change-Id: I143d30b2744dfe11d43908a7a01f006cc9115f21 --- qcom/shima.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 36d8b95c6ad2..24ae0ef8f0d8 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -531,6 +531,11 @@ qcom,rtb-size = <0x100000>; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + }; + qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; From 5c5dda42daa8b6a5b17367a464c1c2a7099da84e Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 8 Jun 2020 18:10:20 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Add bus interconnect property for cdsp Update cdsp node with interconnect property. Change-Id: I122824187dd6cfe4dc490604be3ad24b64b4414c --- qcom/shima.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 24ae0ef8f0d8..da4ec9f07137 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1510,6 +1510,8 @@ memory-region = <&pil_cdsp_mem>; qcom,complete-ramdump; + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + /* Inputs from turing */ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, <&cdsp_smp2p_in 0 0>,