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2nd batch of v4.15 features:

Browse source 
- lib/scatterlist updates, use for userptr allocations (Tvrtko)
 - Fixed point wrapper cleanup (Mahesh)
 - Gen9+ transition watermarks, watermark optimization and fixes (Mahesh)
 - Display IPC (Isochronous Priority Control) support (Mahesh)
 - GEM workaround fixes (Oscar)
 - GVT: PCI config sanitize series (Changbin)
 - GVT: Workload submission error handling series (Fred)
 - PSR fixes and refactoring (Rodrigo)
 - HWSP based optimizations (Chris)
 - Private PAT management (Zhi)
 - IRQ handling fixes and refactoring (Ville)
 - Module parameter refactoring and variable name clash fix (Michal)
 - Execlist refactoring, incomplete request unwinding on reset (Chris)
 - GuC scheduling improvements (Michal)
 - OA updates (Lionel)
 - Coffeelake out of alpha support (Rodrigo)
 - seqno fixes (Chris)
 - Execlist refactoring (Mika)
 - DP and DP MST cleanups (Dhinakaran)
 - Cannonlake slice/sublice config (Ben)
 - Numerous fixes all around (Everyone)
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEFWWmW3ewYy4RJOWc05gHnSar7m8FAlnOMGwACgkQ05gHnSar
 7m8UABAAgtpuUdm7IFsQwogtEn7JDbS3Q2LfwpyW2kAkTEdDqIBqAFl27PSTMhCj
 Yk5Q1/uG/cYqx9zdO7mLoCM77YTATlCZT4zTOulRZxhFlKMmSyvFDFE3D99LmLUT
 +pbywT7CCh3J+/Xrjf4S8WKFFsz0DRc6ycXwUim1gNJHURWzlG0A4gJhz8MfnuZF
 JmUsO68o8AL5FY6WmWNOF4vEtnwJqvRS0nUzd1UNqmz8sEGu6jSnrzUy9WpdOzoH
 k0PeNBqTaq8QVvlll1pyF4Xn9czKH6XlNXMA/bnVgCODs/A4E1r6rhnDadVZTI57
 KWePlVXeSuXFvnseINPajQnV8BvXwmcBi0eBBllFMOoo9izXhRz7CAGW+vsZvdsr
 Xxcmo8Qrbv+qBsbkX0TSKmZBFT7eBqUn7Pf+WPZhRG2/DAyKdbhcWJi5BfvPQze4
 73bL60XXQlXSacsgkzOIaGlhH1l7DoFdKnG1gWvdLr25xgbcq0uHHGRtwfK1QFT3
 /3DUOJgzd7uwcTRKkBCL4YkeQSRL4ilRuJhJIOebaElz/KBXSU1lyQQz26dSr6iO
 33WdSYjE09+02kXtsjHFIgFFOuTM8Rl38wuI82DbNiH0rh7houMFKfDUjuOgJh2e
 PuHheX9D/SILFCwCwmDvtS4wAmOe72nnA7zW9rV5VWWINPV75x8=
 =qpkh
 -----END PGP SIGNATURE-----

Merge tag 'drm-intel-next-2017-09-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

2nd batch of v4.15 features:

- lib/scatterlist updates, use for userptr allocations (Tvrtko)
- Fixed point wrapper cleanup (Mahesh)
- Gen9+ transition watermarks, watermark optimization and fixes (Mahesh)
- Display IPC (Isochronous Priority Control) support (Mahesh)
- GEM workaround fixes (Oscar)
- GVT: PCI config sanitize series (Changbin)
- GVT: Workload submission error handling series (Fred)
- PSR fixes and refactoring (Rodrigo)
- HWSP based optimizations (Chris)
- Private PAT management (Zhi)
- IRQ handling fixes and refactoring (Ville)
- Module parameter refactoring and variable name clash fix (Michal)
- Execlist refactoring, incomplete request unwinding on reset (Chris)
- GuC scheduling improvements (Michal)
- OA updates (Lionel)
- Coffeelake out of alpha support (Rodrigo)
- seqno fixes (Chris)
- Execlist refactoring (Mika)
- DP and DP MST cleanups (Dhinakaran)
- Cannonlake slice/sublice config (Ben)
- Numerous fixes all around (Everyone)

* tag 'drm-intel-next-2017-09-29' of git://anongit.freedesktop.org/drm/drm-intel: (168 commits)
  drm/i915: Update DRIVER_DATE to 20170929
  drm/i915: Use memset64() to prefill the GTT page
  drm/i915: Also discard second CRC on gen8+ platforms.
  drm/i915/psr: Set frames before SU entry for psr2
  drm/dp: Add defines for latency in sink
  drm/i915: Allow optimized platform checks
  drm/i915: Avoid using dev_priv->info.gen directly.
  i915: Use %pS printk format for direct addresses
  drm/i915/execlists: Notify context-out for lost requests
  drm/i915/cnl: Add support slice/subslice/eu configs
  drm/i915: Compact device info access by a small re-ordering
  drm/i915: Add IS_PLATFORM macro
  drm/i915/selftests: Try to recover from a wedged GPU during reset tests
  drm/i915/huc: Reorganize HuC authentication
  drm/i915: Fix default values of some modparams
  drm/i915: Extend I915_PARAMS_FOR_EACH with default member value
  drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible
  drm/i915: Enable scanline read based on frame timestamps
  drm/i915/execlists: Microoptimise execlists_cancel_port_request()
  drm/i915: Don't rmw PIPESTAT enable bits
  ...
This commit is contained in:
Dave Airlie 2017-10-12 10:20:03 +10:00
commit c5c7bc71a0
89 changed files with 3665 additions and 2425 deletions
Download patch file Download diff file Expand all files Collapse all files

11
include/uapi/drm/i915_drm.h
View file

@ -1308,14 +1308,16 @@ struct drm_i915_reg_read {
* be specified
*/
__u64 offset;
#define I915_REG_READ_8B_WA BIT(0)
__u64 val; /* Return value */
};
/* Known registers:
*
* Render engine timestamp - 0x2358 + 64bit - gen7+
* - Note this register returns an invalid value if using the default
* single instruction 8byte read, in order to workaround that use
* offset (0x2538 | 1) instead.
* single instruction 8byte read, in order to workaround that pass
* flag I915_REG_READ_8B_WA in offset field.
*
*/
@ -1509,6 +1511,11 @@ struct drm_i915_perf_oa_config {
__u32 n_boolean_regs;
__u32 n_flex_regs;
/*
* These fields are pointers to tuples of u32 values (register
* address, value). For example the expected length of the buffer
* pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
*/
__u64 mux_regs_ptr;
__u64 boolean_regs_ptr;
__u64 flex_regs_ptr;