From c675971a663d36104f673df8eb768a9756c9acb4 Mon Sep 17 00:00:00 2001
From: Raghu Ananya Arabolu <rarabolu@quicinc.com>
Date: Thu, 6 Aug 2020 14:21:16 -0700
Subject: [PATCH] ARM: dts: qcom: Add clocks to access KGSL SMMU register space

Add GPU_CC_CX_GMU_CLK, GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK, GPU_CC_HUB_AON_CLK
and GPU_CC_HUB_CX_INT_CLK clock to the list of clocks to vote for in
order to access the KGSL SMMU register space.

Change-Id: Ia91e01ed4758caff7a050ce41f67247682fc8ebe
---
 qcom/lahaina-gpu.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi
index 00a629d1c01e..bfb36ae6e5ea 100644
--- a/qcom/lahaina-gpu.dtsi
+++ b/qcom/lahaina-gpu.dtsi
@@ -23,10 +23,18 @@
 		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
 			<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
 			<&clock_gpucc GPU_CC_AHB_CLK>,
+			<&clock_gpucc GPU_CC_CX_GMU_CLK>,
+			<&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+			<&clock_gpucc GPU_CC_HUB_AON_CLK>,
+			<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
 			<&clock_aop QDSS_CLK>;
 		clock-names = "gcc_gpu_memnoc_gfx",
 				"gcc_gpu_snoc_dvm_gfx",
 				"gpu_cc_ahb",
+				"gpu_cc_cx_gmu",
+				"gpu_cc_hlos1_vote_gpu_smmu",
+				"gpu_cc_hub_aon",
+				"gpu_cc_hub_cx_int",
 				"apb_pclk";
 
 		qcom,chipid = <0x06060000>;