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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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clk: qcom: Add VIDEOCC clock driver for SM8150
Add the VIDEOCC clock definitions and driver support for SM8150. Change-Id: I7874461de22f3d120d9b4c6594c003fbe2571ecb Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
This commit is contained in:
Veera Vegivada
parent
9ad208e4f1
commit
c6d48fab42
3 changed files with 394 additions and 0 deletions
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@ -317,6 +317,15 @@ config SM_GPUCC_8150
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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config SM_VIDEOCC_8150
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tristate "SM8150 Video Clock Controller"
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select SM_GCC_8150
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help
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Support for the video clock controller on Qualcomm Technologies, Inc.
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SM8150 devices.
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Say Y if you want to support video devices and functionality such as
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video encode/decode.
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config SPMI_PMIC_CLKDIV
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tristate "SPMI PMIC clkdiv Support"
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depends on SPMI || COMPILE_TEST
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@ -77,6 +77,7 @@ obj-$(CONFIG_SM_GCC_SHIMA) += gcc-shima.o
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obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
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obj-$(CONFIG_SM_GPUCC_HOLI) += gpucc-holi.o
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obj-$(CONFIG_SM_GPUCC_SHIMA) += gpucc-shima.o
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obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
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obj-$(CONFIG_SM_VIDEOCC_SHIMA) += videocc-shima.o
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obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
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obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
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384
drivers/clk/qcom/videocc-sm8150.c
Normal file
384
drivers/clk/qcom/videocc-sm8150.c
Normal file
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@ -0,0 +1,384 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,videocc-sm8150.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "reset.h"
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#include "vdd-level-sm8150.h"
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static DEFINE_VDD_REGULATORS(vdd_mm, VDD_MM_NUM, 1, vdd_corner);
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enum {
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P_BI_TCXO,
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P_CHIP_SLEEP_CLK,
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P_CORE_BI_PLL_TEST_SE,
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P_VIDEO_PLL0_OUT_EVEN,
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P_VIDEO_PLL0_OUT_MAIN,
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P_VIDEO_PLL0_OUT_ODD,
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};
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static struct pll_vco trion_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 400 MHz configuration */
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static struct alpha_pll_config video_pll0_config = {
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.l = 0x14,
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.alpha = 0xD555,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002267,
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.config_ctl_hi1_val = 0x00000024,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000002,
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.test_ctl_hi1_val = 0x00000020,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x000000D0,
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};
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static struct clk_alpha_pll video_pll0 = {
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.offset = 0x42c,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
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.config = &video_pll0_config,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "video_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_trion_pll_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct parent_map video_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_PLL0_OUT_MAIN, 1 },
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{ P_VIDEO_PLL0_OUT_EVEN, 2 },
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{ P_VIDEO_PLL0_OUT_ODD, 3 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const struct clk_parent_data video_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo", },
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{ .hw = &video_pll0.clkr.hw },
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{ .hw = &video_pll0.clkr.hw },
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{ .hw = &video_pll0.clkr.hw },
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
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F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(225000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(432000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(480000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static const struct freq_tbl ftbl_video_cc_iris_clk_src_sm8150_v2[] = {
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F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_iris_clk_src = {
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.cmd_rcgr = 0x7f0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_iris_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "video_cc_iris_clk_src",
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.parent_data = video_cc_parent_data_0,
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.num_parents = 5,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 200000000,
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[VDD_LOWER] = 225000000,
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[VDD_LOW] = 300000000,
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[VDD_LOW_L1] = 365000000,
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[VDD_NOMINAL] = 432000000,
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[VDD_HIGH] = 480000000},
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},
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};
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static struct clk_branch video_cc_iris_ahb_clk = {
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.halt_reg = 0x8f4,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x8f4,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_iris_ahb_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &video_cc_iris_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0_core_clk = {
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.halt_reg = 0x890,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x890,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvs0_core_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &video_cc_iris_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1_core_clk = {
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.halt_reg = 0x8d0,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x8d0,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvs1_core_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &video_cc_iris_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvsc_core_clk = {
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.halt_reg = 0x850,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x850,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvsc_core_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &video_cc_iris_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_xo_clk = {
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.halt_reg = 0x984,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x984,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_xo_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *video_cc_sm8150_clocks[] = {
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[VIDEO_PLL0] = &video_pll0.clkr,
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[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
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[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
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[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
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[VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
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[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
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[VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr,
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};
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static const struct qcom_reset_map video_cc_sm8150_resets[] = {
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[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
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[VIDEO_CC_MVS0_BCR] = { 0x870 },
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[VIDEO_CC_MVS1_BCR] = { 0x8b0 },
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[VIDEO_CC_MVSC_BCR] = { 0x810 },
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[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
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};
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static const struct regmap_config video_cc_sm8150_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xb94,
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.fast_io = true,
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};
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static const struct qcom_cc_desc video_cc_sm8150_desc = {
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.config = &video_cc_sm8150_regmap_config,
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.clks = video_cc_sm8150_clocks,
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.num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),
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.resets = video_cc_sm8150_resets,
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.num_resets = ARRAY_SIZE(video_cc_sm8150_resets),
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};
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static const struct of_device_id video_cc_sm8150_match_table[] = {
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{ .compatible = "qcom,sm8150-videocc" },
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{ .compatible = "qcom,sm8150-videocc-v2" },
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{ .compatible = "qcom,sa8155-videocc" },
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{ .compatible = "qcom,sa8155-videocc-v2" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
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static void video_cc_sm8150_fixup_sm8150v2(struct regmap *regmap)
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{
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video_pll0.config->test_ctl_hi_val = 0x00000000;
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video_cc_iris_clk_src.freq_tbl = ftbl_video_cc_iris_clk_src_sm8150_v2;
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video_cc_iris_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] = 240000000;
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video_cc_iris_clk_src.clkr.vdd_data.rate_max[VDD_LOW] = 338000000;
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video_cc_iris_clk_src.clkr.vdd_data.rate_max[VDD_NOMINAL] = 444000000;
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video_cc_iris_clk_src.clkr.vdd_data.rate_max[VDD_HIGH] = 533000000;
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}
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static int video_cc_sm8150_fixup(struct platform_device *pdev,
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struct regmap *regmap)
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{
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const char *compat = NULL;
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int compatlen = 0;
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compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);
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if (!compat || (compatlen <= 0))
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return -EINVAL;
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if (!strcmp(compat, "qcom,sm8150-videocc-v2") ||
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!strcmp(compat, "qcom,sa8155-videocc-v2"))
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video_cc_sm8150_fixup_sm8150v2(regmap);
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return 0;
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}
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static int video_cc_sm8150_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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vdd_mm.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mm");
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if (IS_ERR(vdd_mm.regulator[0])) {
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if (PTR_ERR(vdd_mm.regulator[0]) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n");
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return PTR_ERR(vdd_mm.regulator[0]);
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}
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pm_runtime_enable(&pdev->dev);
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ret = pm_clk_create(&pdev->dev);
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if (ret)
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goto disable_pm_runtime;
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ret = pm_clk_add(&pdev->dev, "cfg_ahb_clk");
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if (ret < 0) {
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dev_err(&pdev->dev, "Unable to get ahb clock handle\n");
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goto destroy_pm_clk;
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}
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regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
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if (IS_ERR(regmap)) {
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pr_err("Failed to map the Video CC registers\n");
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ret = PTR_ERR(regmap);
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goto destroy_pm_clk;
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}
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ret = video_cc_sm8150_fixup(pdev, regmap);
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if (ret)
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goto destroy_pm_clk;
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clk_trion_pll_configure(&video_pll0, regmap, video_pll0.config);
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ret = qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
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goto destroy_pm_clk;
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}
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dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");
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return 0;
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destroy_pm_clk:
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pm_clk_destroy(&pdev->dev);
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disable_pm_runtime:
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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static const struct dev_pm_ops video_cc_sm8150_pm_ops = {
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SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
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};
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static struct platform_driver video_cc_sm8150_driver = {
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.probe = video_cc_sm8150_probe,
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.driver = {
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.name = "video_cc-sm8150",
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.of_match_table = video_cc_sm8150_match_table,
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.pm = &video_cc_sm8150_pm_ops,
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},
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};
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static int __init video_cc_sm8150_init(void)
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{
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return platform_driver_register(&video_cc_sm8150_driver);
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}
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subsys_initcall(video_cc_sm8150_init);
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static void __exit video_cc_sm8150_exit(void)
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{
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platform_driver_unregister(&video_cc_sm8150_driver);
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}
|
||||
module_exit(video_cc_sm8150_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI VIDEO_CC SM8150 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue